From 128385051afa074c491f4bd8132a3613c3f9d24c Mon Sep 17 00:00:00 2001 From: Akhil R Date: Tue, 27 Sep 2022 15:54:13 +0530 Subject: [PATCH] gpu: host1x: Add SE SID entries for Tegra234. Add Security Engine Stream ID entries in host1x SID table for Tegra234. Bug 3583641 Signed-off-by: Akhil R Change-Id: I5d96478aad8d24208bad92e61942a57c0fd5df1a Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2782822 Reviewed-by: svcacv Reviewed-by: Mikko Perttunen GVS: Gerrit_Virtual_Submit --- drivers/gpu/host1x/dev.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index acf5130d..80ebf0ef 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -2,7 +2,7 @@ /* * Tegra host1x driver * - * Copyright (c) 2010-2022, NVIDIA Corporation. + * Copyright (c) 2010-2022, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved. */ #include @@ -256,6 +256,42 @@ static const struct host1x_info host1x07_info = { * and firmware stream ID in the MMIO path table. */ static const struct host1x_sid_entry tegra234_sid_table[] = { + { + /* SE1 MMIO */ + .base = 0x1650, + .offset = 0x90, + .limit = 0x90 + }, + { + /* SE2 MMIO */ + .base = 0x1658, + .offset = 0x90, + .limit = 0x90 + }, + { + /* SE4 MMIO */ + .base = 0x1660, + .offset = 0x90, + .limit = 0x90 + }, + { + /* SE1 channel */ + .base = 0x1730, + .offset = 0x90, + .limit = 0x90 + }, + { + /* SE2 channel */ + .base = 0x1738, + .offset = 0x90, + .limit = 0x90 + }, + { + /* SE4 channel */ + .base = 0x1740, + .offset = 0x90, + .limit = 0x90 + }, { /* VIC channel */ .base = 0x17b8,