net: can: mttcan: split 8Mbps for 40MHz and 50MHz

The MTTCAN controller uses different core clock frequencies depending on
the SoC variant: 40MHz for T264 and 50MHz for T194/T234. The 8Mbps data
bitrate needs to be an exact divisor of the clock frequency for proper
operation.

For 40MHz clock: 8Mbps = 8000000 bps (40MHz / 5)
For 50MHz clock: 8Mbps = 8333333 bps (50MHz / 6)

The previous single MTTCAN_SPEED_8MBPS definition (8333333) only worked
correctly for 50MHz clocks and would not divide evenly for 40MHz clocks.

Split MTTCAN_SPEED_8MBPS into two separate defines:
- MTTCAN_SPEED_8MBPS_40MHZ: 8000000 for exact 8Mbps on 40MHz clock
- MTTCAN_SPEED_8MBPS_50MHZ: 8333333 for closest 8Mbps on 50MHz clock

Both values use the same production settings (prod_c_can_8m) and will be
selected based on the chip's configured clock frequency. The 5Mbps rate
remains unchanged as it divides evenly for both clock frequencies.

Bug 5497458

Change-Id: I17190ae6821f89d33e76114f20b91dbd65ba25f2
Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3469194
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Kevin Fu <chunhuaif@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>

drivers/net/can/mttcan/hal/m_ttcan.c

@@ -10,7 +10,8 @@
 #define MTTCAN_INIT_TIMEOUT 1000
 
 #define MTTCAN_SPEED_5MBPS  5000000
-#define MTTCAN_SPEED_8MBPS  8333333
+#define MTTCAN_SPEED_8MBPS_40MHZ  8000000  /* Exact 8 Mbps for 40MHz clock */
+#define MTTCAN_SPEED_8MBPS_50MHZ  8333333  /* Closest to 8 Mbps for 50MHz clock */
 
 void ttcan_print_version(struct ttcan_controller *ttcan)
 {
@@ -302,7 +303,8 @@ static void tegra_mttcan_config_prod_settings(struct mttcan_priv *priv)
 	case MTTCAN_SPEED_5MBPS:
 		prod_name = "prod_c_can_5m";
 		break;
-	case MTTCAN_SPEED_8MBPS:
+	case MTTCAN_SPEED_8MBPS_40MHZ:
+	case MTTCAN_SPEED_8MBPS_50MHZ:
 		prod_name = "prod_c_can_8m";
 		break;
 	default: