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ufs: scsi: enable lane1 rx calibration first

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Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I549a15b2853c1b890aec7e66c5296d56b8616f25
This commit is contained in:
Mallikarjun Kasoju
2024-08-19 03:06:09 +00:00
committed by Jon Hunter
parent 0b489f8588
commit 179dc474f7
1 changed files with 10 additions and 14 deletions
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24
drivers/scsi/ufs/ufs-tegra-common.c
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@@ -41,6 +41,11 @@
#include "ufs-tegra.h" #include "ufs-tegra.h"
#include "ufs-provision.h" #include "ufs-provision.h"
/* Fuse register offset to know if chip is RDL part or not */
#define TEGRA_FUSE_OPT_LOT_CODE_0_0 0x108U
#define NON_RDL_STRUCTURE 0x90570c8
#define NON_RDL_LEAD 0x83c1002
static void ufs_tegra_mphy_startup_sequence(struct ufs_tegra_host *ufs_tegra); static void ufs_tegra_mphy_startup_sequence(struct ufs_tegra_host *ufs_tegra);
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
@@ -158,31 +163,22 @@ static int ufs_tegra_mphy_receiver_calibration(struct ufs_tegra_host *ufs_tegra,
if (ufs_tegra->soc->chip_id >= TEGRA234) { if (ufs_tegra->soc->chip_id >= TEGRA234) {
/* Set RX lane calibration */ /* Set RX lane calibration */
mphy_update(ufs_tegra->mphy_l0_base,
MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, mphy_rx_vendor2_reg);
if (ufs_tegra->x2config == true) { if (ufs_tegra->x2config == true) {
dev_dbg(dev, "%s:x2config is true so invoking mphy_update\n", dev_dbg(dev, "%s:x2config is true so invoking mphy_update\n",
__func__); __func__);
mphy_update(ufs_tegra->mphy_l1_base, mphy_update(ufs_tegra->mphy_l1_base,
MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, MPHY_RX_APB_VENDOR2_0_RX_CAL_EN,
mphy_rx_vendor2_reg); mphy_rx_vendor2_reg);
}
/* TODO: GO bit has to be read back after updating it */
mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT,
mphy_rx_vendor2_reg);
if (ufs_tegra->x2config == true) {
/* TODO: GO bit has to be read back after updating it */ /* TODO: GO bit has to be read back after updating it */
mphy_update(ufs_tegra->mphy_l1_base, mphy_update(ufs_tegra->mphy_l1_base,
MPHY_GO_BIT, mphy_rx_vendor2_reg); MPHY_GO_BIT, mphy_rx_vendor2_reg);
} }
/* Fuse register offset to know if chip is RDL part or not */ mphy_update(ufs_tegra->mphy_l0_base,
#define TEGRA_FUSE_OPT_LOT_CODE_0_0 0x108U MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, mphy_rx_vendor2_reg);
#define NON_RDL_STRUCTURE 0x90570c8 /* TODO: GO bit has to be read back after updating it */
#define NON_RDL_LEAD 0x83c1002 mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT,
mphy_rx_vendor2_reg);
if (ufs_tegra->x2config == true) { if (ufs_tegra->x2config == true) {
/* Wait till lane calibration is done */ /* Wait till lane calibration is done */