From 1a030099f019c0525ce4bc06c77e8111e8ee75a1 Mon Sep 17 00:00:00 2001 From: sreeharim Date: Tue, 23 Apr 2024 21:08:41 -0700 Subject: [PATCH] drivers: PVA : Update the PVE SID - Update the PVE SID to match the GSC access SID for PPE to access the embedded clear code Jira PVAAS-14913 Change-Id: Icc5a6d2a4cd5faf4711134f48d27263cf1d72879 Signed-off-by: sreeharim Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3122900 Tested-by: Omar Nemri Reviewed-by: Omar Nemri GVS: Gerrit_Virtual_Submit --- drivers/video/tegra/host/pva/pva_t264.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/video/tegra/host/pva/pva_t264.h b/drivers/video/tegra/host/pva/pva_t264.h index ec9d2d84..84c9fd45 100644 --- a/drivers/video/tegra/host/pva/pva_t264.h +++ b/drivers/video/tegra/host/pva/pva_t264.h @@ -1,7 +1,8 @@ /* * Tegra Graphics Chip support for T264 * - * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: GPL-2.0+ * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,6 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program. If not, see . + * */ #ifndef __PVA_T264_H__ #define __PVA_T264_H__ @@ -63,7 +65,7 @@ static u32 vm_regs_sid_idx_t264[] = {1, 2, 3, 4, 5, 6, 7, 7, 8, 8, 8, 8, 8, 0, 0, 0}; #else static u32 vm_regs_sid_idx_t264[] = {1, 2, 3, 4, 5, 6, 7, 7, - 8, 0, 9, 8, 8, 0, 0, 0}; + 8, 0, 9, 0, 0, 0, 0, 0}; #endif static u32 vm_regs_reg_idx_t264[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 8, 9, 9, 0, 0, 0};