diff --git a/drivers/misc/mods/Makefile.nvidia b/drivers/misc/mods/Makefile.nvidia
new file mode 100644
index 00000000..95ea2916
--- /dev/null
+++ b/drivers/misc/mods/Makefile.nvidia
@@ -0,0 +1,15 @@
+obj-$(CONFIG_MODS)                 := mods.o
+mods-y                             := mods_krnl.o
+mods-y                             += mods_mem.o
+mods-y                             += mods_irq.o
+mods-y                             += mods_clock.o
+mods-$(CONFIG_ARCH_TEGRA)          += mods_tegraprod.o
+mods-$(CONFIG_PCI)                 += mods_pci.o
+mods-$(CONFIG_ACPI)                += mods_acpi.o
+mods-$(CONFIG_ARCH_TEGRA)	   += mods_dmabuf.o
+mods-$(CONFIG_DMA_ENGINE)          += mods_dma.o
+mods-$(CONFIG_DEBUG_FS)            += mods_debugfs.o
+mods-$(CONFIG_TEGRA_DC)            += mods_tegradc.o
+mods-$(CONFIG_TEGRA_NVADSP)        += mods_adsp.o
+mods-$(CONFIG_NET)                 += mods_netdevice.o
+mods-objs                          := mods.dtb.o
diff --git a/drivers/misc/mods/mods.dts b/drivers/misc/mods/mods.dts
new file mode 100644
index 00000000..818b2b0d
--- /dev/null
+++ b/drivers/misc/mods/mods.dts
@@ -0,0 +1,27 @@
+/*
+ * mods.dts - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+/ {
+	mods {
+		compatible = "nvidia,tegra-mods";
+		status = "okay";
+	};
+};
diff --git a/drivers/misc/mods/mods.h b/drivers/misc/mods/mods.h
new file mode 100644
index 00000000..1d59872b
--- /dev/null
+++ b/drivers/misc/mods/mods.h
@@ -0,0 +1,1188 @@
+/*
+ * mods.h - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2008-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _MODS_H_
+#define _MODS_H_
+
+#include <linux/types.h>
+
+/* Driver version */
+#define MODS_DRIVER_VERSION_MAJOR 3
+#define MODS_DRIVER_VERSION_MINOR 73
+#define MODS_DRIVER_VERSION ((MODS_DRIVER_VERSION_MAJOR << 8) | \
+			     ((MODS_DRIVER_VERSION_MINOR/10) << 4) | \
+			     (MODS_DRIVER_VERSION_MINOR%10))
+
+#pragma pack(push, 1)
+
+/* ************************************************************************* */
+/* ** ESCAPE INTERFACE STRUCTURE					     */
+/* ************************************************************************* */
+
+struct mods_pci_dev_2 {
+	__u16 domain;
+	__u16 bus;
+	__u16 device;
+	__u16 function;
+};
+
+struct mods_pci_dev {
+	__u16 bus;
+	__u8  device;
+	__u8  function;
+};
+
+/* MODS_ESC_ALLOC_PAGES */
+struct MODS_ALLOC_PAGES {
+	/* IN */
+	__u32	num_bytes;
+	__u32	contiguous;
+	__u32	address_bits;
+	__u32	attrib;
+
+	/* OUT */
+	__u64	memory_handle;
+};
+
+/* MODS_ESC_DEVICE_ALLOC_PAGES_2 */
+struct MODS_DEVICE_ALLOC_PAGES_2 {
+	/* IN */
+	__u32			num_bytes;
+	__u32			contiguous;
+	__u32			address_bits;
+	__u32			attrib;
+	struct mods_pci_dev_2 pci_device;
+
+	/* OUT */
+	__u64			memory_handle;
+};
+
+/* MODS_ESC_DEVICE_ALLOC_PAGES */
+struct MODS_DEVICE_ALLOC_PAGES {
+	/* IN */
+	__u32		    num_bytes;
+	__u32		    contiguous;
+	__u32		    address_bits;
+	__u32		    attrib;
+	struct mods_pci_dev pci_device;
+
+	/* OUT */
+	__u64		    memory_handle;
+};
+
+/* MODS_ESC_FREE_PAGES */
+struct MODS_FREE_PAGES {
+	/* IN */
+	__u64	memory_handle;
+};
+
+/* MODS_ESC_GET_PHYSICAL_ADDRESS */
+struct MODS_GET_PHYSICAL_ADDRESS {
+	/* IN */
+	__u64	memory_handle;
+	__u32	offset;
+
+	/* OUT */
+	__u64	physical_address;
+};
+
+/* MODS_ESC_GET_PHYSICAL_ADDRESS */
+struct MODS_GET_PHYSICAL_ADDRESS_2 {
+	/* IN */
+	__u64                 memory_handle;
+	__u32	              offset;
+	struct mods_pci_dev_2 pci_device;
+
+	/* OUT */
+	__u64                 physical_address;
+};
+
+/* MODS_ESC_VIRTUAL_TO_PHYSICAL */
+struct MODS_VIRTUAL_TO_PHYSICAL {
+	/* IN */
+	__u64	virtual_address;
+
+	/* OUT */
+	__u64	physical_address;
+};
+
+/* MODS_ESC_PHYSICAL_TO_VIRTUAL */
+struct MODS_PHYSICAL_TO_VIRTUAL {
+	/* IN */
+	__u64	physical_address;
+
+	/* OUT */
+	__u64	virtual_address;
+
+};
+
+/* MODS_ESC_FLUSH_CACHE_RANGE */
+#define MODS_FLUSH_CPU_CACHE	  1
+#define MODS_INVALIDATE_CPU_CACHE 2
+
+struct MODS_FLUSH_CPU_CACHE_RANGE {
+	/* IN */
+	__u64 virt_addr_start;
+	__u64 virt_addr_end;
+	__u32 flags;
+};
+
+/* MODS_ESC_DMA_MAP_MEMORY */
+struct MODS_DMA_MAP_MEMORY {
+	/* IN */
+	__u64                 memory_handle;
+	struct mods_pci_dev_2 pci_device;
+};
+
+/* MODS_ESC_FIND_PCI_DEVICE_2 */
+struct MODS_FIND_PCI_DEVICE_2 {
+	/* IN */
+	__u32	device_id;
+	__u32	vendor_id;
+	__u32	index;
+
+	/* OUT */
+	struct mods_pci_dev_2 pci_device;
+};
+
+/* MODS_ESC_FIND_PCI_DEVICE */
+struct MODS_FIND_PCI_DEVICE {
+	/* IN */
+	__u32	  device_id;
+	__u32	  vendor_id;
+	__u32	  index;
+
+	/* OUT */
+	__u32	  bus_number;
+	__u32	  device_number;
+	__u32	  function_number;
+};
+
+/* MODS_ESC_FIND_PCI_CLASS_CODE_2 */
+struct MODS_FIND_PCI_CLASS_CODE_2 {
+	/* IN */
+	__u32	class_code;
+	__u32	index;
+
+	/* OUT */
+	struct mods_pci_dev_2 pci_device;
+};
+
+/* MODS_ESC_FIND_PCI_CLASS_CODE */
+struct MODS_FIND_PCI_CLASS_CODE {
+	/* IN */
+	__u32	class_code;
+	__u32	index;
+
+	/* OUT */
+	__u32	bus_number;
+	__u32	device_number;
+	__u32	function_number;
+};
+
+/* MODS_ESC_PCI_GET_BAR_INFO_2 */
+struct MODS_PCI_GET_BAR_INFO_2 {
+	/* IN */
+	struct mods_pci_dev_2 pci_device;
+	__u32			bar_index;
+
+	/* OUT */
+	__u64 base_address;
+	__u64 bar_size;
+};
+
+/* MODS_ESC_PCI_GET_BAR_INFO */
+struct MODS_PCI_GET_BAR_INFO {
+	/* IN */
+	struct mods_pci_dev pci_device;
+	__u32		    bar_index;
+
+	/* OUT */
+	__u64 base_address;
+	__u64 bar_size;
+};
+
+/* MODS_ESC_PCI_GET_IRQ_2 */
+struct MODS_PCI_GET_IRQ_2 {
+	/* IN */
+	struct mods_pci_dev_2 pci_device;
+
+	/* OUT */
+	__u32 irq;
+};
+
+/* MODS_ESC_PCI_GET_IRQ */
+struct MODS_PCI_GET_IRQ {
+	/* IN */
+	struct mods_pci_dev pci_device;
+
+	/* OUT */
+	__u32 irq;
+};
+
+/* MODS_ESC_PCI_READ_2 */
+struct MODS_PCI_READ_2 {
+	/* IN */
+	struct mods_pci_dev_2 pci_device;
+	__u32			address;
+	__u32			data_size;
+
+	/* OUT */
+	__u32			data;
+};
+
+/* MODS_ESC_PCI_READ */
+struct MODS_PCI_READ {
+	/* IN */
+	__u32	bus_number;
+	__u32	device_number;
+	__u32	function_number;
+	__u32	address;
+	__u32	data_size;
+
+	/* OUT */
+	__u32	 data;
+};
+
+/* MODS_ESC_PCI_WRITE_2 */
+struct MODS_PCI_WRITE_2 {
+	/* IN */
+	struct mods_pci_dev_2 pci_device;
+	__u32			address;
+	__u32			data;
+	__u32			data_size;
+};
+
+/* MODS_ESC_PCI_WRITE */
+struct MODS_PCI_WRITE {
+	/* IN */
+	__u32	bus_number;
+	__u32	device_number;
+	__u32	function_number;
+	__u32	address;
+	__u32	data;
+	__u32	data_size;
+};
+
+/* MODS_ESC_PCI_HOT_RESET */
+struct MODS_PCI_HOT_RESET {
+	/* IN */
+	struct mods_pci_dev_2 pci_device;
+};
+
+/* MODS_ESC_SET_PPC_TCE_BYPASS */
+#define MODS_PPC_TCE_BYPASS_DEFAULT  0
+#define MODS_PPC_TCE_BYPASS_ON       1
+#define MODS_PPC_TCE_BYPASS_OFF      2
+struct MODS_SET_PPC_TCE_BYPASS {
+	/* IN */
+	__u8                  mode;
+	__u8                  _dummy_align[7];
+	struct mods_pci_dev_2 pci_device;
+	__u64	              device_dma_mask;
+
+	/* OUT */
+	__u64	              dma_base_address;
+};
+
+/* MODS_ESC_PCI_BUS_ADD_DEVICES*/
+struct MODS_PCI_BUS_ADD_DEVICES {
+	/* IN */
+	__u32	 bus;
+};
+
+/* MODS_ESC_PCI_MAP_RESOURCE */
+struct MODS_PCI_MAP_RESOURCE {
+	/* IN */
+	struct mods_pci_dev_2 local_pci_device;
+	struct mods_pci_dev_2 remote_pci_device;
+	__u32                 resource_index;
+	__u64                 page_count;
+
+	/* IN/OUT */
+	__u64                 va;
+};
+
+/* MODS_ESC_PCI_UNMAP_RESOURCE */
+struct MODS_PCI_UNMAP_RESOURCE {
+	/* IN */
+	struct mods_pci_dev_2 pci_device;
+	__u64                 va;
+};
+
+/* MODS_ESC_PIO_READ */
+struct MODS_PIO_READ {
+	/* IN */
+	__u16	port;
+	__u32	data_size;
+
+	/* OUT */
+	__u32	data;
+};
+
+/* MODS_ESC_PIO_WRITE */
+struct MODS_PIO_WRITE {
+	/* IN */
+	__u16	port;
+	__u32	data;
+	__u32	data_size;
+};
+
+#define INQ_CNT 8
+
+struct mods_irq_data {
+	__u32 irq;
+	__u32 delay;
+};
+
+struct mods_irq_status {
+	struct mods_irq_data data[INQ_CNT];
+	__u32 irqbits:INQ_CNT;
+	__u32 otherirq:1;
+};
+
+/* MODS_ESC_IRQ */
+struct MODS_IRQ {
+	/* IN */
+	__u32 cmd;
+	__u32 size;		/* memory size */
+	__u32 irq;		/* the irq number to be registered in driver */
+
+	/* IN OUT */
+	__u32 channel;		/* application id allocated by driver. */
+
+	/* OUT */
+	struct mods_irq_status stat;	/* for querying irq */
+	__u64		 phys;	/* the memory physical address */
+};
+#define MODS_IRQ_MAX_MASKS 16
+
+/* MODS_ESC_REGISTER_IRQ_3 */
+struct mods_mask_info2 {
+	__u8	mask_type;  /*mask type 32/64 bit access*/
+	__u8	reserved[7]; /*force 64bit alignment */
+	__u32	irq_pending_offset; /* register to read IRQ pending status*/
+	__u32   irq_enabled_offset; /* register to read IRQ enabled status */
+	__u32   irq_enable_offset;  /* register to write to enable IRQs */
+	__u32   irq_disable_offset; /* register to write to disable IRQs */
+	__u64	and_mask;   /*and mask for clearing bits in this register */
+	__u64	or_mask;    /*or mask for setting bit in this register */
+};
+
+struct MODS_REGISTER_IRQ_3 {
+	/* IN */
+	struct	mods_pci_dev_2 dev; /* device identifying interrupt for */
+				    /* which the mask will be applied */
+	__u64	aperture_addr;	    /* physical address of aperture */
+	__u32	aperture_size;	    /* size of the mapped region */
+	__u32	mask_info_cnt;	    /* number of entries in mask_info[]*/
+	struct	mods_mask_info2 mask_info[MODS_IRQ_MAX_MASKS];
+	__u8	irq_type;	    /* MODS_IRQ_TYPE_* */
+	__u8	reserved[7];	    /* keep alignment to 64bits */
+};
+
+/* MODS_ESC_REGISTER_IRQ_2 */
+/* MODS_ESC_UNREGISTER_IRQ_2 */
+/* MODS_ESC_IRQ_HANDLED_2 */
+struct MODS_REGISTER_IRQ_2 {
+	/* IN */
+	struct mods_pci_dev_2 dev;  /* device which generates the interrupt */
+	__u8			type; /* MODS_IRQ_TYPE_* */
+};
+
+/* MODS_ESC_REGISTER_IRQ */
+/* MODS_ESC_UNREGISTER_IRQ */
+/* MODS_ESC_IRQ_HANDLED */
+struct MODS_REGISTER_IRQ {
+	/* IN */
+	struct mods_pci_dev dev;   /* device which generates */
+				   /* the interrupt          */
+	__u8		    type;  /* MODS_IRQ_TYPE_* */
+};
+
+struct mods_irq_2 {
+	__u32			delay; /* delay in ns between the irq        */
+				       /* occurring and MODS querying for it */
+	struct mods_pci_dev_2 dev;  /* device which generated the interrupt */
+};
+
+struct mods_irq {
+	__u32		    delay; /* delay in ns between the irq */
+				   /* occurring and MODS querying */
+				   /* for it                      */
+	struct mods_pci_dev dev;   /* device which generated */
+				   /* the interrupt          */
+};
+
+#define MODS_MAX_IRQS 32
+
+/* MODS_ESC_QUERY_IRQ_2 */
+struct MODS_QUERY_IRQ_2 {
+	/* OUT */
+	struct mods_irq_2 irq_list[MODS_MAX_IRQS];
+	__u8		    more;	/* indicates that more interrupts */
+					/* are waiting                    */
+};
+
+/* MODS_ESC_QUERY_IRQ */
+struct MODS_QUERY_IRQ {
+	/* OUT */
+	struct mods_irq irq_list[MODS_MAX_IRQS];
+	__u8		more;  /* indicates that more interrupts are waiting */
+};
+
+#define MODS_IRQ_TYPE_INT  0
+#define MODS_IRQ_TYPE_MSI  1
+#define MODS_IRQ_TYPE_CPU  2
+
+/* MODS_ESC_SET_IRQ_MULTIMASK */
+struct mods_mask_info {
+	__u8	mask_type;  /*mask type 32/64 bit access*/
+	__u8	reserved[3];
+	__u32	reg_offset; /* offset of register within the bar aperture*/
+	__u64	and_mask;   /*and mask for clearing bits in this register */
+	__u64	or_mask;    /*or value for setting bit in this register */
+};
+struct MODS_SET_IRQ_MULTIMASK {
+	/* IN */
+	__u64	aperture_addr;	    /* physical address of aperture */
+	__u32	aperture_size;	    /* size of the mapped region */
+	struct	mods_pci_dev_2 dev; /* device identifying interrupt for */
+				    /* which the mask will be applied */
+	__u32	mask_info_cnt;	    /* number of entries in mask_info[]*/
+	struct	mods_mask_info mask_info[MODS_IRQ_MAX_MASKS];
+	__u8	irq_type;	    /* irq type */
+};
+
+
+/* MODS_ESC_SET_IRQ_MASK_2 */
+struct MODS_SET_IRQ_MASK_2 {
+	/* IN */
+	__u64			aperture_addr;/* physical address of aperture */
+	__u32			aperture_size;/* size of the mapped region */
+	__u32			reg_offset;   /* offset of the irq mask       */
+					      /* register within the aperture */
+	__u64			and_mask;     /* and mask for clearing bits */
+					      /* in the irq mask register   */
+	__u64			or_mask;      /* or mask for setting bits in */
+					      /* the irq mask register       */
+	struct mods_pci_dev_2 dev;	      /* device identifying interrupt */
+					      /* for which the mask will be   */
+					      /* applied                      */
+	__u8			irq_type;     /* irq type */
+	__u8			mask_type;    /* mask type */
+};
+
+/* MODS_ESC_SET_IRQ_MASK */
+struct MODS_SET_IRQ_MASK {
+	/* IN */
+	__u64		    aperture_addr; /* physical address of aperture */
+	__u32		    aperture_size; /* size of the mapped region */
+	__u32		    reg_offset;	   /* offset of the irq mask register */
+					   /* within the aperture             */
+	__u32		    and_mask;	   /* and mask for clearing bits in */
+					   /* the irq mask register         */
+	__u32		    or_mask;	   /* or mask for setting bits in */
+					   /* the irq mask register       */
+	struct mods_pci_dev dev;	   /* device identifying interrupt */
+					   /* for which the mask will be   */
+					   /* applied                      */
+	__u8		    irq_type;	   /* irq type */
+	__u8		    mask_type;	   /* mask type */
+};
+
+#define MAX_DT_SIZE 64
+#define MAX_FULL_SIZE 128
+
+/*MODS_ESC_MAP_INTERRUPT*/
+struct MODS_DT_INFO {
+	/* OUT */
+	/* Logical irq number*/
+	__u32	irq;
+	/* IN */
+	/* DT name for looking up device tree node */
+	char	dt_name[MAX_DT_SIZE];
+	/* Full name of node as in device tree */
+	char	full_name[MAX_FULL_SIZE];
+	/* Irq index corresponding to physical irq */
+	__u32	index;
+};
+
+#define MODS_MASK_TYPE_IRQ_DISABLE      0
+#define MODS_MASK_TYPE_IRQ_DISABLE64    1
+
+#define ACPI_MODS_TYPE_INTEGER		1
+#define ACPI_MODS_TYPE_BUFFER		2
+#define ACPI_MAX_BUFFER_LENGTH		4096
+#define ACPI_MAX_METHOD_LENGTH		12
+#define ACPI_MAX_ARGUMENT_NUMBER	12
+
+union ACPI_ARGUMENT {
+	__u32	type;
+
+	struct {
+		__u32 type;
+		__u32 value;
+	} integer;
+
+	struct {
+		__u32	type;
+		__u32	length;
+		__u32	offset;
+	} buffer;
+};
+
+/* MODS_ESC_EVAL_ACPI_METHOD */
+struct MODS_EVAL_ACPI_METHOD {
+	/* IN */
+	char		    method_name[ACPI_MAX_METHOD_LENGTH];
+	__u32		    argument_count;
+	union ACPI_ARGUMENT argument[ACPI_MAX_ARGUMENT_NUMBER];
+	__u8		    in_buffer[ACPI_MAX_BUFFER_LENGTH];
+
+	/* IN OUT */
+	__u32		    out_data_size;
+
+	/* OUT */
+	__u8		    out_buffer[ACPI_MAX_BUFFER_LENGTH];
+	__u32		    out_status;
+};
+
+/* MODS_ESC_EVAL_DEV_ACPI_METHOD_2 */
+struct MODS_EVAL_DEV_ACPI_METHOD_2 {
+	/* IN OUT */
+	struct MODS_EVAL_ACPI_METHOD method;
+
+	/* IN */
+	struct mods_pci_dev_2 device;
+};
+
+/* MODS_ESC_EVAL_DEV_ACPI_METHOD */
+struct MODS_EVAL_DEV_ACPI_METHOD {
+	/* IN OUT */
+	struct MODS_EVAL_ACPI_METHOD method;
+
+	/* IN */
+	struct mods_pci_dev device;
+};
+
+/* MODS_ESC_ACPI_GET_DDC_2 */
+struct MODS_ACPI_GET_DDC_2 {
+	/* OUT */
+	__u32			out_data_size;
+	__u8			out_buffer[ACPI_MAX_BUFFER_LENGTH];
+
+	/* IN */
+	struct mods_pci_dev_2 device;
+};
+
+/* MODS_ESC_ACPI_GET_DDC */
+struct MODS_ACPI_GET_DDC {
+	/* OUT */
+	__u32		    out_data_size;
+	__u8		    out_buffer[ACPI_MAX_BUFFER_LENGTH];
+
+	/* IN */
+	struct mods_pci_dev device;
+};
+
+/* MODS_ESC_GET_VERSION */
+struct MODS_GET_VERSION {
+	/* OUT */
+	__u64 version;
+};
+
+/* MODS_ESC_SET_PARA */
+struct MODS_SET_PARA {
+	/* IN */
+	__u64 Highmem4g;
+	__u64 debug;
+};
+
+/* MODS_ESC_SET_MEMORY_TYPE */
+struct MODS_MEMORY_TYPE {
+	/* IN */
+	__u64 physical_address;
+	__u64 size;
+	__u32 type;
+};
+
+#define MAX_CLOCK_HANDLE_NAME 64
+
+/* MODS_ESC_GET_CLOCK_HANDLE */
+struct MODS_GET_CLOCK_HANDLE {
+	/* OUT */
+	__u32 clock_handle;
+
+	/* IN */
+	char  device_name[MAX_CLOCK_HANDLE_NAME];
+	char  controller_name[MAX_CLOCK_HANDLE_NAME];
+};
+
+/* MODS_ESC_SET_CLOCK_RATE, MODS_ESC_GET_CLOCK_RATE,        */
+/* MODS_ESC_GET_CLOCK_MAX_RATE, MODS_ESC_SET_CLOCK_MAX_RATE */
+struct MODS_CLOCK_RATE {
+	/* IN/OUT */
+	__u64 clock_rate_hz;
+
+	/* IN */
+	__u32 clock_handle;
+};
+
+/* MODS_ESC_SET_CLOCK_PARENT, MODS_ESC_GET_CLOCK_PARENT */
+struct MODS_CLOCK_PARENT {
+	/* IN */
+	__u32 clock_handle;
+
+	/* IN/OUT */
+	__u32 clock_parent_handle;
+};
+
+/* MODS_ESC_ENABLE_CLOCK, MODS_ESC_DISABLE_CLOCK,             */
+/* MODS_ESC_CLOCK_RESET_ASSERT, MODS_ESC_CLOCK_RESET_DEASSERT */
+struct MODS_CLOCK_HANDLE {
+	/* IN */
+	__u32 clock_handle;
+};
+
+/* MODS_ESC_IS_CLOCK_ENABLED */
+struct MODS_CLOCK_ENABLED {
+	/* IN */
+	__u32 clock_handle;
+
+	/* OUT */
+	__u32 enable_count;
+};
+
+#if defined(CONFIG_PPC64) || defined(PPC64LE)
+#define MAX_CPU_MASKS 64  /* 32 masks of 32bits = 2048 CPUs max */
+#else
+#define MAX_CPU_MASKS 32  /* 32 masks of 32bits = 1024 CPUs max */
+#endif
+/* MODS_ESC_DEVICE_NUMA_INFO_2 */
+struct MODS_DEVICE_NUMA_INFO_2 {
+	/* IN */
+	struct mods_pci_dev_2 pci_device;
+
+	/* OUT */
+	__s32  node;
+	__u32  node_count;
+	__u32  node_cpu_mask[MAX_CPU_MASKS];
+	__u32  cpu_count;
+};
+
+/* MODS_ESC_DEVICE_NUMA_INFO */
+struct MODS_DEVICE_NUMA_INFO {
+	/* IN */
+	struct mods_pci_dev pci_device;
+
+	/* OUT */
+	__s32  node;
+	__u32  node_count;
+	__u32  node_cpu_mask[MAX_CPU_MASKS];
+	__u32  cpu_count;
+};
+
+/* The ids match MODS ids */
+#define MODS_MEMORY_CACHED		5
+#define MODS_MEMORY_UNCACHED		1
+#define MODS_MEMORY_WRITECOMBINE	2
+
+struct MODS_TEGRA_DC_WINDOW {
+	__s32 index;
+	__u32 flags;
+	__u32 x;
+	__u32 y;
+	__u32 w;
+	__u32 h;
+	__u32 out_x;
+	__u32 out_y;
+	__u32 out_w;
+	__u32 out_h;
+	__u32 pixformat; /* NVDC pix format */
+
+	__u32 bandwidth;
+};
+#define MODS_TEGRA_DC_WINDOW_FLAG_ENABLED   (1 << 0)
+#define MODS_TEGRA_DC_WINDOW_FLAG_TILED     (1 << 1)
+#define MODS_TEGRA_DC_WINDOW_FLAG_SCAN_COL  (1 << 2)
+#define MODS_TEGRA_DC_MAX_WINDOWS           (6)
+
+/* MODS_ESC_TEGRA_DC_CONFIG_POSSIBLE */
+struct MODS_TEGRA_DC_CONFIG_POSSIBLE {
+	/* IN/OUT */
+	struct MODS_TEGRA_DC_WINDOW windows[MODS_TEGRA_DC_MAX_WINDOWS];
+
+	/* IN */
+	__u8 head;
+	__u8 win_num;
+
+	/* OUT */
+	__u8  possible;
+};
+
+
+#define MODS_TEGRA_DC_SETUP_SD_LUT_SIZE  9
+#define MODS_TEGRA_DC_SETUP_BLTF_SIZE   16
+/* MODS_ESC_TEGRA_DC_SETUP_SD */
+struct MODS_TEGRA_DC_SETUP_SD {
+	/* IN */
+	__u8 head;
+	__u8 enable;
+
+	__u8 use_vid_luma;
+	__u8 csc_r;
+	__u8 csc_g;
+	__u8 csc_b;
+	__u8 aggressiveness;
+	__u8 bin_width_log2;
+
+	__u32 lut[MODS_TEGRA_DC_SETUP_SD_LUT_SIZE];
+	__u32 bltf[MODS_TEGRA_DC_SETUP_BLTF_SIZE];
+
+	__u32 klimit;
+	__u32 soft_clipping_threshold;
+	__u32 smooth_k_inc;
+	__u8  k_init_bias;
+
+
+	__u32 win_x;
+	__u32 win_y;
+	__u32 win_w;
+	__u32 win_h;
+};
+
+/* MODS_ESC_DMABUF_GET_PHYSICAL_ADDRESS */
+struct MODS_DMABUF_GET_PHYSICAL_ADDRESS {
+	/* IN */
+	__s32 buf_fd;
+	__u32 padding;
+	__u64 offset;
+
+	/* OUT */
+	__u64 physical_address;
+	__u64 segment_size;
+};
+
+#define MODS_ADSP_APP_NAME_SIZE 64
+#define MODS_ADSP_APP_MAX_PARAM 128
+struct MODS_ADSP_RUN_APP_INFO {
+	char app_name[MODS_ADSP_APP_NAME_SIZE];
+	char app_file_name[MODS_ADSP_APP_NAME_SIZE];
+	__u32 argc;
+	__u32 argv[MODS_ADSP_APP_MAX_PARAM];
+	__u32 timeout;
+};
+
+/* MODS_ESC_GET_SCREEN_INFO */
+struct MODS_SCREEN_INFO {
+	/* OUT */
+	__u8  orig_video_mode;
+	__u8  orig_video_is_vga;
+	__u16 lfb_width;
+	__u16 lfb_height;
+	__u16 lfb_depth;
+	__u32 lfb_base;
+	__u32 lfb_size;
+	__u16 lfb_linelength;
+};
+
+enum MODS_DMA_TRANSACTION_TYPE {
+	MODS_DMA_MEMCPY,
+	MODS_DMA_XOR,
+	MODS_DMA_PQ,
+	MODS_DMA_XOR_VAL,
+	MODS_DMA_PQ_VAL,
+	MODS_DMA_MEMSET,
+	MODS_DMA_MEMSET_SG,
+	MODS_DMA_INTERRUPT,
+	MODS_DMA_SG,
+	MODS_DMA_PRIVATE,
+	MODS_DMA_ASYNC_TX,
+	MODS_DMA_SLAVE,
+	MODS_DMA_CYCLIC,
+	MODS_DMA_INTERLEAVE,
+/* last transaction type for creation of the capabilities mask */
+	MODS_DMA_TX_TYPE_END
+};
+
+struct MODS_DMA_HANDLE {
+	/* IN */
+	__u32 dma_type; /* Indicate the DMA Type*/
+	/* OUT */
+	__u32	dma_id; /* Inditify for the DMA */
+};
+
+enum MODS_DMA_TRANSFER_DIRECTION {
+	MODS_DMA_MEM_TO_MEM,
+	MODS_DMA_MEM_TO_DEV,
+	MODS_DMA_DEV_TO_MEM,
+	MODS_DMA_DEV_TO_DEV,
+	MODS_DMA_TRANS_NONE
+};
+
+enum MODS_DMA_BUSWIDTH {
+	MODS_DMA_BUSWIDTH_UNDEFINED = 0,
+	MODS_DMA_BUSWIDTH_1_BYTE = 1,
+	MODS_DMA_BUSWIDTH_2_BYTES = 2,
+	MODS_DMA_BUSWIDTH_4_BYTES = 4,
+	MODS_DMA_BUSWIDTH_8_BYTES = 8
+};
+
+struct MODS_DMA_CHANNEL_CONFIG {
+	__u64 src_addr;
+	__u64 dst_addr;
+	struct MODS_DMA_HANDLE handle;
+	__u32 direction;
+	__u32 src_addr_width;
+	__u32 dst_addr_width;
+	__u32 src_maxburst;
+	__u32 dst_maxburst;
+	__u32 slave_id;
+	__u32 device_fc;
+};
+
+/* Node: Only support SINGLE MODS so far*/
+enum MODS_DMA_TX_MODE {
+	MODS_DMA_SINGLE = 0,
+	MODS_DMA_TX_CYCLIC,
+	MODS_DMA_INTERLEAVED /* Common to Slave as well as M2M clients. */
+};
+
+typedef __s32 mods_dma_cookie_t;
+
+struct MODS_DMA_TX_DESC	{
+	/* IN */
+	__u64 phys;
+	__u64 phys_2; /* only valid for MEMCPY */
+	struct MODS_DMA_HANDLE handle;
+	__u32 mode;
+	__u32 data_dir;
+	__u32 length;
+	__u32 flags;
+	/* OUT */
+	mods_dma_cookie_t cookie;
+};
+
+enum MODS_DMA_WAIT_TYPE {
+	MODS_DMA_SYNC_WAIT,     /* wait until finished */
+	MODS_DMA_ASYNC_WAIT     /* just check tx status */
+};
+
+struct MODS_DMA_WAIT_DESC {
+	struct MODS_DMA_HANDLE handle;
+	mods_dma_cookie_t cookie;
+	__u32 type;
+	/* OUT */
+	__u32 tx_complete;
+};
+
+#define MAX_NET_DEVICE_NAME_LENGTH 16
+struct MODS_NET_DEVICE_NAME {
+	/* in */
+	char device_name[MAX_NET_DEVICE_NAME_LENGTH];
+};
+struct MODS_DMA_COHERENT_MEM_HANDLE {
+	__u32	num_bytes;
+	__u32	attrib;
+	__u64	memory_handle_phys;
+	__u64	memory_handle_virt;
+};
+
+/* MODS_ESC_DMA_COPY_TO_USER */
+struct MODS_DMA_COPY_TO_USER {
+	__u32	num_bytes;
+	__u32	attrib;
+	__u64	memory_handle_src;
+	__u64	memory_handle_dst;
+};
+
+struct MODS_TEGRA_PROD_SET_TUPLE {
+	/* IN */
+	__u64 prod_dev_handle;
+	__u64 ctrl_dev_handle;
+	char prod_name[MAX_DT_SIZE];
+	__u32 index;
+	__u32 offset;
+	__u32 mask;
+};
+
+struct MODS_TEGRA_PROD_IS_SUPPORTED {
+	/* IN */
+	__u64 prod_dev_handle;
+	char prod_name[MAX_DT_SIZE];
+	/* OUT */
+	__u32 is_supported;
+};
+
+struct MODS_TEGRA_PROD_ITERATOR {
+	/* IN */
+	__u64 device_handle;
+	char name[MAX_DT_SIZE];
+	char next_name[MAX_DT_SIZE];
+	__u32 index;
+	__u32 is_leaf;
+	/* OUT */
+	__u64 next_device_handle;
+};
+
+/* MODS_ESC_GET_ATS_ADDRESS_RANGE */
+struct MODS_GET_ATS_ADDRESS_RANGE {
+	/* IN */
+	struct mods_pci_dev_2 pci_device;
+	__s32		      npu_index;
+	__u8		      reserved[4]; /* Alignment */
+
+	/* OUT */
+	struct mods_pci_dev_2 npu_device;
+	__u64		      phys_addr;
+	__u64		      guest_addr;
+	__u64		      aperture_size;
+	__s32		      numa_memory_node;
+};
+
+#pragma pack(pop)
+
+/* ************************************************************************* */
+/* ************************************************************************* */
+/* **									     */
+/* ** ESCAPE CALLS							     */
+/* **									     */
+/* ************************************************************************* */
+/* ************************************************************************* */
+#define MODS_IOC_MAGIC	  'x'
+#define MODS_ESC_ALLOC_PAGES			\
+		   _IOWR(MODS_IOC_MAGIC, 0, struct MODS_ALLOC_PAGES)
+#define MODS_ESC_FREE_PAGES			\
+		   _IOWR(MODS_IOC_MAGIC, 1, struct MODS_FREE_PAGES)
+#define MODS_ESC_GET_PHYSICAL_ADDRESS		\
+		   _IOWR(MODS_IOC_MAGIC, 2, struct MODS_GET_PHYSICAL_ADDRESS)
+#define MODS_ESC_VIRTUAL_TO_PHYSICAL		\
+		   _IOWR(MODS_IOC_MAGIC, 3, struct MODS_VIRTUAL_TO_PHYSICAL)
+#define MODS_ESC_PHYSICAL_TO_VIRTUAL		\
+		   _IOWR(MODS_IOC_MAGIC, 4, struct MODS_PHYSICAL_TO_VIRTUAL)
+#define MODS_ESC_FIND_PCI_DEVICE		\
+		   _IOWR(MODS_IOC_MAGIC, 5, struct MODS_FIND_PCI_DEVICE)
+#define MODS_ESC_FIND_PCI_CLASS_CODE		\
+		   _IOWR(MODS_IOC_MAGIC, 6, struct MODS_FIND_PCI_CLASS_CODE)
+#define MODS_ESC_PCI_READ			\
+		   _IOWR(MODS_IOC_MAGIC, 7, struct MODS_PCI_READ)
+#define MODS_ESC_PCI_WRITE			\
+		   _IOWR(MODS_IOC_MAGIC, 8, struct MODS_PCI_WRITE)
+#define MODS_ESC_PIO_READ			\
+		   _IOWR(MODS_IOC_MAGIC, 9, struct MODS_PIO_READ)
+#define MODS_ESC_PIO_WRITE			\
+		   _IOWR(MODS_IOC_MAGIC, 10, struct MODS_PIO_WRITE)
+#define MODS_ESC_IRQ_REGISTER			\
+		   _IOWR(MODS_IOC_MAGIC, 11, struct MODS_IRQ)
+#define MODS_ESC_IRQ_FREE			\
+		   _IOWR(MODS_IOC_MAGIC, 12, struct MODS_IRQ)
+#define MODS_ESC_IRQ_INQUIRY			\
+		   _IOWR(MODS_IOC_MAGIC, 13, struct MODS_IRQ)
+#define MODS_ESC_EVAL_ACPI_METHOD		\
+		   _IOWR_BAD(MODS_IOC_MAGIC, 16, struct MODS_EVAL_ACPI_METHOD)
+#define MODS_ESC_GET_API_VERSION		\
+		   _IOWR(MODS_IOC_MAGIC, 17, struct MODS_GET_VERSION)
+#define MODS_ESC_GET_KERNEL_VERSION		\
+		   _IOWR(MODS_IOC_MAGIC, 18, struct MODS_GET_VERSION)
+#define MODS_ESC_SET_DRIVER_PARA		\
+		   _IOWR(MODS_IOC_MAGIC, 19, struct MODS_SET_PARA)
+#define MODS_ESC_MSI_REGISTER			\
+		   _IOWR(MODS_IOC_MAGIC, 20, struct MODS_IRQ)
+#define MODS_ESC_REARM_MSI			\
+		   _IOWR(MODS_IOC_MAGIC, 21, struct MODS_IRQ)
+#define MODS_ESC_SET_MEMORY_TYPE		\
+		    _IOW(MODS_IOC_MAGIC, 22, struct MODS_MEMORY_TYPE)
+#define MODS_ESC_PCI_BUS_ADD_DEVICES		\
+		    _IOW(MODS_IOC_MAGIC, 23, struct MODS_PCI_BUS_ADD_DEVICES)
+#define MODS_ESC_REGISTER_IRQ			\
+		    _IOW(MODS_IOC_MAGIC, 24, struct MODS_REGISTER_IRQ)
+#define MODS_ESC_UNREGISTER_IRQ			\
+		    _IOW(MODS_IOC_MAGIC, 25, struct MODS_REGISTER_IRQ)
+#define MODS_ESC_QUERY_IRQ			\
+		    _IOR(MODS_IOC_MAGIC, 26, struct MODS_QUERY_IRQ)
+#define MODS_ESC_EVAL_DEV_ACPI_METHOD		\
+		_IOWR_BAD(MODS_IOC_MAGIC, 27, struct MODS_EVAL_DEV_ACPI_METHOD)
+#define MODS_ESC_ACPI_GET_DDC			\
+		   _IOWR(MODS_IOC_MAGIC, 28, struct MODS_ACPI_GET_DDC)
+#define MODS_ESC_GET_CLOCK_HANDLE		\
+		   _IOWR(MODS_IOC_MAGIC, 29, struct MODS_GET_CLOCK_HANDLE)
+#define MODS_ESC_SET_CLOCK_RATE			\
+		    _IOW(MODS_IOC_MAGIC, 30, struct MODS_CLOCK_RATE)
+#define MODS_ESC_GET_CLOCK_RATE			\
+		   _IOWR(MODS_IOC_MAGIC, 31, struct MODS_CLOCK_RATE)
+#define MODS_ESC_SET_CLOCK_PARENT		\
+		    _IOW(MODS_IOC_MAGIC, 32, struct MODS_CLOCK_PARENT)
+#define MODS_ESC_GET_CLOCK_PARENT		\
+		   _IOWR(MODS_IOC_MAGIC, 33, struct MODS_CLOCK_PARENT)
+#define MODS_ESC_ENABLE_CLOCK			\
+		    _IOW(MODS_IOC_MAGIC, 34, struct MODS_CLOCK_HANDLE)
+#define MODS_ESC_DISABLE_CLOCK			\
+		    _IOW(MODS_IOC_MAGIC, 35, struct MODS_CLOCK_HANDLE)
+#define MODS_ESC_IS_CLOCK_ENABLED		\
+		   _IOWR(MODS_IOC_MAGIC, 36, struct MODS_CLOCK_ENABLED)
+#define MODS_ESC_CLOCK_RESET_ASSERT		\
+		    _IOW(MODS_IOC_MAGIC, 37, struct MODS_CLOCK_HANDLE)
+#define MODS_ESC_CLOCK_RESET_DEASSERT		\
+		    _IOW(MODS_IOC_MAGIC, 38, struct MODS_CLOCK_HANDLE)
+#define MODS_ESC_SET_IRQ_MASK			\
+		    _IOW(MODS_IOC_MAGIC, 39, struct MODS_SET_IRQ_MASK)
+#define MODS_ESC_MEMORY_BARRIER			\
+		     _IO(MODS_IOC_MAGIC, 40)
+#define MODS_ESC_IRQ_HANDLED			\
+		    _IOW(MODS_IOC_MAGIC, 41, struct MODS_REGISTER_IRQ)
+#define MODS_ESC_FLUSH_CPU_CACHE_RANGE		\
+		    _IOW(MODS_IOC_MAGIC, 42, struct MODS_FLUSH_CPU_CACHE_RANGE)
+#define MODS_ESC_GET_CLOCK_MAX_RATE		\
+		   _IOWR(MODS_IOC_MAGIC, 43, struct MODS_CLOCK_RATE)
+#define MODS_ESC_SET_CLOCK_MAX_RATE		\
+		    _IOW(MODS_IOC_MAGIC, 44, struct MODS_CLOCK_RATE)
+#define MODS_ESC_DEVICE_ALLOC_PAGES		\
+		   _IOWR(MODS_IOC_MAGIC, 45, struct MODS_DEVICE_ALLOC_PAGES)
+#define MODS_ESC_DEVICE_NUMA_INFO		\
+		   _IOWR(MODS_IOC_MAGIC, 46, struct MODS_DEVICE_NUMA_INFO)
+#define MODS_ESC_TEGRA_DC_CONFIG_POSSIBLE	\
+		   _IOWR(MODS_IOC_MAGIC, 47,	\
+			 struct MODS_TEGRA_DC_CONFIG_POSSIBLE)
+#define MODS_ESC_TEGRA_DC_SETUP_SD		\
+		    _IOW(MODS_IOC_MAGIC, 48, struct MODS_TEGRA_DC_SETUP_SD)
+#define MODS_ESC_DMABUF_GET_PHYSICAL_ADDRESS	\
+		   _IOWR(MODS_IOC_MAGIC, 49,    \
+			 struct MODS_DMABUF_GET_PHYSICAL_ADDRESS)
+#define MODS_ESC_ADSP_LOAD			\
+		     _IO(MODS_IOC_MAGIC, 50)
+#define MODS_ESC_ADSP_START			\
+		     _IO(MODS_IOC_MAGIC, 51)
+#define MODS_ESC_ADSP_STOP			\
+		     _IO(MODS_IOC_MAGIC, 52)
+#define MODS_ESC_ADSP_RUN_APP			\
+		    _IOW(MODS_IOC_MAGIC, 53, struct MODS_ADSP_RUN_APP_INFO)
+#define MODS_ESC_PCI_GET_BAR_INFO		\
+		   _IOWR(MODS_IOC_MAGIC, 54, struct MODS_PCI_GET_BAR_INFO)
+#define MODS_ESC_PCI_GET_IRQ			\
+		   _IOWR(MODS_IOC_MAGIC, 55, struct MODS_PCI_GET_IRQ)
+#define MODS_ESC_GET_MAPPED_PHYSICAL_ADDRESS	\
+		   _IOWR(MODS_IOC_MAGIC, 56,	\
+			 struct MODS_GET_PHYSICAL_ADDRESS)
+#define MODS_ESC_DEVICE_ALLOC_PAGES_2		\
+		   _IOWR(MODS_IOC_MAGIC, 57, struct MODS_DEVICE_ALLOC_PAGES_2)
+#define MODS_ESC_FIND_PCI_DEVICE_2		\
+		   _IOWR(MODS_IOC_MAGIC, 58, struct MODS_FIND_PCI_DEVICE_2)
+#define MODS_ESC_FIND_PCI_CLASS_CODE_2		\
+		   _IOWR(MODS_IOC_MAGIC, 59,	\
+			 struct MODS_FIND_PCI_CLASS_CODE_2)
+#define MODS_ESC_PCI_GET_BAR_INFO_2		\
+		   _IOWR(MODS_IOC_MAGIC, 60, struct MODS_PCI_GET_BAR_INFO_2)
+#define MODS_ESC_PCI_GET_IRQ_2			\
+		   _IOWR(MODS_IOC_MAGIC, 61, struct MODS_PCI_GET_IRQ_2)
+#define MODS_ESC_PCI_READ_2			\
+		   _IOWR(MODS_IOC_MAGIC, 62, struct MODS_PCI_READ_2)
+#define MODS_ESC_PCI_WRITE_2			\
+		    _IOW(MODS_IOC_MAGIC, 63, struct MODS_PCI_WRITE_2)
+#define MODS_ESC_REGISTER_IRQ_2			\
+		    _IOW(MODS_IOC_MAGIC, 64, struct MODS_REGISTER_IRQ_2)
+#define MODS_ESC_UNREGISTER_IRQ_2		\
+		    _IOW(MODS_IOC_MAGIC, 65, struct MODS_REGISTER_IRQ_2)
+#define MODS_ESC_IRQ_HANDLED_2			\
+		    _IOW(MODS_IOC_MAGIC, 66, struct MODS_REGISTER_IRQ_2)
+#define MODS_ESC_QUERY_IRQ_2			\
+		    _IOR(MODS_IOC_MAGIC, 67, struct MODS_QUERY_IRQ_2)
+#define MODS_ESC_SET_IRQ_MASK_2			\
+		    _IOW(MODS_IOC_MAGIC, 68, struct MODS_SET_IRQ_MASK_2)
+#define MODS_ESC_EVAL_DEV_ACPI_METHOD_2		\
+		   _IOWR_BAD(MODS_IOC_MAGIC, 69,\
+		   struct MODS_EVAL_DEV_ACPI_METHOD_2)
+#define MODS_ESC_DEVICE_NUMA_INFO_2		\
+		   _IOWR(MODS_IOC_MAGIC, 70, struct MODS_DEVICE_NUMA_INFO_2)
+#define MODS_ESC_ACPI_GET_DDC_2			\
+		   _IOWR(MODS_IOC_MAGIC, 71, struct MODS_ACPI_GET_DDC_2)
+#define MODS_ESC_GET_SCREEN_INFO			\
+		    _IOR(MODS_IOC_MAGIC, 72, struct MODS_SCREEN_INFO)
+#define MODS_ESC_PCI_HOT_RESET			\
+		    _IOW(MODS_IOC_MAGIC, 73, struct MODS_PCI_HOT_RESET)
+#define MODS_ESC_SET_PPC_TCE_BYPASS			\
+		    _IOWR(MODS_IOC_MAGIC, 74, struct MODS_SET_PPC_TCE_BYPASS)
+#define MODS_ESC_DMA_MAP_MEMORY			\
+		    _IOW(MODS_IOC_MAGIC, 75, struct MODS_DMA_MAP_MEMORY)
+#define MODS_ESC_DMA_UNMAP_MEMORY			\
+		    _IOW(MODS_IOC_MAGIC, 76, struct MODS_DMA_MAP_MEMORY)
+#define MODS_ESC_GET_MAPPED_PHYSICAL_ADDRESS_2			\
+		    _IOWR(MODS_IOC_MAGIC, 77,                   \
+			  struct MODS_GET_PHYSICAL_ADDRESS_2)
+#define MODS_ESC_PCI_MAP_RESOURCE			\
+		    _IOWR(MODS_IOC_MAGIC, 78, struct MODS_PCI_MAP_RESOURCE)
+#define MODS_ESC_PCI_UNMAP_RESOURCE			\
+		    _IOW(MODS_IOC_MAGIC, 79, struct MODS_PCI_UNMAP_RESOURCE)
+#define MODS_ESC_DMA_REQUEST_HANDLE		\
+		   _IOR(MODS_IOC_MAGIC,  80, struct MODS_DMA_HANDLE)
+#define MODS_ESC_DMA_RELEASE_HANDLE		\
+		   _IOW(MODS_IOC_MAGIC,  81, struct MODS_DMA_HANDLE)
+#define MODS_ESC_DMA_SET_CONFIG			\
+		   _IOW(MODS_IOC_MAGIC,  82, struct MODS_DMA_CHANNEL_CONFIG)
+#define MODS_ESC_DMA_TX_SUBMIT			\
+		   _IOW(MODS_IOC_MAGIC,  83, struct MODS_DMA_TX_DESC)
+#define MODS_ESC_DMA_TX_WAIT			\
+		   _IOWR(MODS_IOC_MAGIC, 84, struct MODS_DMA_WAIT_DESC)
+#define MODS_ESC_DMA_ISSUE_PENDING		\
+		   _IOW(MODS_IOC_MAGIC,  85, struct MODS_DMA_HANDLE)
+#define MODS_ESC_SET_IRQ_MULTIMASK			\
+		    _IOW(MODS_IOC_MAGIC, 86, struct MODS_SET_IRQ_MULTIMASK)
+#define MODS_ESC_NET_FORCE_LINK			\
+		    _IOW(MODS_IOC_MAGIC, 87, struct MODS_NET_DEVICE_NAME)
+#define MODS_ESC_REGISTER_IRQ_3			\
+		    _IOW(MODS_IOC_MAGIC, 88, struct MODS_REGISTER_IRQ_3)
+#define MODS_ESC_DMA_ALLOC_COHERENT			\
+		   _IOWR(MODS_IOC_MAGIC, 89,		\
+		   struct MODS_DMA_COHERENT_MEM_HANDLE)
+#define MODS_ESC_DMA_FREE_COHERENT			\
+		   _IOWR(MODS_IOC_MAGIC, 90,		\
+		   struct MODS_DMA_COHERENT_MEM_HANDLE)
+#define MODS_ESC_DMA_COPY_TO_USER			\
+		   _IOWR(MODS_IOC_MAGIC, 91,		\
+		   struct MODS_DMA_COPY_TO_USER)
+#define MODS_ESC_MAP_INTERRUPT			\
+		   _IOWR(MODS_IOC_MAGIC, 92,		\
+		   struct MODS_DT_INFO)
+#define MODS_ESC_LOCK_CONSOLE			\
+		    _IO(MODS_IOC_MAGIC, 93)
+#define MODS_ESC_UNLOCK_CONSOLE		\
+		    _IO(MODS_IOC_MAGIC, 94)
+#define MODS_ESC_TEGRA_PROD_IS_SUPPORTED		\
+		   _IOWR(MODS_IOC_MAGIC, 95,		\
+		   struct MODS_TEGRA_PROD_IS_SUPPORTED)
+#define MODS_ESC_TEGRA_PROD_SET_PROD_ALL		\
+		   _IOW(MODS_IOC_MAGIC, 96,		\
+		   struct MODS_TEGRA_PROD_SET_TUPLE)
+#define MODS_ESC_TEGRA_PROD_SET_PROD_BOOT		\
+		   _IOW(MODS_IOC_MAGIC, 97,		\
+		   struct MODS_TEGRA_PROD_SET_TUPLE)
+#define MODS_ESC_TEGRA_PROD_SET_PROD_BY_NAME		\
+		   _IOW(MODS_IOC_MAGIC, 98,		\
+		   struct MODS_TEGRA_PROD_SET_TUPLE)
+#define MODS_ESC_TEGRA_PROD_SET_PROD_EXACT		\
+		   _IOW(MODS_IOC_MAGIC, 99,		\
+		   struct MODS_TEGRA_PROD_SET_TUPLE)
+#define MODS_ESC_TEGRA_PROD_ITERATE_DT			\
+		   _IOWR(MODS_IOC_MAGIC, 100,		\
+		   struct MODS_TEGRA_PROD_ITERATOR)
+#define MODS_ESC_GET_ATS_ADDRESS_RANGE        \
+		   _IOWR(MODS_IOC_MAGIC, 101, \
+		   struct MODS_GET_ATS_ADDRESS_RANGE)
+
+#endif /* _MODS_H_  */
diff --git a/drivers/misc/mods/mods_acpi.c b/drivers/misc/mods/mods_acpi.c
new file mode 100644
index 00000000..90974ec9
--- /dev/null
+++ b/drivers/misc/mods/mods_acpi.c
@@ -0,0 +1,452 @@
+/*
+ * mods_acpi.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2008-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mods_internal.h"
+
+#include <linux/acpi.h>
+#include <linux/device.h>
+#include <acpi/acpi.h>
+#include <acpi/acpi_bus.h>
+
+static acpi_status mods_acpi_find_acpi_handler(acpi_handle,
+					       u32,
+					       void *,
+					       void **);
+
+/*********************
+ * PRIVATE FUNCTIONS *
+ *********************/
+
+/* store handle if found. */
+static void mods_acpi_handle_init(char *method_name, acpi_handle *handler)
+{
+	MODS_ACPI_WALK_NAMESPACE(ACPI_TYPE_ANY,
+				 ACPI_ROOT_OBJECT,
+				 ACPI_UINT32_MAX,
+				 mods_acpi_find_acpi_handler,
+				 method_name,
+				 handler);
+
+	if (!(*handler)) {
+		mods_debug_printk(DEBUG_ACPI, "ACPI method %s not found\n",
+				  method_name);
+		return;
+	}
+}
+
+static acpi_status mods_acpi_find_acpi_handler(
+	acpi_handle handle,
+	u32 nest_level,
+	void *dummy1,
+	void **dummy2
+)
+{
+	acpi_handle acpi_method_handler_temp;
+
+	if (!acpi_get_handle(handle, dummy1, &acpi_method_handler_temp))
+		*dummy2 = acpi_method_handler_temp;
+
+	return OK;
+}
+
+static int mods_extract_acpi_object(
+	char *method,
+	union acpi_object *obj,
+	u8 **buf,
+	u8 *buf_end
+)
+{
+	int ret = OK;
+
+	switch (obj->type) {
+
+	case ACPI_TYPE_BUFFER:
+		if (obj->buffer.length == 0) {
+			mods_error_printk(
+			    "empty ACPI output buffer from ACPI method %s\n",
+			    method);
+			ret = -EINVAL;
+		} else if (obj->buffer.length <= buf_end-*buf) {
+			u32 size = obj->buffer.length;
+
+			memcpy(*buf, obj->buffer.pointer, size);
+			*buf += size;
+		} else {
+			mods_error_printk(
+			    "output buffer too small for ACPI method %s\n",
+			    method);
+			ret = -EINVAL;
+		}
+		break;
+
+	case ACPI_TYPE_INTEGER:
+		if (buf_end - *buf >= 4) {
+			if (obj->integer.value > 0xFFFFFFFFU) {
+				mods_error_printk(
+			    "integer value from ACPI method %s out of range\n",
+					  method);
+				ret = -EINVAL;
+			} else {
+				memcpy(*buf, &obj->integer.value, 4);
+				*buf += 4;
+			}
+		} else {
+			mods_error_printk(
+				"output buffer too small for ACPI method %s\n",
+				method);
+			ret = -EINVAL;
+		}
+		break;
+
+	case ACPI_TYPE_PACKAGE:
+		if (obj->package.count == 0) {
+			mods_error_printk(
+			    "empty ACPI output package from ACPI method %s\n",
+			    method);
+			ret = -EINVAL;
+		} else {
+			union acpi_object *elements = obj->package.elements;
+			u32                size     = 0;
+			u32                i;
+
+			for (i = 0; i < obj->package.count; i++) {
+				u8 *old_buf = *buf;
+
+				ret = mods_extract_acpi_object(method,
+							       &elements[i],
+							       buf,
+							       buf_end);
+				if (ret == OK) {
+					u32 new_size = *buf - old_buf;
+
+					if (size == 0) {
+						size = new_size;
+					} else if (size != new_size) {
+						mods_error_printk(
+			 "ambiguous package element size from ACPI method %s\n",
+						  method);
+						ret = -EINVAL;
+					}
+				} else
+					break;
+			}
+		}
+		break;
+
+	default:
+		mods_error_printk(
+			"unsupported ACPI output type 0x%02x from method %s\n",
+			(unsigned int)obj->type, method);
+		ret = -EINVAL;
+		break;
+
+	}
+	return ret;
+}
+
+static int mods_eval_acpi_method(struct file		      *pfile,
+				 struct MODS_EVAL_ACPI_METHOD *p,
+				 struct mods_pci_dev_2	      *pdevice)
+{
+	int ret = OK;
+	int i;
+	acpi_status status;
+	struct acpi_object_list input;
+	struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
+	union acpi_object *acpi_method = NULL;
+	union acpi_object acpi_params[ACPI_MAX_ARGUMENT_NUMBER];
+	acpi_handle acpi_method_handler = NULL;
+
+	if (pdevice) {
+		unsigned int devfn;
+		struct pci_dev *dev;
+
+		mods_debug_printk(DEBUG_ACPI,
+				  "ACPI %s for device %04x:%x:%02x.%x\n",
+				  p->method_name,
+				  (unsigned int)pdevice->domain,
+				  (unsigned int)pdevice->bus,
+				  (unsigned int)pdevice->device,
+				  (unsigned int)pdevice->function);
+
+		devfn = PCI_DEVFN(pdevice->device, pdevice->function);
+		dev = MODS_PCI_GET_SLOT(pdevice->domain, pdevice->bus, devfn);
+		if (!dev) {
+			mods_error_printk("ACPI: PCI device not found\n");
+			return -EINVAL;
+		}
+		acpi_method_handler = MODS_ACPI_HANDLE(&dev->dev);
+	} else {
+		mods_debug_printk(DEBUG_ACPI, "ACPI %s\n", p->method_name);
+		mods_acpi_handle_init(p->method_name, &acpi_method_handler);
+	}
+
+	if (!acpi_method_handler) {
+		mods_debug_printk(DEBUG_ACPI, "ACPI: handle for %s not found\n",
+				  p->method_name);
+		return -EINVAL;
+	}
+
+	if (p->argument_count >= ACPI_MAX_ARGUMENT_NUMBER) {
+		mods_error_printk("invalid argument count for ACPI call\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < p->argument_count; i++) {
+		switch (p->argument[i].type) {
+		case ACPI_MODS_TYPE_INTEGER: {
+			acpi_params[i].integer.type = ACPI_TYPE_INTEGER;
+			acpi_params[i].integer.value
+				= p->argument[i].integer.value;
+			break;
+		}
+		case ACPI_MODS_TYPE_BUFFER: {
+			acpi_params[i].buffer.type = ACPI_TYPE_BUFFER;
+			acpi_params[i].buffer.length
+				= p->argument[i].buffer.length;
+			acpi_params[i].buffer.pointer
+				= p->in_buffer + p->argument[i].buffer.offset;
+			break;
+		}
+		default: {
+			mods_error_printk("unsupported ACPI argument type\n");
+			return -EINVAL;
+		}
+		}
+	}
+
+	input.count   = p->argument_count;
+	input.pointer = acpi_params;
+
+	status = acpi_evaluate_object(acpi_method_handler,
+				      pdevice ? p->method_name : NULL,
+				      &input,
+				      &output);
+
+	if (ACPI_FAILURE(status)) {
+		mods_error_printk("ACPI method %s failed\n", p->method_name);
+		return -EINVAL;
+	}
+
+	acpi_method = output.pointer;
+	if (!acpi_method) {
+		mods_error_printk("missing output from ACPI method %s\n",
+				  p->method_name);
+		ret = -EINVAL;
+	} else {
+		u8 *buf = p->out_buffer;
+
+		ret = mods_extract_acpi_object(p->method_name,
+					       acpi_method,
+					       &buf,
+					       buf+sizeof(p->out_buffer));
+		p->out_data_size = (ret == OK) ? (buf - p->out_buffer) : 0;
+	}
+
+	kfree(output.pointer);
+	return ret;
+}
+
+static int mods_acpi_get_ddc(struct file *pfile,
+			     struct MODS_ACPI_GET_DDC_2 *p,
+			     struct mods_pci_dev_2 *pci_device)
+{
+	acpi_status status;
+	struct acpi_device *device = NULL;
+	struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
+	union acpi_object *ddc;
+	union acpi_object ddc_arg0 = { ACPI_TYPE_INTEGER };
+	struct acpi_object_list input = { 1, &ddc_arg0 };
+	struct list_head *node, *next;
+	u32 i;
+	acpi_handle dev_handle	= NULL;
+	acpi_handle lcd_dev_handle	= NULL;
+
+	mods_debug_printk(DEBUG_ACPI,
+			  "ACPI _DDC (EDID) for device %04x:%x:%02x.%x\n",
+			  (unsigned int)pci_device->domain,
+			  (unsigned int)pci_device->bus,
+			  (unsigned int)pci_device->device,
+			  (unsigned int)pci_device->function);
+
+	{
+		unsigned int devfn = PCI_DEVFN(pci_device->device,
+					       pci_device->function);
+		struct pci_dev *dev = MODS_PCI_GET_SLOT(pci_device->domain,
+							pci_device->bus, devfn);
+		if (!dev) {
+			mods_error_printk("ACPI: PCI device not found\n");
+			return -EINVAL;
+		}
+		dev_handle = MODS_ACPI_HANDLE(&dev->dev);
+	}
+	if (!dev_handle) {
+		mods_debug_printk(DEBUG_ACPI,
+				  "ACPI: handle for _DDC not found\n");
+		return -EINVAL;
+	}
+	status = acpi_bus_get_device(dev_handle, &device);
+
+	if (ACPI_FAILURE(status) || !device) {
+		mods_error_printk("ACPI: device for _DDC not found\n");
+		return -EINVAL;
+	}
+
+	list_for_each_safe(node, next, &device->children) {
+#ifdef MODS_ACPI_DEVID_64
+		unsigned long long
+#else
+		unsigned long
+#endif
+			device_id = 0;
+
+		struct acpi_device *dev =
+			list_entry(node, struct acpi_device, node);
+
+		if (!dev)
+			continue;
+
+		status = acpi_evaluate_integer(dev->handle,
+					       "_ADR",
+					       NULL,
+					       &device_id);
+		if (ACPI_FAILURE(status))
+			/* Couldnt query device_id for this device */
+			continue;
+
+		device_id = (device_id & 0xffff);
+
+		if ((device_id == 0x0110) || /* Only for an LCD*/
+		    (device_id == 0x0118) ||
+		    (device_id == 0x0400)) {
+
+			lcd_dev_handle = dev->handle;
+			mods_debug_printk(DEBUG_ACPI,
+			    "ACPI: Found LCD 0x%x on device %04x:%x:%02x.%x\n",
+			    (unsigned int)device_id,
+			    (unsigned int)p->device.domain,
+			    (unsigned int)p->device.bus,
+			    (unsigned int)p->device.device,
+			    (unsigned int)p->device.function);
+			break;
+		}
+
+	}
+
+	if (lcd_dev_handle == NULL) {
+		mods_error_printk(
+			"ACPI: LCD not found for device %04x:%x:%02x.%x\n",
+			(unsigned int)p->device.domain,
+			(unsigned int)p->device.bus,
+			(unsigned int)p->device.device,
+			(unsigned int)p->device.function);
+		return -EINVAL;
+	}
+
+	/*
+	 * As per ACPI Spec 3.0:
+	 * ARG0 = 0x1 for 128 bytes EDID buffer
+	 * ARG0 = 0x2 for 256 bytes EDID buffer
+	 */
+	for (i = 1; i <= 2; i++) {
+		ddc_arg0.integer.value = i;
+		status = acpi_evaluate_object(lcd_dev_handle,
+					      "_DDC",
+					      &input,
+					      &output);
+		if (ACPI_SUCCESS(status))
+			break;
+	}
+
+	if (ACPI_FAILURE(status)) {
+		mods_error_printk("ACPI method _DDC (EDID) failed\n");
+		return -EINVAL;
+	}
+
+	ddc = output.pointer;
+	if (ddc && (ddc->type == ACPI_TYPE_BUFFER)
+		&& (ddc->buffer.length > 0)) {
+
+		if (ddc->buffer.length <= sizeof(p->out_buffer)) {
+			p->out_data_size = ddc->buffer.length;
+			memcpy(p->out_buffer,
+			       ddc->buffer.pointer,
+			       p->out_data_size);
+		} else {
+			mods_error_printk(
+		       "output buffer too small for ACPI method _DDC (EDID)\n");
+			kfree(output.pointer);
+			return -EINVAL;
+		}
+	} else {
+		mods_error_printk("unsupported ACPI output type\n");
+		kfree(output.pointer);
+		return -EINVAL;
+	}
+
+	kfree(output.pointer);
+	return OK;
+}
+
+/*************************
+ * ESCAPE CALL FUNCTIONS *
+ *************************/
+
+int esc_mods_eval_acpi_method(struct file *pfile,
+			      struct MODS_EVAL_ACPI_METHOD *p)
+{
+	return mods_eval_acpi_method(pfile, p, 0);
+}
+
+int esc_mods_eval_dev_acpi_method_2(struct file *pfile,
+				    struct MODS_EVAL_DEV_ACPI_METHOD_2 *p)
+{
+	return mods_eval_acpi_method(pfile, &p->method, &p->device);
+}
+
+int esc_mods_eval_dev_acpi_method(struct file *pfile,
+				  struct MODS_EVAL_DEV_ACPI_METHOD *p)
+{
+	struct mods_pci_dev_2 device = {0};
+
+	device.domain		= 0;
+	device.bus		= p->device.bus;
+	device.device		= p->device.device;
+	device.function		= p->device.function;
+	return mods_eval_acpi_method(pfile, &p->method, &device);
+}
+
+int esc_mods_acpi_get_ddc_2(struct file *pfile,
+			    struct MODS_ACPI_GET_DDC_2 *p)
+{
+	return mods_acpi_get_ddc(pfile, p, &p->device);
+}
+
+int esc_mods_acpi_get_ddc(struct file *pfile, struct MODS_ACPI_GET_DDC *p)
+{
+	struct MODS_ACPI_GET_DDC_2 *pp     = (struct MODS_ACPI_GET_DDC_2 *) p;
+	struct mods_pci_dev_2       device = {0};
+
+	device.domain	= 0;
+	device.bus	= p->device.bus;
+	device.device	= p->device.device;
+	device.function	= p->device.function;
+
+	return mods_acpi_get_ddc(pfile, pp, &device);
+}
diff --git a/drivers/misc/mods/mods_adsp.c b/drivers/misc/mods/mods_adsp.c
new file mode 100644
index 00000000..244dcc05
--- /dev/null
+++ b/drivers/misc/mods/mods_adsp.c
@@ -0,0 +1,95 @@
+/*
+ * mods_adsp.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/uaccess.h>
+#include "mods_internal.h"
+#include <linux/tegra_nvadsp.h>
+
+int esc_mods_adsp_load(struct file *pfile)
+{
+	return nvadsp_os_load();
+}
+
+int esc_mods_adsp_start(struct file *pfile)
+{
+	return nvadsp_os_start();
+}
+
+int esc_mods_adsp_stop(struct file *pfile)
+{
+	nvadsp_os_stop();
+	return OK;
+}
+
+int esc_mods_adsp_run_app(struct file *pfile, struct MODS_ADSP_RUN_APP_INFO *p)
+{
+	int rc = -1;
+	int max_retry = 3;
+	int rcount = 0;
+	nvadsp_app_handle_t handle;
+	nvadsp_app_info_t *p_app_info;
+	nvadsp_app_args_t app_args;
+
+	handle = nvadsp_app_load(p->app_name,  p->app_file_name);
+	if (!handle) {
+		mods_error_printk("load adsp app fail");
+		return -1;
+	}
+
+	if (p->argc > 0 && p->argc <= MODS_ADSP_APP_MAX_PARAM) {
+		app_args.argc = p->argc;
+		memcpy(app_args.argv, p->argv, p->argc * sizeof(__u32));
+		p_app_info = nvadsp_app_init(handle, &app_args);
+	} else
+		p_app_info = nvadsp_app_init(handle, NULL);
+
+	if (!p_app_info) {
+		mods_error_printk("init adsp app fail");
+		nvadsp_app_unload(handle);
+		return -1;
+	}
+
+	rc = nvadsp_app_start(p_app_info);
+	if (rc) {
+		mods_error_printk("start adsp app fail");
+		goto failed;
+	}
+
+	while (rcount++ < max_retry) {
+		rc = wait_for_nvadsp_app_complete_timeout(p_app_info,
+						msecs_to_jiffies(p->timeout));
+		if (rc == -ERESTARTSYS)
+			continue;
+		else if (rc == 0) {
+			mods_error_printk("app timeout(%d)", p->timeout);
+			rc = -1;
+		} else if (rc < 0) {
+			mods_error_printk("run app failed, err=%d\n", rc);
+			rc = -1;
+		} else
+			rc = 0;
+		break;
+	}
+
+failed:
+	nvadsp_app_deinit(p_app_info);
+	nvadsp_app_unload(handle);
+
+	return rc;
+}
diff --git a/drivers/misc/mods/mods_clock.c b/drivers/misc/mods/mods_clock.c
new file mode 100644
index 00000000..09101719
--- /dev/null
+++ b/drivers/misc/mods/mods_clock.c
@@ -0,0 +1,621 @@
+/*
+ * mods_clock.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mods_internal.h"
+#include <linux/clk.h>
+#include <linux/platform/tegra/clock.h>
+#if defined(CONFIG_TEGRA_CLK_FRAMEWORK)
+	#include <linux/clk/tegra.h>
+#elif defined(CONFIG_COMMON_CLK) && defined(CONFIG_OF_RESOLVE) && \
+defined(CONFIG_OF_DYNAMIC)
+	#define MODS_COMMON_CLK 1
+#endif
+#if defined(MODS_COMMON_CLK)
+	#include <linux/clk-provider.h>
+	#include <linux/of_device.h>
+	#include <linux/of.h>
+	#include <linux/of_fdt.h>
+	#include <linux/reset.h>
+	#define ARBITRARY_MAX_CLK_FREQ  3500000000
+#endif
+
+static struct list_head mods_clock_handles;
+static spinlock_t mods_clock_lock;
+static u32 last_handle;
+
+struct clock_entry {
+	struct clk *pclk;
+	u32 handle;
+	struct list_head list;
+};
+
+#if defined(MODS_COMMON_CLK)
+static struct device_node *find_clocks_node(const char *name)
+{
+	const char *node_name = "mods-simple-bus";
+	struct device_node *pp = NULL, *np = NULL;
+
+	pp = of_find_node_by_name(NULL, node_name);
+
+	if (!pp) {
+		mods_error_printk("'mods-simple-bus' node not found in device tree\n");
+		return pp;
+	}
+
+	np = of_get_child_by_name(pp, name);
+	return np;
+}
+#endif
+
+void mods_init_clock_api(void)
+{
+#if defined(MODS_COMMON_CLK)
+	const char *okay_value = "okay";
+	struct device_node *mods_np = 0;
+	struct property *pp = 0;
+	int size_value = 0;
+
+	mods_np = find_clocks_node("mods-clocks");
+	if (!mods_np) {
+		mods_error_printk("'mods-clocks' node not found in device tree\n");
+		goto err;
+	}
+
+	pp = of_find_property(mods_np, "status", NULL);
+	if (IS_ERR(pp)) {
+		mods_error_printk("'status' prop not found in 'mods-clocks' node.");
+		goto err;
+	}
+
+	/* if status is 'okay', then skip updating property */
+	if (of_device_is_available(mods_np))
+		goto err;
+
+	size_value = strlen(okay_value) + 1;
+	pp->value = kmalloc(size_value, GFP_KERNEL);
+	strncpy(pp->value, okay_value, size_value);
+	pp->length = size_value;
+
+err:
+	of_node_put(mods_np);
+#endif
+
+	spin_lock_init(&mods_clock_lock);
+	INIT_LIST_HEAD(&mods_clock_handles);
+	last_handle = 0;
+}
+
+void mods_shutdown_clock_api(void)
+{
+	struct list_head *head = &mods_clock_handles;
+	struct list_head *iter;
+	struct list_head *tmp;
+
+	spin_lock(&mods_clock_lock);
+
+	list_for_each_safe(iter, tmp, head) {
+		struct clock_entry *entry
+			= list_entry(iter, struct clock_entry, list);
+		list_del(iter);
+		kfree(entry);
+	}
+
+	spin_unlock(&mods_clock_lock);
+}
+
+static u32 mods_get_clock_handle(struct clk *pclk)
+{
+	struct list_head *head = &mods_clock_handles;
+	struct list_head *iter;
+	struct clock_entry *entry = 0;
+	u32 handle = 0;
+
+	spin_lock(&mods_clock_lock);
+
+	list_for_each(iter, head) {
+		struct clock_entry *cur
+			= list_entry(iter, struct clock_entry, list);
+		if (cur->pclk == pclk) {
+			entry = cur;
+			handle = cur->handle;
+			break;
+		}
+	}
+
+	if (!entry) {
+		entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
+		if (!unlikely(!entry)) {
+			entry->pclk = pclk;
+			entry->handle = ++last_handle;
+			handle = entry->handle;
+			list_add(&entry->list, &mods_clock_handles);
+		}
+	}
+
+	spin_unlock(&mods_clock_lock);
+
+	return handle;
+}
+
+static struct clk *mods_get_clock(u32 handle)
+{
+	struct list_head *head = &mods_clock_handles;
+	struct list_head *iter;
+	struct clk *pclk = 0;
+
+	spin_lock(&mods_clock_lock);
+
+	list_for_each(iter, head) {
+		struct clock_entry *entry
+			= list_entry(iter, struct clock_entry, list);
+		if (entry->handle == handle) {
+			pclk = entry->pclk;
+			break;
+		}
+	}
+
+	spin_unlock(&mods_clock_lock);
+
+	return pclk;
+}
+
+int esc_mods_get_clock_handle(struct file *pfile,
+			      struct MODS_GET_CLOCK_HANDLE *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+#if defined(CONFIG_TEGRA_CLK_FRAMEWORK)
+	LOG_ENT();
+
+	p->device_name[sizeof(p->device_name)-1] = 0;
+	p->controller_name[sizeof(p->controller_name)-1] = 0;
+	pclk = clk_get_sys(p->device_name, p->controller_name);
+
+	if (IS_ERR(pclk)) {
+		mods_error_printk("invalid clock specified: dev=%s, ctx=%s\n",
+				  p->device_name, p->controller_name);
+	} else {
+		p->clock_handle = mods_get_clock_handle(pclk);
+		ret = OK;
+	}
+#elif defined(MODS_COMMON_CLK)
+	struct device_node *mods_np = 0;
+	struct property *pp = 0;
+
+	LOG_ENT();
+
+	mods_np = find_clocks_node("mods-clocks");
+	if (!mods_np || !of_device_is_available(mods_np)) {
+		mods_error_printk("'mods-clocks' node not found in device tree\n");
+		goto err;
+	}
+	pp = of_find_property(mods_np, "clock-names", NULL);
+	if (IS_ERR(pp)) {
+		mods_error_printk(
+		    "No 'clock-names' prop in 'mods-clocks' node for dev %s\n",
+				  p->controller_name);
+		goto err;
+	}
+
+	pclk = of_clk_get_by_name(mods_np, p->controller_name);
+
+	if (IS_ERR(pclk))
+		mods_error_printk("clk (%s) not found\n", p->controller_name);
+	else {
+		p->clock_handle = mods_get_clock_handle(pclk);
+		ret = OK;
+	}
+err:
+	of_node_put(mods_np);
+#endif
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_set_clock_rate(struct file *pfile, struct MODS_CLOCK_RATE *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+
+	pclk = mods_get_clock(p->clock_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+	} else {
+		ret = clk_set_rate(pclk, p->clock_rate_hz);
+		if (ret) {
+			mods_error_printk(
+				"unable to set rate %lluHz on clock 0x%x\n",
+				p->clock_rate_hz, p->clock_handle);
+		} else {
+			mods_debug_printk(DEBUG_CLOCK,
+				  "successfuly set rate %lluHz on clock 0x%x\n",
+				  p->clock_rate_hz, p->clock_handle);
+		}
+	}
+
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_get_clock_rate(struct file *pfile, struct MODS_CLOCK_RATE *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+
+	pclk = mods_get_clock(p->clock_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+	} else {
+		p->clock_rate_hz = clk_get_rate(pclk);
+		mods_debug_printk(DEBUG_CLOCK, "clock 0x%x has rate %lluHz\n",
+				  p->clock_handle, p->clock_rate_hz);
+		ret = OK;
+	}
+
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_get_clock_max_rate(struct file *pfile, struct MODS_CLOCK_RATE *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+	pclk = mods_get_clock(p->clock_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+#if defined(CONFIG_TEGRA_CLK_FRAMEWORK)
+	} else if (!pclk->ops || !pclk->ops->round_rate) {
+		mods_error_printk(
+			"unable to detect max rate for clock handle 0x%x\n",
+			p->clock_handle);
+	} else {
+		long rate = pclk->ops->round_rate(pclk, pclk->max_rate);
+
+		p->clock_rate_hz = rate < 0 ? pclk->max_rate
+					    : (unsigned long)rate;
+#elif defined(MODS_COMMON_CLK)
+	} else {
+		long rate = clk_round_rate(pclk, ARBITRARY_MAX_CLK_FREQ);
+
+		p->clock_rate_hz = rate < 0 ? ARBITRARY_MAX_CLK_FREQ
+			: (unsigned long)rate;
+#endif
+		mods_debug_printk(DEBUG_CLOCK,
+				  "clock 0x%x has max rate %lluHz\n",
+				  p->clock_handle, p->clock_rate_hz);
+		ret = OK;
+	}
+
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_set_clock_max_rate(struct file *pfile, struct MODS_CLOCK_RATE *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+
+	pclk = mods_get_clock(p->clock_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+	} else {
+#if defined(CONFIG_TEGRA_CLOCK_DEBUG_FUNC)
+		ret = tegra_clk_set_max(pclk, p->clock_rate_hz);
+		if (ret) {
+			mods_error_printk(
+		"unable to override max clock rate %lluHz on clock 0x%x\n",
+					  p->clock_rate_hz, p->clock_handle);
+		} else {
+			mods_debug_printk(DEBUG_CLOCK,
+			  "successfuly set max rate %lluHz on clock 0x%x\n",
+					  p->clock_rate_hz, p->clock_handle);
+		}
+#else
+		mods_error_printk("unable to override max clock rate\n");
+		mods_error_printk(
+		"reconfigure kernel with CONFIG_TEGRA_CLOCK_DEBUG_FUNC=y\n");
+		ret = -EINVAL;
+#endif
+	}
+
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_set_clock_parent(struct file *pfile, struct MODS_CLOCK_PARENT *p)
+{
+	struct clk *pclk = 0;
+	struct clk *pparent = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+
+	pclk = mods_get_clock(p->clock_handle);
+	pparent = mods_get_clock(p->clock_parent_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+	} else if (!pparent) {
+		mods_error_printk("unrecognized parent clock handle: 0x%x\n",
+				  p->clock_parent_handle);
+	} else {
+		ret = clk_set_parent(pclk, pparent);
+		if (ret) {
+			mods_error_printk(
+			    "unable to make clock 0x%x parent of clock 0x%x\n",
+			    p->clock_parent_handle, p->clock_handle);
+		} else {
+			mods_debug_printk(DEBUG_CLOCK,
+			  "successfuly made clock 0x%x parent of clock 0x%x\n",
+			  p->clock_parent_handle, p->clock_handle);
+		}
+	}
+
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_get_clock_parent(struct file *pfile, struct MODS_CLOCK_PARENT *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+
+	pclk = mods_get_clock(p->clock_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+	} else {
+		struct clk *pparent = clk_get_parent(pclk);
+
+		p->clock_parent_handle = mods_get_clock_handle(pparent);
+		mods_debug_printk(DEBUG_CLOCK,
+				  "clock 0x%x is parent of clock 0x%x\n",
+				  p->clock_parent_handle, p->clock_handle);
+		ret = OK;
+	}
+
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_enable_clock(struct file *pfile, struct MODS_CLOCK_HANDLE *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+
+	pclk = mods_get_clock(p->clock_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+	} else {
+#if defined(MODS_COMMON_CLK)
+		ret = clk_prepare(pclk);
+		if (ret) {
+			mods_error_printk(
+			    "unable to prepare clock 0x%x before enabling\n",
+					  p->clock_handle);
+		}
+#endif
+		ret = clk_enable(pclk);
+		if (ret) {
+			mods_error_printk("failed to enable clock 0x%x\n",
+					  p->clock_handle);
+		} else {
+			mods_debug_printk(DEBUG_CLOCK, "clock 0x%x enabled\n",
+					  p->clock_handle);
+		}
+	}
+
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_disable_clock(struct file *pfile, struct MODS_CLOCK_HANDLE *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+
+	pclk = mods_get_clock(p->clock_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+	} else {
+		clk_disable(pclk);
+#if defined(MODS_COMMON_CLK)
+		clk_unprepare(pclk);
+#endif
+		mods_debug_printk(DEBUG_CLOCK, "clock 0x%x disabled\n",
+				  p->clock_handle);
+		ret = OK;
+	}
+
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_is_clock_enabled(struct file *pfile, struct MODS_CLOCK_ENABLED *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+
+	pclk = mods_get_clock(p->clock_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+	} else {
+#if defined(CONFIG_TEGRA_CLK_FRAMEWORK)
+		p->enable_count = pclk->refcnt;
+#elif defined(MODS_COMMON_CLK)
+		p->enable_count = (u32)__clk_is_enabled(pclk);
+#endif
+		mods_debug_printk(DEBUG_CLOCK, "clock 0x%x enable count is %u\n",
+				  p->clock_handle, p->enable_count);
+		ret = OK;
+	}
+
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_clock_reset_assert(struct file *pfile,
+				struct MODS_CLOCK_HANDLE *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+
+	pclk = mods_get_clock(p->clock_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+	} else {
+#if defined(MODS_COMMON_CLK)
+		const char *clk_name = 0;
+		struct reset_control *prst = 0;
+		struct device_node *mods_np = 0;
+		struct property *pp = 0;
+
+		mods_np = find_clocks_node("mods-clocks");
+		if (!mods_np || !of_device_is_available(mods_np)) {
+			mods_error_printk("'mods-clocks' node not found in DTB\n");
+			goto err;
+		}
+		pp = of_find_property(mods_np, "reset-names", NULL);
+		if (IS_ERR(pp)) {
+			mods_error_printk(
+		    "No 'reset-names' prop in 'mods-clocks' node for dev %s\n",
+					  __clk_get_name(pclk));
+			goto err;
+		}
+
+		clk_name = __clk_get_name(pclk);
+
+		prst = of_reset_control_get(mods_np, clk_name);
+		if (IS_ERR(prst)) {
+			mods_error_printk("reset device %s not found\n",
+					  clk_name);
+			goto err;
+		}
+		ret = reset_control_assert(prst);
+		if (ret) {
+			mods_error_printk("failed to assert reset on '%s'\n",
+					  clk_name);
+		} else {
+			mods_debug_printk(DEBUG_CLOCK, "asserted reset on '%s'",
+					  clk_name);
+		}
+
+err:
+		of_node_put(mods_np);
+#endif
+	}
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_clock_reset_deassert(struct file *pfile,
+				  struct MODS_CLOCK_HANDLE *p)
+{
+	struct clk *pclk = 0;
+	int ret = -EINVAL;
+
+	LOG_ENT();
+
+	pclk = mods_get_clock(p->clock_handle);
+
+	if (!pclk) {
+		mods_error_printk("unrecognized clock handle: 0x%x\n",
+				  p->clock_handle);
+	} else {
+#if defined(MODS_COMMON_CLK)
+		const char *clk_name = 0;
+		struct reset_control *prst = 0;
+		struct device_node *mods_np = 0;
+		struct property *pp = 0;
+
+		mods_np = find_clocks_node("mods-clocks");
+		if (!mods_np || !of_device_is_available(mods_np)) {
+			mods_error_printk("'mods-clocks' node not found in DTB\n");
+			goto err;
+		}
+		pp = of_find_property(mods_np, "reset-names", NULL);
+		if (IS_ERR(pp)) {
+			mods_error_printk(
+		    "No 'reset-names' prop in 'mods-clocks' node for dev %s\n",
+					  __clk_get_name(pclk));
+			goto err;
+		}
+
+		clk_name = __clk_get_name(pclk);
+
+		prst = of_reset_control_get(mods_np, clk_name);
+		if (IS_ERR(prst)) {
+			mods_error_printk(
+				"reset device %s not found\n", clk_name);
+			goto err;
+		}
+		ret = reset_control_deassert(prst);
+		if (ret) {
+			mods_error_printk("failed to assert reset on '%s'\n",
+					  clk_name);
+		} else {
+			mods_debug_printk(DEBUG_CLOCK, "deasserted reset on '%s'",
+					  clk_name);
+		}
+
+err:
+		of_node_put(mods_np);
+#endif
+	}
+
+	LOG_EXT();
+	return ret;
+}
diff --git a/drivers/misc/mods/mods_config.h b/drivers/misc/mods/mods_config.h
new file mode 100644
index 00000000..3978af12
--- /dev/null
+++ b/drivers/misc/mods/mods_config.h
@@ -0,0 +1,63 @@
+/*
+ * mods_config.h - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2008-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _MODS_CONFIG_H_
+#define _MODS_CONFIG_H_
+
+#define MODS_KERNEL_VERSION KERNEL_VERSION(3, 18, 0)
+
+#define MODS_IRQ_HANDLE_NO_REGS 1
+#define MODS_HAS_SET_MEMORY 1
+#define MODS_ACPI_DEVID_64 1
+#define MODS_HAS_WC 1
+#define MODS_HAS_DEV_TO_NUMA_NODE 1
+#define MODS_HAS_NEW_ACPI_WALK 1
+#ifdef CONFIG_DEBUG_FS
+#define MODS_HAS_DEBUGFS 1
+#endif
+#if defined(CONFIG_TEGRA_KFUSE)
+#define MODS_HAS_KFUSE 1
+#endif
+#ifdef CONFIG_DMA_SHARED_BUFFER
+#define MODS_HAS_DMABUF 1
+#endif
+#define MODS_MULTI_INSTANCE_DEFAULT_VALUE 1
+#define MODS_HAS_IORESOURCE_MEM_64 1
+#undef MODS_HAS_NEW_ACPI_HANDLE /* new in 3.13 */
+#if defined(CONFIG_ARCH_TEGRA)
+#define MODS_TEGRA 1
+#endif
+#if defined(CONFIG_TEGRA_CLK_FRAMEWORK) ||	\
+	(defined(CONFIG_COMMON_CLK) && defined(CONFIG_OF_RESOLVE) && \
+	 defined(CONFIG_OF_DYNAMIC))
+#define MODS_HAS_CLOCK 1
+#endif
+#ifdef CONFIG_NET
+#define MODS_HAS_NET 1
+#endif
+#ifdef CONFIG_ZONE_DMA32
+#define MODS_HAS_DMA32	1
+#endif
+#ifdef CONFIG_PCI
+#define MODS_CAN_REGISTER_PCI_DEV 1
+#endif
+
+#endif /* _MODS_CONFIG_H_  */
+
+/* vim: set ts=8 sw=8 noet: */
diff --git a/drivers/misc/mods/mods_debugfs.c b/drivers/misc/mods/mods_debugfs.c
new file mode 100644
index 00000000..50f484d7
--- /dev/null
+++ b/drivers/misc/mods/mods_debugfs.c
@@ -0,0 +1,807 @@
+/*
+ * mods_debugfs.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mods_internal.h"
+
+#ifdef MODS_HAS_DEBUGFS
+
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/miscdevice.h>
+#include <linux/device.h>
+#include <linux/uaccess.h>
+
+static struct dentry *mods_debugfs_dir;
+
+#if defined(MODS_TEGRA) && defined(MODS_HAS_KFUSE)
+#include <soc/tegra/kfuse.h>
+#endif
+
+#ifdef CONFIG_TEGRA_DC
+#include <video/tegra_dc_ext_kernel.h>
+#include <../drivers/video/tegra/dc/dc_config.h>
+#include <../drivers/video/tegra/dc/dsi.h>
+
+static int mods_dc_color_formats_show(struct seq_file *s, void *unused)
+{
+	struct tegra_dc *dc = s->private;
+	u32 i, j;
+
+	for (i = 0; i < tegra_dc_get_numof_dispwindows(); i++) {
+		struct tegra_dc_win *win;
+		u32 *fmt_masks;
+
+		win = tegra_dc_get_window(dc, i);
+		if (!win)
+			continue;
+		fmt_masks = tegra_dc_parse_feature(dc, i, GET_WIN_FORMATS);
+		if (!fmt_masks)
+			continue;
+		seq_printf(s, "window_%u:", i);
+		for (j = 0; j < ENTRY_SIZE; j++)
+			seq_printf(s, " 0x%08x", fmt_masks[j]);
+		seq_puts(s, "\n");
+	}
+	return 0;
+}
+
+static int mods_dc_color_formats_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_dc_color_formats_show, inode->i_private);
+}
+
+static const struct file_operations mods_dc_color_formats_fops = {
+	.open		= mods_dc_color_formats_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int mods_dc_blend_gen_show(struct seq_file *s, void *unused)
+{
+	struct tegra_dc *dc = s->private;
+	u32 i;
+
+	for (i = 0; i < tegra_dc_get_numof_dispwindows(); i++) {
+		struct tegra_dc_win *win;
+		u32 *blend_gen;
+
+		win = tegra_dc_get_window(dc, i);
+		if (!win)
+			continue;
+		blend_gen = tegra_dc_parse_feature(dc, i, HAS_GEN2_BLEND);
+		if (!blend_gen)
+			continue;
+		seq_printf(s, "window_%u: %u\n", i,
+			blend_gen[BLEND_GENERATION]);
+	}
+	return 0;
+}
+
+static int mods_dc_blend_gen_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_dc_blend_gen_show, inode->i_private);
+}
+
+static const struct file_operations mods_dc_blend_gen_fops = {
+	.open		= mods_dc_blend_gen_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int mods_dc_layout_show(struct seq_file *s, void *unused)
+{
+	struct tegra_dc *dc = s->private;
+	u32 i;
+
+	seq_puts(s, "          Pitch Tiled Block\n");
+	for (i = 0; i < tegra_dc_get_numof_dispwindows(); i++) {
+		struct tegra_dc_win *win;
+		u32 *layouts;
+
+		win = tegra_dc_get_window(dc, i);
+		if (!win)
+			continue;
+		layouts = tegra_dc_parse_feature(dc, i, HAS_TILED);
+		if (!layouts)
+			continue;
+		seq_printf(s, "window_%u: %5u %5u %5u\n", i,
+			layouts[PITCHED_LAYOUT],
+			layouts[TILED_LAYOUT],
+			layouts[BLOCK_LINEAR]);
+	}
+	return 0;
+}
+
+static int mods_dc_layout_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_dc_layout_show, inode->i_private);
+}
+
+static const struct file_operations mods_dc_layout_fops = {
+	.open		= mods_dc_layout_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int mods_dc_invert_show(struct seq_file *s, void *unused)
+{
+	struct tegra_dc *dc = s->private;
+	u32 i;
+
+	seq_puts(s, "          FlipH FlipV ScanColumn\n");
+	for (i = 0; i < tegra_dc_get_numof_dispwindows(); i++) {
+		struct tegra_dc_win *win;
+		u32 *invert_data;
+
+		win = tegra_dc_get_window(dc, i);
+		if (!win)
+			continue;
+		invert_data = tegra_dc_parse_feature(dc, i, GET_INVERT);
+		if (!invert_data)
+			continue;
+		seq_printf(s, "window_%u: %5u %5u %10u\n", i,
+			invert_data[H_INVERT],
+			invert_data[V_INVERT],
+			invert_data[SCAN_COLUMN]);
+	}
+	return 0;
+}
+
+static int mods_dc_invert_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_dc_invert_show, inode->i_private);
+}
+
+static const struct file_operations mods_dc_invert_fops = {
+	.open		= mods_dc_invert_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int mods_dc_interlaced_show(struct seq_file *s, void *unused)
+{
+	struct tegra_dc *dc = s->private;
+	u32 i;
+#ifdef CONFIG_TEGRA_DC_INTERLACE
+	const unsigned int head_interlaced = 1;
+#else
+	const unsigned int head_interlaced = 0;
+#endif
+
+	seq_printf(s, "head: %u\n", head_interlaced);
+	for (i = 0; i < tegra_dc_get_numof_dispwindows(); i++) {
+		struct tegra_dc_win *win;
+		u32 *interlaced;
+
+		win = tegra_dc_get_window(dc, i);
+
+		if (!win)
+			continue;
+		interlaced = tegra_dc_parse_feature(dc, i, HAS_INTERLACE);
+		if (!interlaced)
+			continue;
+		seq_printf(s, "window_%u: %u\n", i, interlaced[0]);
+	}
+	return 0;
+}
+
+static int mods_dc_interlaced_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_dc_interlaced_show, inode->i_private);
+}
+
+static const struct file_operations mods_dc_interlaced_fops = {
+	.open		= mods_dc_interlaced_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int mods_dc_window_mask_show(struct seq_file *s, void *unused)
+{
+	struct tegra_dc *dc = s->private;
+
+	seq_printf(s, "0x%02lx\n", dc->valid_windows);
+	return 0;
+}
+
+static int mods_dc_window_mask_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_dc_window_mask_show, inode->i_private);
+}
+
+static const struct file_operations mods_dc_window_mask_fops = {
+	.open		= mods_dc_window_mask_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int mods_dc_scaling_show(struct seq_file *s, void *unused)
+{
+	struct tegra_dc *dc = s->private;
+	u32 i;
+
+	seq_puts(s, "          UpH UpV DownH DownV\n");
+	for (i = 0; i < tegra_dc_get_numof_dispwindows(); i++) {
+		struct tegra_dc_win *win;
+		u32 *scaling;
+
+		win = tegra_dc_get_window(dc, i);
+		if (!win)
+			continue;
+		scaling = tegra_dc_parse_feature(dc, i, HAS_SCALE);
+		if (!scaling)
+			continue;
+		seq_printf(s, "window_%u: %3u %3u %5u %5u\n", i,
+			scaling[H_SCALE_UP],
+			scaling[V_SCALE_UP],
+			scaling[H_FILTER_DOWN],
+			scaling[V_FILTER_DOWN]);
+	}
+	return 0;
+}
+
+static int mods_dc_scaling_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_dc_scaling_show, inode->i_private);
+}
+
+static const struct file_operations mods_dc_scaling_fops = {
+	.open		= mods_dc_scaling_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int mods_dsi_ganged_get(void *data, u64 *val)
+{
+	struct tegra_dc_dsi_data *dsi = data;
+
+	*val = (u64)dsi->info.ganged_type;
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(mods_dsi_ganged_fops, mods_dsi_ganged_get, NULL,
+	"%llu\n");
+
+static int mods_dsi_inst_get(void *data, u64 *val)
+{
+	struct tegra_dc_dsi_data *dsi = data;
+
+	*val = (u64)dsi->info.dsi_instance;
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(mods_dsi_inst_fops, mods_dsi_inst_get, NULL, "%llu\n");
+
+static int mods_dc_border_get(void *data, u64 *val)
+{
+	struct tegra_dc *dc = data;
+#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
+	u32 blender_reg = DC_DISP_BORDER_COLOR;
+#else
+	u32 blender_reg = DC_DISP_BLEND_BACKGROUND_COLOR;
+#endif
+	if (!dc->enabled)
+		*val = 0ULL;
+	else
+		*val = (u64)tegra_dc_readl_exported(dc, blender_reg);
+	return 0;
+}
+static int mods_dc_border_set(void *data, u64 val)
+{
+	struct tegra_dc *dc = data;
+#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
+	u32 blender_reg = DC_DISP_BORDER_COLOR;
+#else
+	u32 blender_reg = DC_DISP_BLEND_BACKGROUND_COLOR;
+#endif
+	if (!dc->enabled)
+		return 0;
+	mutex_lock(&dc->lock);
+	tegra_dc_get(dc);
+	tegra_dc_writel_exported(dc, val, blender_reg);
+	tegra_dc_writel_exported(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
+	tegra_dc_put(dc);
+	mutex_unlock(&dc->lock);
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(mods_dc_border_fops, mods_dc_border_get,
+	mods_dc_border_set, "0x%llx\n");
+
+static int mods_sd_brightness_get(void *data, u64 *val)
+{
+	struct tegra_dc *dc = data;
+
+	if (!dc->enabled)
+		*val = 0ULL;
+	else {
+		*val = (u64)tegra_dc_readl_exported(dc, DC_DISP_SD_BL_CONTROL);
+		*val = SD_BLC_BRIGHTNESS(*val);
+	}
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(mods_sd_brightness_fops, mods_sd_brightness_get,
+	NULL, "%llu\n");
+
+static int mods_sd_pixel_count_get(void *data, u64 *val)
+{
+	struct tegra_dc *dc = data;
+
+	if (!dc->enabled)
+		*val = 0ULL;
+	else
+		*val = (u64)tegra_dc_readl_exported(dc, DC_DISP_SD_PIXEL_COUNT);
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(mods_sd_pixel_count_fops, mods_sd_pixel_count_get,
+	NULL, "%llu\n");
+
+static int mods_sd_hw_k_rgb_show(struct seq_file *s, void *unused)
+{
+	struct tegra_dc *dc = s->private;
+	u32 val;
+
+	if (!dc->enabled)
+		val = 0U;
+	else
+		val = tegra_dc_readl_exported(dc, DC_DISP_SD_HW_K_VALUES);
+
+	seq_printf(s, "%u %u %u\n", SD_HW_K_R(val), SD_HW_K_G(val),
+		SD_HW_K_B(val));
+	return 0;
+}
+
+static int mods_sd_hw_k_rgb_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_sd_hw_k_rgb_show, inode->i_private);
+}
+
+static const struct file_operations mods_sd_hw_k_rgb_fops = {
+	.open		= mods_sd_hw_k_rgb_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int mods_sd_histogram_show(struct seq_file *s, void *unused)
+{
+	struct tegra_dc *dc = s->private;
+	u32 i;
+
+	for (i = 0; i < DC_DISP_SD_HISTOGRAM_NUM; i++) {
+		u32 val;
+
+		if (!dc->enabled)
+			val = 0U;
+		else
+			val = tegra_dc_readl_exported(dc,
+						      DC_DISP_SD_HISTOGRAM(i));
+		seq_printf(s, "%u %u %u %u\n",
+			SD_HISTOGRAM_BIN_0(val),
+			SD_HISTOGRAM_BIN_1(val),
+			SD_HISTOGRAM_BIN_2(val),
+			SD_HISTOGRAM_BIN_3(val));
+	}
+
+	return 0;
+}
+
+static int mods_sd_histogram_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_sd_histogram_show, inode->i_private);
+}
+
+static const struct file_operations mods_sd_histogram_fops = {
+	.open		= mods_sd_histogram_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+
+static int mods_dc_ocp_show(struct seq_file *s, void *unused)
+{
+	seq_puts(s, "rgb\n");
+	return 0;
+}
+
+static int mods_dc_ocp_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_dc_ocp_show, inode->i_private);
+}
+
+static const struct file_operations mods_dc_ocp_fops = {
+	.open		= mods_dc_ocp_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+
+#define DC_DISP_CSC2_CONTROL		0x4ef
+#define  CSC2_OUTPUT_COLOR_RGB		(0 << 0)
+#define  CSC2_OUTPUT_COLOR_709		(1 << 0)
+#define  CSC2_OUTPUT_COLOR_601		(2 << 0)
+#define  CSC2_OUTPUT_COLOR(val)		(val & 0x3)
+#define  CSC2_LIMIT_RGB_DISABLE		(0 << 2)
+#define  CSC2_LIMIT_RGB_ENABLE		(1 << 2)
+
+static int mods_dc_oc_show(struct seq_file *s, void *unused)
+{
+	seq_puts(s, "rgb\n");
+	return 0;
+}
+
+static int mods_dc_oc_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_dc_oc_show, inode->i_private);
+}
+
+static ssize_t mods_dc_oc_write(struct file *file, const char __user *user_buf,
+			      size_t size, loff_t *ppos)
+{
+	char buf[8];
+	int buf_size;
+
+	buf_size = min(size, (sizeof(buf) - 1));
+	if (strncpy_from_user(buf, user_buf, buf_size) < 0)
+		return -EFAULT;
+	buf[buf_size] = 0;
+
+	if (strncmp(buf, "rgb", 3) != 0)
+		return -EINVAL;
+	*ppos += size;
+	return size;
+}
+
+static const struct file_operations mods_dc_oc_fops = {
+	.open		= mods_dc_oc_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+	.write		= mods_dc_oc_write,
+};
+
+static int mods_dc_ddc_bus_get(void *data, u64 *val)
+{
+	struct tegra_dc *dc = data;
+	*val = dc->out->ddc_bus;
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(mods_dc_ddc_bus_fops, mods_dc_ddc_bus_get,
+	NULL, "%lld\n");
+
+
+static int mods_dc_crc_latched_show(struct seq_file *s, void *unused)
+{
+	struct tegra_dc *dc = s->private;
+	u32 crc = tegra_dc_read_checksum_latched(dc);
+	u32 field = 0;
+
+#ifdef CONFIG_TEGRA_DC_INTERLACE
+	{
+		u32 val;
+
+		val = tegra_dc_readl_exported(dc, DC_DISP_INTERLACE_CONTROL);
+		if (val & INTERLACE_MODE_ENABLE)
+			field = (val & INTERLACE_STATUS_FIELD_2) ? 1 : 0;
+	}
+#endif
+	seq_printf(s, "0x%08x %u\n", crc, field);
+
+	return 0;
+}
+
+static int mods_dc_crc_latched_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_dc_crc_latched_show, inode->i_private);
+}
+
+static const struct file_operations mods_dc_crc_latched_fops = {
+	.open		= mods_dc_crc_latched_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+#endif /* CONFIG_TEGRA_DC */
+
+#if defined(MODS_TEGRA) && defined(MODS_HAS_KFUSE)
+static int mods_kfuse_show(struct seq_file *s, void *unused)
+{
+	unsigned int buf[KFUSE_DATA_SZ / 4];
+
+	/* copy load kfuse into buffer - only needed for early Tegra parts */
+	int ret = tegra_kfuse_read(buf, sizeof(buf));
+	int i;
+
+	if (ret)
+		return ret;
+
+	for (i = 0; i < KFUSE_DATA_SZ / 4; i += 4)
+		seq_printf(s, "0x%08x 0x%08x 0x%08x 0x%08x\n",
+			buf[i], buf[i+1], buf[i+2], buf[i+3]);
+
+	return 0;
+}
+
+static int mods_kfuse_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mods_kfuse_show, inode->i_private);
+}
+
+static const struct file_operations mods_kfuse_fops = {
+	.open		= mods_kfuse_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+#endif /* MODS_TEGRA */
+
+static int mods_debug_get(void *data, u64 *val)
+{
+	*val = (u64)(mods_get_debug_level() & DEBUG_ALL);
+	return 0;
+}
+static int mods_debug_set(void *data, u64 val)
+{
+	mods_set_debug_level((int)val & DEBUG_ALL);
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(mods_debug_fops, mods_debug_get, mods_debug_set,
+						"0x%08llx\n");
+
+static int mods_mi_get(void *data, u64 *val)
+{
+	*val = (u64)mods_get_multi_instance();
+	return 0;
+}
+static int mods_mi_set(void *data, u64 val)
+{
+	mods_set_multi_instance((int)val);
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(mods_mi_fops, mods_mi_get, mods_mi_set, "%llu\n");
+#endif /* MODS_HAS_DEBUGFS */
+
+void mods_remove_debugfs(void)
+{
+#ifdef MODS_HAS_DEBUGFS
+	debugfs_remove_recursive(mods_debugfs_dir);
+	mods_debugfs_dir = NULL;
+#endif
+}
+
+int mods_create_debugfs(struct miscdevice *modsdev)
+{
+#ifdef MODS_HAS_DEBUGFS
+	struct dentry *retval;
+#ifdef CONFIG_TEGRA_DC
+	unsigned int dc_idx;
+	int nheads = tegra_dc_get_numof_dispheads();
+#endif
+	int err = 0;
+
+#ifdef CONFIG_TEGRA_DC
+	if (nheads <= 0) {
+		pr_err("%s: max heads:%d cannot be negative or zero\n",
+			__func__, nheads);
+		return -EINVAL;
+	}
+#endif
+
+	mods_debugfs_dir = debugfs_create_dir(dev_name(modsdev->this_device),
+		NULL);
+	if (IS_ERR(mods_debugfs_dir)) {
+		err = -EIO;
+		goto remove_out;
+	}
+
+	retval = debugfs_create_file("debug", 0644,
+		mods_debugfs_dir, 0, &mods_debug_fops);
+	if (IS_ERR(retval)) {
+		err = -EIO;
+		goto remove_out;
+	}
+
+	retval = debugfs_create_file("multi_instance", 0644,
+		mods_debugfs_dir, 0, &mods_mi_fops);
+	if (IS_ERR(retval)) {
+		err = -EIO;
+		goto remove_out;
+	}
+
+#if defined(MODS_TEGRA) && defined(MODS_HAS_KFUSE)
+	retval = debugfs_create_file("kfuse_data", 0444,
+		mods_debugfs_dir, 0, &mods_kfuse_fops);
+	if (IS_ERR(retval)) {
+		err = -EIO;
+		goto remove_out;
+	}
+#endif
+
+#ifdef CONFIG_TEGRA_DC
+	for (dc_idx = 0; dc_idx < nheads; dc_idx++) {
+		struct dentry *dc_debugfs_dir;
+#ifdef CONFIG_TEGRA_NVSD
+		struct dentry *sd_debugfs_dir;
+#endif
+		char devname[16];
+		struct tegra_dc *dc = tegra_dc_get_dc(dc_idx);
+
+		if (!dc)
+			continue;
+
+		snprintf(devname, sizeof(devname), "tegradc.%d", dc->ctrl_num);
+		dc_debugfs_dir = debugfs_create_dir(devname, mods_debugfs_dir);
+
+		if (IS_ERR(dc_debugfs_dir)) {
+			err = -EIO;
+			goto remove_out;
+		}
+
+		retval = debugfs_create_file("window_mask", 0444,
+			dc_debugfs_dir, dc, &mods_dc_window_mask_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("color_formats", 0444,
+			dc_debugfs_dir, dc, &mods_dc_color_formats_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("blend_gen", 0444,
+			dc_debugfs_dir, dc, &mods_dc_blend_gen_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("layout", 0444, dc_debugfs_dir,
+			dc, &mods_dc_layout_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("invert", 0444, dc_debugfs_dir,
+			dc, &mods_dc_invert_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("interlaced", 0444,
+			dc_debugfs_dir, dc, &mods_dc_interlaced_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("scaling", 0444, dc_debugfs_dir,
+			dc, &mods_dc_scaling_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("border_color", 0644,
+			dc_debugfs_dir, dc, &mods_dc_border_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+
+		retval = debugfs_create_file("output_color_possible", 0444,
+			dc_debugfs_dir, NULL, &mods_dc_ocp_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("output_color", 0644,
+			dc_debugfs_dir, dc, &mods_dc_oc_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+
+		retval = debugfs_create_file("crc_checksum_latched", 0444,
+			dc_debugfs_dir, dc, &mods_dc_crc_latched_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+
+#if defined(CONFIG_TEGRA_NVSD)
+		sd_debugfs_dir = debugfs_create_dir("smartdimmer",
+			dc_debugfs_dir);
+
+		retval = debugfs_create_file("brightness", 0444,
+			sd_debugfs_dir, dc, &mods_sd_brightness_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("pixel_count", 0444,
+			sd_debugfs_dir, dc, &mods_sd_pixel_count_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("hw_k_rgb", 0444,
+			sd_debugfs_dir, dc, &mods_sd_hw_k_rgb_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+		retval = debugfs_create_file("histogram", 0444,
+			sd_debugfs_dir, dc, &mods_sd_histogram_fops);
+		if (IS_ERR(retval)) {
+			err = -EIO;
+			goto remove_out;
+		}
+#endif
+
+		if (dc->out && dc->out->type == TEGRA_DC_OUT_DSI) {
+			struct dentry *dsi_debugfs_dir;
+
+			dsi_debugfs_dir = debugfs_create_dir("dsi",
+				dc_debugfs_dir);
+			if (IS_ERR(dsi_debugfs_dir)) {
+				err = -EIO;
+				goto remove_out;
+			}
+			retval = debugfs_create_file("ganged", 0444,
+				dsi_debugfs_dir, tegra_dc_get_outdata(dc),
+				&mods_dsi_ganged_fops);
+			if (IS_ERR(retval)) {
+				err = -EIO;
+				goto remove_out;
+			}
+			retval = debugfs_create_file("instance", 0444,
+				dsi_debugfs_dir, tegra_dc_get_outdata(dc),
+				&mods_dsi_inst_fops);
+			if (IS_ERR(retval)) {
+				err = -EIO;
+				goto remove_out;
+			}
+		}
+
+		if (dc->out && dc->out->type == TEGRA_DC_OUT_HDMI) {
+			retval = debugfs_create_file("ddc_bus", 0444,
+				dc_debugfs_dir, dc, &mods_dc_ddc_bus_fops);
+			if (IS_ERR(retval)) {
+				err = -EIO;
+				goto remove_out;
+			}
+		}
+	}
+#endif
+
+	return 0;
+remove_out:
+	dev_err(modsdev->this_device, "could not create debugfs\n");
+	mods_remove_debugfs();
+	return err;
+#else
+	return 0;
+#endif
+}
+
diff --git a/drivers/misc/mods/mods_dma.c b/drivers/misc/mods/mods_dma.c
new file mode 100644
index 00000000..2fd58146
--- /dev/null
+++ b/drivers/misc/mods/mods_dma.c
@@ -0,0 +1,502 @@
+/*
+ * mods_dma.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/uaccess.h>
+#include <linux/dmaengine.h>
+#include "mods_internal.h"
+
+#define MODS_DMA_MAX_CHANNEL 32
+struct mods_dma_chan_info {
+	rwlock_t lock;
+	bool    in_use;
+	u32     id;
+	struct  dma_chan *pch;
+	bool    should_notify;
+};
+
+static DECLARE_BITMAP(dma_info_mask, MODS_DMA_MAX_CHANNEL);
+static struct mods_dma_chan_info dma_info_chan_list[MODS_DMA_MAX_CHANNEL];
+static DEFINE_SPINLOCK(dma_info_lock);
+
+int mods_get_dma_id(u32 *p_id)
+{
+	u32 id;
+
+	spin_lock(&dma_info_lock);
+	id = find_first_zero_bit(dma_info_mask, MODS_DMA_MAX_CHANNEL);
+	if (id >= MODS_DMA_MAX_CHANNEL) {
+		spin_unlock(&dma_info_lock);
+		return -ENOSPC;
+	}
+	set_bit(id, dma_info_mask);
+	spin_unlock(&dma_info_lock);
+
+	*p_id = id;
+	return OK;
+}
+
+void mods_release_dma_id(u32 id)
+{
+	spin_lock(&dma_info_lock);
+	clear_bit(id, dma_info_mask);
+	spin_unlock(&dma_info_lock);
+}
+
+int mods_get_chan_by_id(u32 id, struct mods_dma_chan_info **p_dma_chan)
+{
+	if (id > MODS_DMA_MAX_CHANNEL)
+		return	-ERANGE;
+
+	*p_dma_chan = &dma_info_chan_list[id];
+
+	return OK;
+}
+
+int mods_init_dma(void)
+{
+	struct mods_dma_chan_info *p_chan_info;
+	int i;
+
+	for (i = 0; i < MODS_DMA_MAX_CHANNEL; i++) {
+		p_chan_info = &dma_info_chan_list[i];
+		rwlock_init(&(p_chan_info->lock));
+		p_chan_info->in_use = false;
+	}
+
+	return OK;
+}
+
+void mods_release_channel(u32 id)
+{
+	struct mods_dma_chan_info *p_mods_chan;
+	struct dma_chan *pch = 0;
+
+	if (mods_get_chan_by_id(id, &p_mods_chan) != OK) {
+		mods_error_printk("get dma channel failed, id %d\n", id);
+		return;
+	}
+
+	write_lock(&(p_mods_chan->lock));
+	if (p_mods_chan->in_use) {
+		pch = p_mods_chan->pch;
+		p_mods_chan->pch = NULL;
+		mods_release_dma_id(id);
+		p_mods_chan->in_use = false;
+	}
+	write_unlock(&(p_mods_chan->lock));
+
+	/* do not call this when hold spin lock */
+	if (pch) {
+		dmaengine_terminate_all(pch);
+		dma_release_channel(pch);
+	}
+}
+
+void mods_exit_dma(void)
+{
+	int i;
+
+	for (i = 0; i < MODS_DMA_MAX_CHANNEL; i++)
+		mods_release_channel(i);
+}
+
+bool mods_chan_is_inuse(struct mods_dma_chan_info *p_mods_chan)
+{
+	bool in_use = false;
+
+	read_lock(&(p_mods_chan->lock));
+	if (p_mods_chan->in_use)
+		in_use = true;
+	read_unlock(&(p_mods_chan->lock));
+
+	return in_use;
+}
+
+int mods_get_inuse_chan_by_handle(struct MODS_DMA_HANDLE *p_handle,
+				  struct mods_dma_chan_info **p_mods_chan)
+{
+	int ret;
+	bool in_use;
+	struct mods_dma_chan_info *p_mods_ch;
+
+	ret = mods_get_chan_by_id(p_handle->dma_id, &p_mods_ch);
+	if (ret != OK) {
+		mods_error_printk("get dma channel failed, id %d\n",
+				  p_handle->dma_id);
+		return -ENODEV;
+	}
+
+	in_use = mods_chan_is_inuse(p_mods_ch);
+	if (!in_use) {
+		mods_error_printk("invalid dma channel: %d, not in use\n",
+				  p_handle->dma_id);
+		return -EINVAL;
+	}
+	*p_mods_chan = p_mods_ch;
+	return OK;
+}
+
+int mods_dma_sync_wait(struct MODS_DMA_HANDLE *p_handle,
+		       mods_dma_cookie_t cookie)
+{
+	int ret = OK;
+	struct mods_dma_chan_info *p_mods_chan;
+
+	ret = mods_get_inuse_chan_by_handle(p_handle, &p_mods_chan);
+	if (ret != OK)
+		return ret;
+
+	mods_debug_printk(DEBUG_TEGRADMA,
+			  "Wait on chan: %p\n", p_mods_chan->pch);
+	read_lock(&(p_mods_chan->lock));
+	if (dma_sync_wait(p_mods_chan->pch, cookie) != DMA_COMPLETE)
+		ret = -1;
+	read_unlock(&(p_mods_chan->lock));
+
+	return ret;
+}
+
+int mods_dma_async_is_tx_complete(struct MODS_DMA_HANDLE *p_handle,
+				  mods_dma_cookie_t cookie,
+				  __u32 *p_is_complete)
+{
+	int ret = OK;
+	struct mods_dma_chan_info *p_mods_chan;
+	enum dma_status status;
+
+	ret = mods_get_inuse_chan_by_handle(p_handle, &p_mods_chan);
+	if (ret != OK)
+		return ret;
+
+	read_lock(&(p_mods_chan->lock));
+	status = dma_async_is_tx_complete(p_mods_chan->pch, cookie, NULL, NULL);
+	read_unlock(&(p_mods_chan->lock));
+
+	if (status == DMA_COMPLETE)
+		*p_is_complete = true;
+	else if (status == DMA_IN_PROGRESS)
+		*p_is_complete = false;
+	else
+		ret = -EINVAL;
+
+	return ret;
+}
+
+int esc_mods_dma_request_channel(struct file *pfile,
+				 struct MODS_DMA_HANDLE *p_handle)
+{
+	struct dma_chan *chan;
+	struct mods_dma_chan_info *p_mods_chan;
+	dma_cap_mask_t mask;
+	u32 id;
+	int ret;
+
+	LOG_ENT();
+
+	ret = mods_get_dma_id(&id);
+	if (ret != OK) {
+		mods_error_printk("no dma handle available\n");
+		return ret;
+	}
+
+	ret = mods_get_chan_by_id(id, &p_mods_chan);
+	if (ret != OK) {
+		mods_error_printk("get dma channel failed\n");
+		return ret;
+	}
+
+	read_lock(&(p_mods_chan->lock));
+	if (p_mods_chan->in_use) {
+		mods_error_printk("mods dma channel in use\n");
+		read_unlock(&(p_mods_chan->lock));
+		return -EBUSY;
+	}
+	read_unlock(&(p_mods_chan->lock));
+
+	dma_cap_zero(mask);
+	dma_cap_set(p_handle->dma_type, mask);
+	chan = dma_request_channel(mask, NULL, NULL);
+	if (!chan) {
+		mods_error_printk("Dma channel is not available\n");
+		mods_release_dma_id(id);
+		return -EBUSY;
+	}
+
+	write_lock(&(p_mods_chan->lock));
+	p_mods_chan->pch = chan;
+	p_mods_chan->in_use = true;
+	write_unlock(&(p_mods_chan->lock));
+
+	p_handle->dma_id = id;
+	mods_debug_printk(DEBUG_TEGRADMA,
+			  "request get dma id: %d\n", id);
+	LOG_EXT();
+
+	return 0;
+}
+
+int esc_mods_dma_release_channel(struct file *pfile,
+				 struct MODS_DMA_HANDLE *p_handle)
+{
+	mods_release_channel(p_handle->dma_id);
+	return OK;
+}
+
+int esc_mods_dma_set_config(struct file *pfile,
+			    struct MODS_DMA_CHANNEL_CONFIG *p_config)
+
+{
+	struct dma_slave_config config;
+	struct mods_dma_chan_info *p_mods_chan;
+	int ret;
+
+	LOG_ENT();
+	ret = mods_get_inuse_chan_by_handle(&p_config->handle, &p_mods_chan);
+	if (ret != OK)
+		return ret;
+
+	config.direction = p_config->direction;
+	config.src_addr = p_config->src_addr;
+	config.dst_addr = p_config->dst_addr;
+	config.src_addr_width = p_config->src_addr_width;
+	config.dst_addr_width = p_config->dst_addr_width;
+	config.src_maxburst = p_config->src_maxburst;
+	config.dst_maxburst = p_config->dst_maxburst;
+	config.device_fc = (p_config->device_fc == 0) ? false : true;
+	config.slave_id = p_config->slave_id;
+
+	mods_debug_printk(DEBUG_TEGRADMA,
+			  "ch: %d dir [%d], addr[%p -> %p], burst [%d %d]",
+			  p_config->handle.dma_id,
+			  config.direction,
+			  (void *)config.src_addr, (void *)config.dst_addr,
+			  config.src_maxburst, config.dst_maxburst);
+	mods_debug_printk(DEBUG_TEGRADMA,
+			  "width [%d %d] slave id %d\n",
+			  config.src_addr_width, config.dst_addr_width,
+			  config.slave_id);
+
+	write_lock(&(p_mods_chan->lock));
+	ret = dmaengine_slave_config(p_mods_chan->pch, &config);
+	write_unlock(&(p_mods_chan->lock));
+
+	LOG_EXT();
+
+	return ret;
+}
+
+
+int esc_mods_dma_submit_request(struct file *pfile,
+				struct MODS_DMA_TX_DESC *p_mods_desc)
+{
+	int ret = OK;
+	struct mods_dma_chan_info *p_mods_chan;
+	struct dma_async_tx_descriptor *desc;
+	struct dma_device       *dev;
+	enum dma_ctrl_flags     flags;
+	mods_dma_cookie_t cookie = 0;
+
+	LOG_ENT();
+	flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
+
+	ret = mods_get_inuse_chan_by_handle(&p_mods_desc->handle, &p_mods_chan);
+	if (ret != OK)
+		return ret;
+
+	if (p_mods_desc->mode != MODS_DMA_SINGLE) {
+		mods_error_printk("Unsupported Mode: %d\n", p_mods_desc->mode);
+		return -EINVAL;
+	}
+
+	mods_debug_printk(DEBUG_TEGRADMA,
+			  "Submit on chan %p\n", p_mods_chan->pch);
+
+	write_lock(&(p_mods_chan->lock));
+	if (p_mods_desc->data_dir == MODS_DMA_MEM_TO_MEM) {
+		dev = p_mods_chan->pch->device;
+		desc = dev->device_prep_dma_memcpy(
+						p_mods_chan->pch,
+						p_mods_desc->phys,
+						p_mods_desc->phys_2,
+						p_mods_desc->length,
+						flags);
+	} else {
+		mods_debug_printk(DEBUG_TEGRADMA,
+				  "Phys Addr [%p], len [%d], dir [%d]\n",
+					(void *)p_mods_desc->phys,
+					p_mods_desc->length,
+					p_mods_desc->data_dir);
+		desc = dmaengine_prep_slave_single(
+							p_mods_chan->pch,
+							p_mods_desc->phys,
+							p_mods_desc->length,
+							p_mods_desc->data_dir,
+							flags);
+	}
+
+	if (desc == NULL) {
+		mods_error_printk("Not able to get desc for Tx\n");
+		ret = -EIO;
+		goto failed;
+	}
+
+	desc->callback = NULL;
+	desc->callback_param = NULL;
+	cookie = dmaengine_submit(desc);
+
+failed:
+	write_unlock(&(p_mods_chan->lock));
+	if (dma_submit_error(cookie)) {
+		mods_info_printk("Submit cookie: %x Error\n", cookie);
+		return -EIO;
+	}
+
+	p_mods_desc->cookie = cookie;
+
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_dma_async_issue_pending(struct file *pfile,
+				     struct MODS_DMA_HANDLE *p_handle)
+{
+	int ret = OK;
+	struct mods_dma_chan_info *p_mods_chan;
+
+	LOG_ENT();
+	ret = mods_get_inuse_chan_by_handle(p_handle, &p_mods_chan);
+	if (ret != OK)
+		return ret;
+
+	mods_debug_printk(DEBUG_TEGRADMA,
+			  "Issue pending on chan: %p\n", p_mods_chan->pch);
+	read_lock(&(p_mods_chan->lock));
+	dma_async_issue_pending(p_mods_chan->pch);
+	read_unlock(&(p_mods_chan->lock));
+	LOG_EXT();
+
+	return ret;
+}
+
+int esc_mods_dma_wait(struct file *pfile,
+		      struct MODS_DMA_WAIT_DESC *p_wait_desc)
+{
+	int ret;
+
+	LOG_ENT();
+	if (p_wait_desc->type == MODS_DMA_SYNC_WAIT)
+		ret = mods_dma_sync_wait(&p_wait_desc->handle,
+					 p_wait_desc->cookie);
+	else if (p_wait_desc->type == MODS_DMA_ASYNC_WAIT)
+		ret = mods_dma_async_is_tx_complete(&p_wait_desc->handle,
+						    p_wait_desc->cookie,
+						    &p_wait_desc->tx_complete);
+	else
+		ret = -EINVAL;
+
+	LOG_EXT();
+	return  ret;
+}
+
+int esc_mods_dma_alloc_coherent(struct file                    *fp,
+				struct MODS_DMA_COHERENT_MEM_HANDLE *p)
+{
+	dma_addr_t    p_phys_addr;
+	void          *p_cpu_addr;
+
+	LOG_ENT();
+
+	p_cpu_addr = dma_alloc_coherent(NULL,
+					p->num_bytes,
+					&p_phys_addr,
+					GFP_KERNEL);
+
+	mods_debug_printk(DEBUG_MEM,
+		"%s:num_bytes=%d, p_cpu_addr=%p, p_phys_addr=%p\n",
+		__func__,
+		p->num_bytes,
+		(void *)p_cpu_addr,
+		(void *)p_phys_addr);
+
+	if (!p_cpu_addr) {
+		mods_error_printk(
+		"%s:FAILED!!!num_bytes=%d, p_cpu_addr=%p, p_phys_addr=%p\n",
+		__func__,
+		p->num_bytes,
+		(void *)p_cpu_addr,
+		(void *)p_phys_addr);
+		LOG_EXT();
+		return -1;
+	}
+
+	memset(p_cpu_addr, 0x00, p->num_bytes);
+
+	p->memory_handle_phys = (u64)p_phys_addr;
+	p->memory_handle_virt = (u64)p_cpu_addr;
+
+	LOG_EXT();
+	return 0;
+}
+
+int esc_mods_dma_free_coherent(struct file                    *fp,
+				struct MODS_DMA_COHERENT_MEM_HANDLE *p)
+{
+	LOG_ENT();
+
+	mods_debug_printk(DEBUG_MEM,
+		"%s : num_bytes = %d, p_cpu_addr=%p, p_phys_addr=%p\n",
+		__func__,
+		p->num_bytes,
+		(void *)(p->memory_handle_virt),
+		(void *)(p->memory_handle_phys));
+
+	dma_free_coherent(NULL,
+		p->num_bytes,
+		(void *)(p->memory_handle_virt),
+		(dma_addr_t)(p->memory_handle_phys));
+
+	p->memory_handle_phys = (u64)0;
+	p->memory_handle_virt = (u64)0;
+
+	LOG_EXT();
+	return 0;
+}
+
+int esc_mods_dma_copy_to_user(struct file                    *fp,
+				struct MODS_DMA_COPY_TO_USER *p)
+{
+	int retval;
+
+	LOG_ENT();
+
+	mods_debug_printk(DEBUG_MEM,
+		"%s:memory_handle_dst=%p, memory_handle_src=%p, num_bytes=%d\n",
+		__func__,
+		(void *)(p->memory_handle_dst),
+		(void *)(p->memory_handle_src),
+		p->num_bytes);
+
+	retval = copy_to_user((void *)(p->memory_handle_dst),
+				(void *)(p->memory_handle_src),
+				p->num_bytes);
+
+	LOG_EXT();
+
+	return retval;
+}
diff --git a/drivers/misc/mods/mods_dmabuf.c b/drivers/misc/mods/mods_dmabuf.c
new file mode 100644
index 00000000..99736231
--- /dev/null
+++ b/drivers/misc/mods/mods_dmabuf.c
@@ -0,0 +1,142 @@
+/*
+ * mods_dmabuf.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include "mods_config.h"
+
+#ifdef MODS_HAS_DMABUF
+
+#include <linux/dma-buf.h>
+#include <linux/platform_device.h>
+
+#include <linux/tegra_smmu.h>
+
+#include "mods_internal.h"
+
+static struct device_dma_parameters dma_parms = {
+	.max_segment_size = UINT_MAX,
+};
+
+static struct platform_device dummy_device = {
+	.name = "nvidia_mods_dummy_device",
+	.id = -1,
+	.dev = {
+		.dma_parms = &dma_parms,
+	},
+};
+
+static bool dummy_device_registered;
+
+int esc_mods_dmabuf_get_phys_addr(struct file *filp,
+				  struct MODS_DMABUF_GET_PHYSICAL_ADDRESS *op)
+{
+	int err = 0;
+	struct dma_buf *dmabuf = NULL;
+	struct dma_buf_attachment *attachment = NULL;
+	struct sg_table *sgt = NULL;
+	unsigned int remaining_offset = op->offset;
+	phys_addr_t physical_address = 0;
+	unsigned int segment_size = 0;
+	struct scatterlist *sg;
+	unsigned int sg_index;
+
+	if (op->offset > UINT_MAX)
+		return -EINVAL;
+
+	dmabuf = dma_buf_get(op->buf_fd);
+	if (IS_ERR_OR_NULL(dmabuf))
+		return IS_ERR(dmabuf) ? PTR_ERR(dmabuf) : -EINVAL;
+
+	attachment = dma_buf_attach(dmabuf, &dummy_device.dev);
+	if (IS_ERR_OR_NULL(attachment)) {
+		mods_error_printk("%s: failed to attach dma buf\n", __func__);
+		err = IS_ERR(attachment) ? PTR_ERR(attachment) : -EFAULT;
+		goto buf_attach_fail;
+	}
+
+	sgt = dma_buf_map_attachment(attachment, DMA_BIDIRECTIONAL);
+	if (IS_ERR_OR_NULL(sgt)) {
+		mods_error_printk("%s: failed to map dma buf\n", __func__);
+		err = IS_ERR(sgt) ? PTR_ERR(sgt) : -EFAULT;
+		goto buf_map_fail;
+	}
+
+	for_each_sg(sgt->sgl, sg, sgt->nents, sg_index) {
+		if (remaining_offset >= sg->length) {
+			/* haven't reached segment yet, or empty sg */
+			remaining_offset -= sg->length;
+		} else if (segment_size == 0) {
+			/* first sg in segment */
+			physical_address = sg_phys(sg) + remaining_offset;
+			segment_size = sg->length - remaining_offset;
+			remaining_offset = 0;
+		} else if (sg_phys(sg) == physical_address + segment_size) {
+			/* contiguous sg; append to segment */
+			segment_size += sg->length;
+		} else {
+			/* discontiguous sg; end segment */
+			break;
+		}
+	}
+
+	if (segment_size == 0) {
+		err = -EINVAL;
+	} else {
+		op->physical_address = physical_address;
+		op->segment_size = segment_size;
+	}
+
+	dma_buf_unmap_attachment(attachment, sgt, DMA_BIDIRECTIONAL);
+
+buf_map_fail:
+	dma_buf_detach(dmabuf, attachment);
+
+buf_attach_fail:
+	dma_buf_put(dmabuf);
+
+	return err;
+}
+
+int mods_init_dmabuf(void)
+{
+	int ret;
+
+	ret = platform_device_register(&dummy_device);
+	if (ret) {
+		mods_error_printk("failed to register %s\n", dummy_device.name);
+		return ret;
+	}
+
+	tegra_smmu_map_misc_device(&dummy_device.dev);
+
+	dummy_device_registered = true;
+
+	return 0;
+}
+
+void mods_exit_dmabuf(void)
+{
+	if (dummy_device_registered) {
+		tegra_smmu_unmap_misc_device(&dummy_device.dev);
+		platform_device_unregister(&dummy_device);
+		dummy_device_registered = false;
+	}
+}
+
+#endif
diff --git a/drivers/misc/mods/mods_internal.h b/drivers/misc/mods/mods_internal.h
new file mode 100644
index 00000000..3f8180cc
--- /dev/null
+++ b/drivers/misc/mods/mods_internal.h
@@ -0,0 +1,589 @@
+/*
+ * mods_internal.h - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2008-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _MODS_INTERNAL_H_
+#define _MODS_INTERNAL_H_
+
+#include <linux/version.h>
+#include <linux/list.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/miscdevice.h>
+#include <linux/mutex.h>
+
+#include "mods_config.h"
+#include "mods.h"
+
+#ifndef true
+#define true	1
+#define false	0
+#endif
+
+/* function return code */
+#define OK		 0
+
+#define IRQ_FOUND	 1
+#define IRQ_NOT_FOUND	 0
+
+#define DEV_FOUND	 1
+#define DEV_NOT_FOUND	 0
+
+#define MSI_DEV_FOUND	  1
+#define MSI_DEV_NOT_FOUND 0
+
+struct en_dev_entry {
+	struct pci_dev	    *dev;
+	struct en_dev_entry *next;
+};
+
+struct mem_type {
+	u64 dma_addr;
+	u64 size;
+	u32 type;
+};
+
+/* file private data */
+struct mods_file_private_data {
+	struct list_head    *mods_alloc_list;
+	struct list_head    *mods_mapping_list;
+	struct list_head    *mods_pci_res_map_list;
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+	struct list_head    *mods_ppc_tce_bypass_list;
+#endif
+	wait_queue_head_t    interrupt_event;
+	struct en_dev_entry *enabled_devices;
+	int                  mods_id;
+	struct mem_type      mem_type;
+	struct mutex         mtx;
+};
+
+typedef struct mods_file_private_data *MODS_PRIV;
+
+/* VM private data */
+struct mods_vm_private_data {
+	struct file *fp;
+	atomic_t     usage_count;
+};
+
+/* PCI Resource mapping private data*/
+struct MODS_PCI_RES_MAP_INFO {
+	struct pci_dev  *dev;          /* pci_dev the mapping was on */
+	u64              page_count;   /* number of pages for the mapping */
+	u64              va;           /* va address of the mapping */
+	struct list_head list;
+};
+
+struct MODS_PHYS_CHUNK {
+	u64          dma_addr:58; /* phys addr (or machine addr on XEN) */
+	u32          order:5;     /* 1<<order = number of contig pages */
+	int          allocated:1;
+	struct page *p_page;
+};
+
+struct MODS_MAP_CHUNK {
+	struct MODS_PHYS_CHUNK *pt;
+	u64 map_addr;
+};
+
+struct MODS_DMA_MAP {
+	struct pci_dev  *dev;          /* pci_dev to map the page to */
+	struct list_head list;
+	struct MODS_MAP_CHUNK mapping[1];
+};
+
+/* system memory allocation tracking */
+struct MODS_MEM_INFO {
+	u64		 logical_addr;   /* kernel logical address */
+	u32		 num_pages;      /* number of allocated pages */
+	u8		 alloc_type : 2; /* MODS_ALLOC_TYPE_* */
+	u8		 cache_type : 3; /* MODS_MEMORY_* */
+	u8		 addr_bits  : 7; /* phys addr size requested */
+	u32		 length;         /* actual number of bytes allocated */
+	u32		 max_chunks;     /* max number of contig chunks */
+	int		 numa_node;      /* numa node for the allocation */
+	struct pci_dev  *dev;  /* backwards compatibility : pci_dev that the
+				* memory was allocated on
+				*/
+
+	struct list_head *dma_map_list;
+
+	struct list_head list;
+
+	/* information about allocated pages */
+	struct MODS_PHYS_CHUNK pages[1];
+};
+
+#define MODS_ALLOC_TYPE_NON_CONTIG	0
+#define MODS_ALLOC_TYPE_CONTIG		1
+#define MODS_ALLOC_TYPE_BIGPHYS_AREA	2
+
+/* map memory tracking */
+struct SYS_MAP_MEMORY {
+	/* used for offset lookup, NULL for device memory */
+	struct MODS_MEM_INFO *p_mem_info;
+
+	u64 dma_addr;	    /* first physical address of given mapping,
+			     * machine address on Xen
+			     */
+	u64 virtual_addr;   /* virtual address of given mapping */
+	u32 mapping_length; /* tells how many bytes were mapped */
+
+	struct list_head   list;
+};
+
+/* functions used to avoid global debug variables */
+void mods_set_debug_level(int mask);
+int mods_get_debug_level(void);
+int mods_check_debug_level(int mask);
+int mods_get_multi_instance(void);
+void mods_set_multi_instance(int mi);
+
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+void mods_set_ppc_tce_bypass(int bypass);
+int mods_get_ppc_tce_bypass(void);
+
+/* PPC TCE bypass tracking */
+struct PPC_TCE_BYPASS {
+	struct pci_dev *dev;
+	u64 dma_mask;
+	struct list_head   list;
+};
+#endif
+
+#define IRQ_MAX			(256+PCI_IRQ_MAX)
+#define PCI_IRQ_MAX		15
+#define MODS_CHANNEL_MAX	32
+
+#define IRQ_VAL_POISON		0xfafbfcfdU
+
+/* debug print masks */
+#define DEBUG_IOCTL		0x2
+#define DEBUG_PCICFG		0x4
+#define DEBUG_ACPI		0x8
+#define DEBUG_ISR		0x10
+#define DEBUG_MEM		0x20
+#define DEBUG_FUNC		0x40
+#define DEBUG_CLOCK		0x80
+#define DEBUG_DETAILED		0x100
+#define DEBUG_TEGRADC		0x200
+#define DEBUG_TEGRADMA		0x400
+#define DEBUG_ISR_DETAILED	(DEBUG_ISR | DEBUG_DETAILED)
+#define DEBUG_MEM_DETAILED	(DEBUG_MEM | DEBUG_DETAILED)
+#define DEBUG_ALL	        (DEBUG_IOCTL | DEBUG_PCICFG | DEBUG_ACPI | \
+	DEBUG_ISR | DEBUG_MEM | DEBUG_FUNC | DEBUG_CLOCK | DEBUG_DETAILED | \
+	DEBUG_TEGRADC | DEBUG_TEGRADMA)
+
+#define LOG_ENT() mods_debug_printk(DEBUG_FUNC, "> %s\n", __func__)
+#define LOG_EXT() mods_debug_printk(DEBUG_FUNC, "< %s\n", __func__)
+
+#define mods_debug_printk(level, fmt, args...)\
+	({ \
+		if (mods_check_debug_level(level)) \
+			pr_info("mods debug: " fmt, ##args); \
+	})
+
+#define mods_info_printk(fmt, args...)\
+	pr_info("mods: " fmt, ##args)
+
+#define mods_error_printk(fmt, args...)\
+	pr_info("mods error: " fmt, ##args)
+
+#define mods_warning_printk(fmt, args...)\
+	pr_info("mods warning: " fmt, ##args)
+
+struct irq_q_data {
+	u32		time;
+	struct pci_dev *dev;
+	u32		irq;
+};
+
+struct irq_q_info {
+	struct irq_q_data data[MODS_MAX_IRQS];
+	u32		  head;
+	u32		  tail;
+};
+
+struct irq_mask_info {
+	u32	*dev_irq_mask_reg;  /*IRQ mask register, read-only reg*/
+	u32	*dev_irq_state;     /* IRQ status register*/
+	u32 *dev_irq_disable_reg; /* potentionally a write-only reg*/
+	u64	irq_and_mask;
+	u64	 irq_or_mask;
+	u8	 mask_type;
+};
+
+struct dev_irq_map {
+	void	*dev_irq_aperture;
+	u32	apic_irq;
+	u8	type;
+	u8	channel;
+	u8	mask_info_cnt;
+	struct	irq_mask_info mask_info[MODS_IRQ_MAX_MASKS];
+	struct	pci_dev      *dev;
+	struct	list_head     list;
+};
+
+struct mods_priv {
+	/* map info from pci irq to apic irq */
+	struct list_head  irq_head[MODS_CHANNEL_MAX];
+
+	/* bits map for each allocated id. Each mods has an id. */
+	/* the design is to take  into	account multi mods. */
+	unsigned long	  channel_flags;
+
+	/* fifo loop queue */
+	struct irq_q_info rec_info[MODS_CHANNEL_MAX];
+	spinlock_t	  lock;
+};
+
+#ifndef MODS_HAS_SET_MEMORY
+#	define MODS_SET_MEMORY_UC(addr, pages) \
+	       change_page_attr(virt_to_page(addr), pages, PAGE_KERNEL_NOCACHE)
+#	define MODS_SET_MEMORY_WC MODS_SET_MEMORY_UC
+#	define MODS_SET_MEMORY_WB(addr, pages) \
+	       change_page_attr(virt_to_page(addr), pages, PAGE_KERNEL)
+#elif ((defined(CONFIG_ARM) || defined(CONFIG_ARM64)) && \
+	  !defined(CONFIG_CPA)) || defined(CONFIG_PPC64)
+#	define MODS_SET_MEMORY_UC(addr, pages) 0
+#	define MODS_SET_MEMORY_WC(addr, pages) 0
+#	define MODS_SET_MEMORY_WB(addr, pages) 0
+#else
+#	define MODS_SET_MEMORY_UC(addr, pages) set_memory_uc(addr, pages)
+#	ifdef MODS_HAS_WC
+#		define MODS_SET_MEMORY_WC(addr, pages)\
+		       set_memory_wc(addr, pages)
+#	else
+#		define MODS_SET_MEMORY_WC(addr, pages)\
+		       MODS_SET_MEMORY_UC(addr, pages)
+#	endif
+#	define MODS_SET_MEMORY_WB(addr, pages) set_memory_wb(addr, pages)
+#endif
+
+#define MODS_PGPROT_UC pgprot_noncached
+#ifdef MODS_HAS_WC
+#	define MODS_PGPROT_WC pgprot_writecombine
+#else
+#	define MODS_PGPROT_WC pgprot_noncached
+#endif
+
+/* VMA */
+#define MODS_VMA_PGOFF(vma)	((vma)->vm_pgoff)
+#define MODS_VMA_SIZE(vma)	((vma)->vm_end - (vma)->vm_start)
+#define MODS_VMA_OFFSET(vma)	(((u64)(vma)->vm_pgoff) << PAGE_SHIFT)
+#define MODS_VMA_PRIVATE(vma)	((vma)->vm_private_data)
+#define MODS_VMA_FILE(vma)	((vma)->vm_file)
+
+/* Xen adds a translation layer between the physical address
+ * and real system memory address space.
+ *
+ * To illustrate if a PC has 2 GBs of RAM and each VM is given 1GB, then:
+ * for guest OS in domain 0, physical address = machine address;
+ * for guest OS in domain 1, physical address x = machine address 1GB+x
+ *
+ * In reality even domain's 0 physical address is not equal to machine
+ * address and the mappings are not continuous.
+ */
+
+#if defined(CONFIG_XEN) && !defined(CONFIG_PARAVIRT) && \
+	  !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
+	#define MODS_PHYS_TO_DMA(phys_addr) phys_to_machine(phys_addr)
+	#define MODS_DMA_TO_PHYS(dma_addr)  machine_to_phys(dma_addr)
+#else
+	#define MODS_PHYS_TO_DMA(phys_addr) (phys_addr)
+	#define MODS_DMA_TO_PHYS(dma_addr)  (dma_addr)
+#endif
+
+/* PCI */
+#define MODS_PCI_GET_SLOT(mydomain, mybus, devfn)			     \
+({									     \
+	struct pci_dev *__dev = NULL;					     \
+	while ((__dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, __dev))) {    \
+		if (pci_domain_nr(__dev->bus) == mydomain		     \
+		    && __dev->bus->number == mybus			     \
+		    && __dev->devfn == devfn)				     \
+			break;						     \
+	}								     \
+	__dev;								     \
+})
+
+/* ACPI */
+#ifdef MODS_HAS_NEW_ACPI_WALK
+#define MODS_ACPI_WALK_NAMESPACE(type, start_object, max_depth, user_function, \
+				 context, return_value)\
+	acpi_walk_namespace(type, start_object, max_depth, user_function, NULL,\
+			    context, return_value)
+#else
+#define MODS_ACPI_WALK_NAMESPACE acpi_walk_namespace
+#endif
+#ifdef MODS_HAS_NEW_ACPI_HANDLE
+#define MODS_ACPI_HANDLE(dev) ACPI_HANDLE(dev)
+#else
+#define MODS_ACPI_HANDLE(dev) DEVICE_ACPI_HANDLE(dev)
+#endif
+
+/* FILE */
+#define MODS_GET_FILE_PRIVATE_ID(fp) (((struct mods_file_private_data *)(fp) \
+				      ->private_data)->mods_id)
+
+/* ************************************************************************* */
+/* ** MODULE WIDE FUNCTIONS						     */
+/* ************************************************************************* */
+
+/* irq */
+void mods_init_irq(void);
+void mods_cleanup_irq(void);
+unsigned char mods_alloc_channel(void);
+void mods_free_channel(unsigned char channel);
+void mods_irq_dev_clr_pri(unsigned char id);
+void mods_irq_dev_set_pri(unsigned char id, void *pri);
+int mods_irq_event_check(unsigned char channel);
+
+/* mem */
+const char *mods_get_prot_str(u32 mem_type);
+int mods_unregister_all_alloc(struct file *fp);
+struct MODS_MEM_INFO *mods_find_alloc(struct file *fp, u64 phys_addr);
+
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+int mods_unregister_all_ppc_tce_bypass(struct file *fp);
+#endif
+
+#ifdef CONFIG_PCI
+int mods_unregister_all_pci_res_mappings(struct file *fp);
+#define MODS_UNREGISTER_PCI_MAP(fp) mods_unregister_all_pci_res_mappings(fp)
+#else
+#define MODS_UNREGISTER_PCI_MAP(fp) 0
+#endif
+
+/* clock */
+#ifdef MODS_TEGRA
+void mods_init_clock_api(void);
+void mods_shutdown_clock_api(void);
+#endif
+
+/* ioctl hanndlers */
+
+/* mem */
+int esc_mods_alloc_pages(struct file *fp, struct MODS_ALLOC_PAGES *p);
+int esc_mods_device_alloc_pages(struct file *fp,
+				struct MODS_DEVICE_ALLOC_PAGES *p);
+int esc_mods_device_alloc_pages_2(struct file *fp,
+				  struct MODS_DEVICE_ALLOC_PAGES_2 *p);
+int esc_mods_free_pages(struct file *fp, struct MODS_FREE_PAGES *p);
+int esc_mods_set_mem_type(struct file *fp, struct MODS_MEMORY_TYPE *p);
+int esc_mods_get_phys_addr(struct file *fp,
+			   struct MODS_GET_PHYSICAL_ADDRESS *p);
+int esc_mods_get_mapped_phys_addr(struct file *fp,
+			  struct MODS_GET_PHYSICAL_ADDRESS *p);
+int esc_mods_get_mapped_phys_addr_2(struct file *fp,
+				    struct MODS_GET_PHYSICAL_ADDRESS_2 *p);
+int esc_mods_virtual_to_phys(struct file *fp,
+			     struct MODS_VIRTUAL_TO_PHYSICAL *p);
+int esc_mods_phys_to_virtual(struct file *fp,
+			     struct MODS_PHYSICAL_TO_VIRTUAL *p);
+int esc_mods_memory_barrier(struct file *fp);
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+int esc_mods_set_ppc_tce_bypass(struct file *fp,
+				struct MODS_SET_PPC_TCE_BYPASS *p);
+int esc_mods_get_ats_address_range(struct file *fp,
+				   struct MODS_GET_ATS_ADDRESS_RANGE *p);
+#endif
+
+int esc_mods_dma_map_memory(struct file *fp,
+			    struct MODS_DMA_MAP_MEMORY *p);
+int esc_mods_dma_unmap_memory(struct file *fp,
+			      struct MODS_DMA_MAP_MEMORY *p);
+
+/* acpi */
+#ifdef CONFIG_ACPI
+int esc_mods_eval_acpi_method(struct file *fp,
+			      struct MODS_EVAL_ACPI_METHOD *p);
+int esc_mods_eval_dev_acpi_method(struct file *fp,
+				  struct MODS_EVAL_DEV_ACPI_METHOD *p);
+int esc_mods_eval_dev_acpi_method_2(struct file *fp,
+				    struct MODS_EVAL_DEV_ACPI_METHOD_2 *p);
+int esc_mods_acpi_get_ddc(struct file *fp, struct MODS_ACPI_GET_DDC *p);
+int esc_mods_acpi_get_ddc_2(struct file *fp, struct MODS_ACPI_GET_DDC_2 *p);
+#endif
+/* pci */
+#ifdef CONFIG_PCI
+int esc_mods_find_pci_dev(struct file *fp, struct MODS_FIND_PCI_DEVICE *p);
+int esc_mods_find_pci_dev_2(struct file *fp,
+			    struct MODS_FIND_PCI_DEVICE_2 *p);
+int esc_mods_find_pci_class_code(struct file *fp,
+				 struct MODS_FIND_PCI_CLASS_CODE *p);
+int esc_mods_find_pci_class_code_2(struct file *fp,
+				   struct MODS_FIND_PCI_CLASS_CODE_2 *p);
+int esc_mods_pci_get_bar_info(struct file *fp, struct MODS_PCI_GET_BAR_INFO *p);
+int esc_mods_pci_get_bar_info_2(struct file *fp,
+				struct MODS_PCI_GET_BAR_INFO_2 *p);
+int esc_mods_pci_get_irq(struct file *fp, struct MODS_PCI_GET_IRQ *p);
+int esc_mods_pci_get_irq_2(struct file *fp,
+			   struct MODS_PCI_GET_IRQ_2 *p);
+int esc_mods_pci_read(struct file *fp, struct MODS_PCI_READ *p);
+int esc_mods_pci_read_2(struct file *fp, struct MODS_PCI_READ_2 *p);
+int esc_mods_pci_write(struct file *fp, struct MODS_PCI_WRITE *p);
+int esc_mods_pci_write_2(struct file *fp, struct MODS_PCI_WRITE_2 *p);
+int esc_mods_pci_bus_add_dev(struct file *fp,
+			     struct MODS_PCI_BUS_ADD_DEVICES *p);
+int esc_mods_pci_hot_reset(struct file *fp,
+			   struct MODS_PCI_HOT_RESET *p);
+int esc_mods_pio_read(struct file *fp, struct MODS_PIO_READ *p);
+int esc_mods_pio_write(struct file *fp, struct MODS_PIO_WRITE *p);
+int esc_mods_device_numa_info(struct file *fp,
+			      struct MODS_DEVICE_NUMA_INFO *p);
+int esc_mods_device_numa_info_2(struct file *fp,
+				struct MODS_DEVICE_NUMA_INFO_2 *p);
+int esc_mods_pci_map_resource(struct file *fp,
+			      struct MODS_PCI_MAP_RESOURCE *p);
+int esc_mods_pci_unmap_resource(struct file *fp,
+				struct MODS_PCI_UNMAP_RESOURCE *p);
+#endif
+/* irq */
+#if defined(MODS_TEGRA) && defined(CONFIG_OF_IRQ) && defined(CONFIG_OF)
+int esc_mods_map_irq(struct file *fp, struct MODS_DT_INFO *p);
+#endif
+int esc_mods_register_irq(struct file *fp, struct MODS_REGISTER_IRQ *p);
+int esc_mods_register_irq_2(struct file *fp,
+			    struct MODS_REGISTER_IRQ_2 *p);
+int esc_mods_register_irq_3(struct file *fp,
+			    struct MODS_REGISTER_IRQ_3 *p);
+int esc_mods_unregister_irq(struct file *fp, struct MODS_REGISTER_IRQ *p);
+int esc_mods_unregister_irq_2(struct file *fp,
+			      struct MODS_REGISTER_IRQ_2 *p);
+int esc_mods_query_irq(struct file *fp, struct MODS_QUERY_IRQ *p);
+int esc_mods_query_irq_2(struct file *fp, struct MODS_QUERY_IRQ_2 *p);
+int esc_mods_set_irq_mask(struct file *fp, struct MODS_SET_IRQ_MASK *p);
+int esc_mods_set_irq_mask_2(struct file *fp,
+			    struct MODS_SET_IRQ_MASK_2 *p);
+int esc_mods_set_irq_multimask(struct file *fp,
+			       struct MODS_SET_IRQ_MULTIMASK *p);
+int esc_mods_irq_handled(struct file *fp, struct MODS_REGISTER_IRQ *p);
+int esc_mods_irq_handled_2(struct file *fp,
+			   struct MODS_REGISTER_IRQ_2 *p);
+#ifdef MODS_TEGRA
+
+/* clock */
+int esc_mods_get_clock_handle(struct file *fp,
+			      struct MODS_GET_CLOCK_HANDLE *p);
+int esc_mods_set_clock_rate(struct file *fp, struct MODS_CLOCK_RATE *p);
+int esc_mods_get_clock_rate(struct file *fp, struct MODS_CLOCK_RATE *p);
+int esc_mods_get_clock_max_rate(struct file *fp, struct MODS_CLOCK_RATE *p);
+int esc_mods_set_clock_max_rate(struct file *fp, struct MODS_CLOCK_RATE *p);
+int esc_mods_set_clock_parent(struct file *fp, struct MODS_CLOCK_PARENT *p);
+int esc_mods_get_clock_parent(struct file *fp, struct MODS_CLOCK_PARENT *p);
+int esc_mods_enable_clock(struct file *fp, struct MODS_CLOCK_HANDLE *p);
+int esc_mods_disable_clock(struct file *fp, struct MODS_CLOCK_HANDLE *p);
+int esc_mods_is_clock_enabled(struct file *fp,
+			      struct MODS_CLOCK_ENABLED *p);
+int esc_mods_clock_reset_assert(struct file *fp,
+				struct MODS_CLOCK_HANDLE *p);
+int esc_mods_clock_reset_deassert(struct file *fp,
+				  struct MODS_CLOCK_HANDLE *p);
+int esc_mods_flush_cpu_cache_range(struct file *fp,
+				   struct MODS_FLUSH_CPU_CACHE_RANGE *p);
+int esc_mods_dma_alloc_coherent(struct file *fp,
+				struct MODS_DMA_COHERENT_MEM_HANDLE *p);
+int esc_mods_dma_free_coherent(struct file *fp,
+				struct MODS_DMA_COHERENT_MEM_HANDLE *p);
+int esc_mods_dma_copy_to_user(struct file *fp,
+				struct MODS_DMA_COPY_TO_USER *p);
+
+#ifdef CONFIG_DMA_ENGINE
+int esc_mods_dma_request_channel(struct file *fp, struct MODS_DMA_HANDLE *p);
+int esc_mods_dma_release_channel(struct file *fp, struct MODS_DMA_HANDLE *p);
+int esc_mods_dma_set_config(struct file *fp, struct MODS_DMA_CHANNEL_CONFIG *p);
+int esc_mods_dma_wait(struct file *fp, struct MODS_DMA_WAIT_DESC *p);
+int esc_mods_dma_submit_request(struct file *fp,
+				struct MODS_DMA_TX_DESC *p);
+int esc_mods_dma_async_issue_pending(struct file *fp,
+				struct MODS_DMA_HANDLE *p);
+#endif
+
+#ifdef CONFIG_TEGRA_DC
+int esc_mods_tegra_dc_config_possible(struct file *fp,
+				struct MODS_TEGRA_DC_CONFIG_POSSIBLE *p);
+int esc_mods_tegra_dc_setup_sd(struct file *fp,
+			       struct MODS_TEGRA_DC_SETUP_SD *p);
+#endif
+
+#ifdef MODS_HAS_NET
+int esc_mods_net_force_link(struct file *fp, struct MODS_NET_DEVICE_NAME *p);
+#endif
+
+#ifdef MODS_HAS_DMABUF
+int esc_mods_dmabuf_get_phys_addr(struct file *fp,
+				  struct MODS_DMABUF_GET_PHYSICAL_ADDRESS *p);
+#else
+static inline int esc_mods_dmabuf_get_phys_addr(struct file *fp,
+				  struct MODS_DMABUF_GET_PHYSICAL_ADDRESS *p)
+				  { return -EINVAL; }
+#endif
+
+#ifdef CONFIG_TEGRA_NVADSP
+int esc_mods_adsp_load(struct file *fp);
+int esc_mods_adsp_start(struct file *fp);
+int esc_mods_adsp_stop(struct file *fp);
+int esc_mods_adsp_run_app(struct file *fp, struct MODS_ADSP_RUN_APP_INFO *p);
+#endif
+
+/* prod */
+int mods_tegra_prod_init(const struct miscdevice *misc_dev);
+int esc_mods_tegra_prod_iterate_dt(struct file *fp,
+	struct MODS_TEGRA_PROD_ITERATOR *iterator);
+int esc_mods_tegra_prod_is_supported(struct file *fp,
+	struct MODS_TEGRA_PROD_IS_SUPPORTED *tuple);
+int esc_mods_tegra_prod_set_prod_all(struct file *fp,
+	struct MODS_TEGRA_PROD_SET_TUPLE *tuple);
+int esc_mods_tegra_prod_set_prod_boot(struct file *fp,
+	struct MODS_TEGRA_PROD_SET_TUPLE *tuple);
+int esc_mods_tegra_prod_set_prod_by_name(struct file *fp,
+	struct MODS_TEGRA_PROD_SET_TUPLE *tuple);
+int esc_mods_tegra_prod_set_prod_exact(struct file *fp,
+	struct MODS_TEGRA_PROD_SET_TUPLE *tuple);
+
+#endif
+
+#ifdef CONFIG_DEBUG_FS
+int mods_create_debugfs(struct miscdevice *modsdev);
+void mods_remove_debugfs(void);
+#else
+static inline int mods_create_debugfs(struct miscdevice *modsdev)
+{
+	return 0;
+}
+static inline void mods_remove_debugfs(void) {}
+#endif /* CONFIG_DEBUG_FS */
+
+#ifdef CONFIG_TEGRA_DC
+int mods_init_tegradc(void);
+void mods_exit_tegradc(void);
+#else
+static inline int mods_init_tegradc(void) { return 0; }
+static inline void mods_exit_tegradc(void) {}
+#endif
+
+#if defined(MODS_TEGRA) && defined(MODS_HAS_DMABUF)
+int mods_init_dmabuf(void);
+void mods_exit_dmabuf(void);
+#else
+static inline int mods_init_dmabuf(void) { return 0; }
+static inline void mods_exit_dmabuf(void) {}
+#endif
+
+#endif	/* _MODS_INTERNAL_H_  */
diff --git a/drivers/misc/mods/mods_irq.c b/drivers/misc/mods/mods_irq.c
new file mode 100644
index 00000000..2871594f
--- /dev/null
+++ b/drivers/misc/mods/mods_irq.c
@@ -0,0 +1,1385 @@
+/*
+ * mods_irq.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2008-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mods_internal.h"
+
+#include <linux/sched.h>
+#include <linux/poll.h>
+#include <linux/interrupt.h>
+#include <linux/pci_regs.h>
+#if defined(MODS_TEGRA) && defined(CONFIG_OF_IRQ) && defined(CONFIG_OF)
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#endif
+
+#define PCI_VENDOR_ID_NVIDIA 0x10de
+#define INDEX_IRQSTAT(irq)	(irq / BITS_NUM)
+#define POS_IRQSTAT(irq)	 (irq & (BITS_NUM - 1))
+
+/* MSI */
+#define PCI_MSI_MASK_BIT	16
+#define MSI_CONTROL_REG(base)		(base + PCI_MSI_FLAGS)
+#define IS_64BIT_ADDRESS(control)	(!!(control & PCI_MSI_FLAGS_64BIT))
+#define MSI_DATA_REG(base, is64bit) \
+	((is64bit == 1) ? base + PCI_MSI_DATA_64 : base + PCI_MSI_DATA_32)
+#define TOP_TKE_TKEIE_WDT_MASK(i)	(1 << (16 + 4 * (i)))
+#define TOP_TKE_TKEIE(i)		(0x100 + 4 * (i))
+
+struct nv_device {
+	char		  name[20];
+	struct mods_priv *isr_pri;
+	void		 *pri[MODS_CHANNEL_MAX];
+};
+
+/*********************
+ * PRIVATE FUNCTIONS *
+ *********************/
+static struct mods_priv mp;
+static struct nv_device nv_dev = { "nvidia mods", &mp, {0} };
+
+static struct mods_priv *get_all_data(void)
+{
+	return &mp;
+}
+
+static struct nv_device *get_dev(void)
+{
+	return &nv_dev;
+}
+
+#ifdef CONFIG_PCI
+static int mods_enable_device(struct mods_file_private_data *priv,
+				  struct pci_dev *pdev)
+{
+	int                  ret   = -1;
+	struct en_dev_entry *entry = priv->enabled_devices;
+
+	while (entry != 0) {
+		if (entry->dev == pdev)
+			return 0;
+		entry = entry->next;
+	}
+
+	ret = pci_enable_device(pdev);
+	if (ret == 0) {
+		entry = kmalloc(sizeof(*entry), GFP_KERNEL | __GFP_NORETRY);
+		if (unlikely(!entry))
+			return 0;
+		entry->dev = pdev;
+		entry->next = priv->enabled_devices;
+		priv->enabled_devices = entry;
+	}
+	return ret;
+}
+#endif
+
+static unsigned int get_cur_time(void)
+{
+	/* This is not very precise, sched_clock() would be better */
+	return jiffies_to_usecs(jiffies);
+}
+
+static int id_is_valid(unsigned char channel)
+{
+	if (channel <= 0 || channel > MODS_CHANNEL_MAX)
+		return -EINVAL;
+
+	return OK;
+}
+
+static inline int mods_check_interrupt(struct dev_irq_map *t)
+{
+	int ii = 0;
+	int valid = 0;
+
+	/* For MSI - we always treat it as pending (must rearm later). */
+	/* For non-GPU devices - we can't tell. */
+	if (t->mask_info_cnt == 0)
+		return true;
+
+	for (ii = 0; ii < t->mask_info_cnt; ii++) {
+		if (!t->mask_info[ii].dev_irq_state ||
+		    !t->mask_info[ii].dev_irq_mask_reg)
+			continue;
+
+		/* GPU device */
+		if (t->mask_info[ii].mask_type == MODS_MASK_TYPE_IRQ_DISABLE64)
+			valid |= ((*(u64 *)t->mask_info[ii].dev_irq_state &&
+			*(u64 *)t->mask_info[ii].dev_irq_mask_reg) != 0);
+		else
+			valid |= ((*t->mask_info[ii].dev_irq_state &&
+			     *t->mask_info[ii].dev_irq_mask_reg) != 0);
+	}
+	return valid;
+}
+
+static void mods_disable_interrupts(struct dev_irq_map *t)
+{
+	u32 ii = 0;
+
+	for (ii = 0; ii < t->mask_info_cnt; ii++) {
+		if (t->mask_info[ii].dev_irq_disable_reg &&
+		   t->mask_info[ii].mask_type == MODS_MASK_TYPE_IRQ_DISABLE64) {
+			if (t->mask_info[ii].irq_and_mask == 0)
+				*(u64 *)t->mask_info[ii].dev_irq_disable_reg =
+				t->mask_info[ii].irq_or_mask;
+			else
+				*(u64 *)t->mask_info[ii].dev_irq_disable_reg =
+				(*(u64 *)t->mask_info[ii].dev_irq_mask_reg &
+				t->mask_info[ii].irq_and_mask) |
+				t->mask_info[ii].irq_or_mask;
+		} else if (t->mask_info[ii].dev_irq_disable_reg) {
+			if (t->mask_info[ii].irq_and_mask == 0) {
+				*t->mask_info[ii].dev_irq_disable_reg =
+				t->mask_info[ii].irq_or_mask;
+			} else {
+				*t->mask_info[ii].dev_irq_disable_reg =
+				(*t->mask_info[ii].dev_irq_mask_reg &
+				t->mask_info[ii].irq_and_mask) |
+				t->mask_info[ii].irq_or_mask;
+			}
+		}
+	}
+	if ((ii == 0) && t->type == MODS_IRQ_TYPE_CPU) {
+		mods_debug_printk(DEBUG_ISR, "IRQ_DISABLE_NOSYNC ");
+		disable_irq_nosync(t->apic_irq);
+	}
+}
+
+static void rec_irq_done(struct nv_device *dev,
+			 unsigned char channel,
+			 struct dev_irq_map *t,
+			 unsigned int irq_time)
+{
+	struct irq_q_info *q;
+	struct mods_priv *pmp = dev->isr_pri;
+	struct mods_file_private_data *private_data = dev->pri[channel - 1];
+
+	/* Get interrupt queue */
+	q = &pmp->rec_info[channel - 1];
+
+	/* Don't do anything if the IRQ has already been recorded */
+	if (q->head != q->tail) {
+		unsigned int i;
+
+		for (i = q->head; i != q->tail; i++) {
+			if (t->dev) {
+				struct pci_dev *cur
+					= q->data[i & (MODS_MAX_IRQS - 1)].dev;
+				if (cur == t->dev)
+					return;
+			} else {
+				u32 cur
+					= q->data[i & (MODS_MAX_IRQS - 1)].irq;
+				if (cur == t->apic_irq)
+					return;
+			}
+		}
+	}
+
+	/* Print an error if the queue is full */
+	/* This is deadly! */
+	if (q->tail - q->head == MODS_MAX_IRQS) {
+		mods_error_printk("IRQ queue is full\n");
+		return;
+	}
+
+	/* Record the device which generated the IRQ in the queue */
+	q->data[q->tail & (MODS_MAX_IRQS - 1)].dev = t->dev;
+	q->data[q->tail & (MODS_MAX_IRQS - 1)].irq = t->apic_irq;
+	q->data[q->tail & (MODS_MAX_IRQS - 1)].time = irq_time;
+	q->tail++;
+
+#ifdef CONFIG_PCI
+	if (t->dev) {
+		mods_debug_printk(DEBUG_ISR_DETAILED,
+			"%04x:%x:%02x.%x %s IRQ 0x%x time=%uus\n",
+				  (unsigned int)(pci_domain_nr(t->dev->bus)),
+				  (unsigned int)(t->dev->bus->number),
+				  (unsigned int)PCI_SLOT(t->dev->devfn),
+				  (unsigned int)PCI_FUNC(t->dev->devfn),
+			(t->type == MODS_IRQ_TYPE_MSI) ? "MSI" : "INTx",
+			t->apic_irq,
+			irq_time);
+	} else
+#endif
+		mods_debug_printk(DEBUG_ISR_DETAILED,
+			"CPU IRQ 0x%x, time=%uus\n",
+			t->apic_irq,
+			irq_time);
+
+	/* Wake MODS to handle the interrupt */
+	if (private_data) {
+		spin_unlock(&pmp->lock);
+		wake_up_interruptible(&private_data->interrupt_event);
+		spin_lock(&pmp->lock);
+	}
+}
+
+/* mods_irq_handle - interrupt function */
+static irqreturn_t mods_irq_handle(int irq, void *data
+#ifndef MODS_IRQ_HANDLE_NO_REGS
+			, struct pt_regs *regs
+#endif
+)
+{
+	struct nv_device *dev = (struct nv_device *)data;
+	struct mods_priv *pmp = dev->isr_pri;
+	struct dev_irq_map *t = NULL;
+	unsigned char channel_idx;
+	unsigned long flags = 0;
+	int found = 0;
+	unsigned int irq_time = get_cur_time();
+
+	spin_lock_irqsave(&pmp->lock, flags);
+
+	for (channel_idx = 0; channel_idx < MODS_CHANNEL_MAX; channel_idx++) {
+		if (!(pmp->channel_flags & (1 << channel_idx)))
+			continue;
+
+		list_for_each_entry(t, &pmp->irq_head[channel_idx], list) {
+			if ((t->apic_irq == irq) && mods_check_interrupt(t)) {
+				/* Disable interrupts on this device to avoid
+				 * interrupt storm
+				 */
+				mods_disable_interrupts(t);
+
+				/* Record IRQ for MODS and wake MODS up */
+				rec_irq_done(dev, channel_idx+1, t, irq_time);
+				found |= 1;
+
+				/* MSI and CPU interrupts are not shared,
+				 * so stop looking
+				 */
+				if (t->type != MODS_IRQ_TYPE_INT) {
+					channel_idx = MODS_CHANNEL_MAX;
+					break;
+				}
+			}
+		}
+	}
+
+	spin_unlock_irqrestore(&pmp->lock, flags);
+	return IRQ_RETVAL(found);
+}
+
+static int mods_lookup_irq(unsigned char channel, struct pci_dev *pdev,
+						   unsigned int irq)
+{
+	unsigned char channel_idx;
+	struct mods_priv *pmp = get_all_data();
+	int ret = IRQ_NOT_FOUND;
+
+	LOG_ENT();
+
+	for (channel_idx = 0; channel_idx < MODS_CHANNEL_MAX; channel_idx++) {
+		struct dev_irq_map *t    = NULL;
+		struct dev_irq_map *next = NULL;
+
+		list_for_each_entry_safe(t,
+					 next,
+					 &pmp->irq_head[channel_idx],
+					 list) {
+			if ((pdev && (t->dev == pdev))
+				|| (!pdev && (t->apic_irq == irq))) {
+
+				if (channel == 0) {
+					ret = IRQ_FOUND;
+				} else {
+					ret = (channel == channel_idx + 1)
+						  ? IRQ_FOUND : IRQ_NOT_FOUND;
+				}
+
+				/* Break out of the outer loop */
+				channel_idx = MODS_CHANNEL_MAX;
+				break;
+			}
+		}
+	}
+
+	LOG_EXT();
+	return ret;
+}
+
+#ifdef CONFIG_PCI
+static int is_nvidia_device(struct pci_dev *pdev)
+{
+	unsigned short class_code, vendor_id, device_id;
+
+	pci_read_config_word(pdev, PCI_CLASS_DEVICE, &class_code);
+	pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor_id);
+	pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
+	if (((class_code == PCI_CLASS_DISPLAY_VGA) ||
+	    (class_code == PCI_CLASS_DISPLAY_3D)) && (vendor_id == 0x10DE)) {
+		return 1;
+	}
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_PCI
+static void setup_mask_info(struct dev_irq_map *newmap,
+			    struct MODS_REGISTER_IRQ_3 *p,
+			    struct pci_dev *pdev)
+{
+	/* account for legacy adapters */
+	char *bar = newmap->dev_irq_aperture;
+	u32 ii = 0;
+
+	if ((p->mask_info_cnt == 0) && is_nvidia_device(pdev)) {
+		newmap->mask_info_cnt = 1;
+		newmap->mask_info[0].dev_irq_mask_reg = (u32 *)(bar+0x140);
+		newmap->mask_info[0].dev_irq_disable_reg = (u32 *)(bar+0x140);
+		newmap->mask_info[0].dev_irq_state = (u32 *)(bar+0x100);
+		newmap->mask_info[0].irq_and_mask = 0;
+		newmap->mask_info[0].irq_or_mask = 0;
+		return;
+	}
+	/* setup for new adapters */
+	newmap->mask_info_cnt = p->mask_info_cnt;
+	for (ii = 0; ii < p->mask_info_cnt; ii++) {
+		newmap->mask_info[ii].dev_irq_state =
+		    (u32 *)(bar + p->mask_info[ii].irq_pending_offset);
+		newmap->mask_info[ii].dev_irq_mask_reg =
+		    (u32 *)(bar + p->mask_info[ii].irq_enabled_offset);
+		newmap->mask_info[ii].dev_irq_disable_reg =
+		    (u32 *)(bar + p->mask_info[ii].irq_disable_offset);
+		newmap->mask_info[ii].irq_and_mask = p->mask_info[ii].and_mask;
+		newmap->mask_info[ii].irq_or_mask = p->mask_info[ii].or_mask;
+		newmap->mask_info[ii].mask_type = p->mask_info[ii].mask_type;
+	}
+}
+#endif
+
+static int add_irq_map(unsigned char channel,
+			   struct pci_dev *pdev,
+			   u32 irq,
+			   struct MODS_REGISTER_IRQ_3 *p)
+{
+	struct dev_irq_map *newmap = NULL;
+	struct mods_priv *pmp = get_all_data();
+	struct nv_device *nvdev = get_dev();
+
+	LOG_ENT();
+
+	/* Allocate memory for the new entry */
+	newmap = kmalloc(sizeof(*newmap), GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!newmap)) {
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+	/* Fill out the new entry */
+	newmap->apic_irq = irq;
+	newmap->dev = pdev;
+	newmap->channel = channel;
+	newmap->dev_irq_aperture = 0;
+	newmap->mask_info_cnt = 0;
+	newmap->type = p->irq_type;
+
+	/* Enable IRQ for this device in the kernel */
+	if (request_irq(
+			irq,
+			&mods_irq_handle,
+			(p->irq_type == MODS_IRQ_TYPE_INT) ? IRQF_SHARED : 0,
+			nvdev->name,
+			nvdev)) {
+		mods_error_printk("unable to enable IRQ 0x%x\n", irq);
+		kfree(newmap);
+		LOG_EXT();
+		return -EPERM;
+	}
+
+	/* Add the new entry to the list of all registered interrupts */
+	list_add(&newmap->list, &pmp->irq_head[channel - 1]);
+
+#ifdef CONFIG_PCI
+	/* Map BAR0 to be able to disable interrupts */
+	if ((p->irq_type == MODS_IRQ_TYPE_INT) &&
+	    (p->aperture_addr != 0) &&
+	    (p->aperture_size != 0)) {
+		char *bar = ioremap_nocache(p->aperture_addr, p->aperture_size);
+
+		if (!bar) {
+			mods_debug_printk(DEBUG_ISR,
+				"failed to remap aperture: 0x%llx size=0x%x\n",
+				p->aperture_addr, p->aperture_size);
+			LOG_EXT();
+			return -EPERM;
+		}
+
+		newmap->dev_irq_aperture = bar;
+		setup_mask_info(newmap, p, pdev);
+	}
+#endif
+
+	/* Print out successful registration string */
+	if (p->irq_type == MODS_IRQ_TYPE_CPU)
+		mods_debug_printk(DEBUG_ISR, "registered CPU IRQ 0x%x\n", irq);
+#ifdef CONFIG_PCI
+	else if (p->irq_type == MODS_IRQ_TYPE_INT) {
+		mods_debug_printk(DEBUG_ISR,
+		"%04x:%x:%02x.%x registered INTx IRQ 0x%x\n",
+		(unsigned int)(pci_domain_nr(pdev->bus)),
+		(unsigned int)(pdev->bus->number),
+		(unsigned int)PCI_SLOT(pdev->devfn),
+		(unsigned int)PCI_FUNC(pdev->devfn),
+		  pdev->irq);
+	}
+#endif
+#ifdef CONFIG_PCI_MSI
+	else if (p->irq_type == MODS_IRQ_TYPE_MSI) {
+		u16 control;
+		u16 data;
+		int cap_pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
+
+		pci_read_config_word(pdev, MSI_CONTROL_REG(cap_pos), &control);
+		if (IS_64BIT_ADDRESS(control))
+			pci_read_config_word(pdev,
+						 MSI_DATA_REG(cap_pos, 1),
+						 &data);
+		else
+			pci_read_config_word(pdev,
+						 MSI_DATA_REG(cap_pos, 0),
+						 &data);
+		mods_debug_printk(DEBUG_ISR,
+			"%04x:%x:%02x.%x registered MSI IRQ 0x%x data:0x%02x\n",
+			(unsigned int)(pci_domain_nr(pdev->bus)),
+			(unsigned int)(pdev->bus->number),
+			(unsigned int)PCI_SLOT(pdev->devfn),
+			(unsigned int)PCI_FUNC(pdev->devfn),
+			pdev->irq,
+			(unsigned int)data);
+	}
+#endif
+
+	LOG_EXT();
+	return OK;
+}
+
+static void mods_free_map(struct dev_irq_map *del)
+{
+	LOG_ENT();
+
+	/* Disable interrupts on the device */
+	mods_disable_interrupts(del);
+
+	/* Unmap aperture used for masking irqs */
+	if (del->dev_irq_aperture)
+		iounmap(del->dev_irq_aperture);
+
+	/* Unhook interrupts in the kernel */
+	free_irq(del->apic_irq, get_dev());
+
+	/* Disable MSI */
+#ifdef CONFIG_PCI_MSI
+	if (del->type == MODS_IRQ_TYPE_MSI)
+		pci_disable_msi(del->dev);
+#endif
+
+	/* Free memory */
+	kfree(del);
+
+	LOG_EXT();
+}
+
+void mods_init_irq(void)
+{
+	int i;
+	struct mods_priv *pmp = get_all_data();
+
+	LOG_ENT();
+
+	memset(pmp, 0, sizeof(struct mods_priv));
+	for (i = 0; i < MODS_CHANNEL_MAX; i++)
+		INIT_LIST_HEAD(&pmp->irq_head[i]);
+
+	spin_lock_init(&pmp->lock);
+	LOG_EXT();
+}
+
+void mods_cleanup_irq(void)
+{
+	int i;
+	struct mods_priv *pmp = get_all_data();
+
+	LOG_ENT();
+	for (i = 0; i < MODS_CHANNEL_MAX; i++) {
+		if (pmp->channel_flags && (1 << i))
+			mods_free_channel(i + 1);
+	}
+	LOG_EXT();
+}
+
+void mods_irq_dev_set_pri(unsigned char id, void *pri)
+{
+	struct nv_device *dev = get_dev();
+
+	dev->pri[id - 1] = pri;
+}
+
+void mods_irq_dev_clr_pri(unsigned char id)
+{
+	struct nv_device *dev = get_dev();
+
+	dev->pri[id - 1] = 0;
+}
+
+int mods_irq_event_check(unsigned char channel)
+{
+	struct mods_priv *pmp = get_all_data();
+	struct irq_q_info *q = &pmp->rec_info[channel - 1];
+	unsigned int pos = (1 << (channel - 1));
+
+	if (!(pmp->channel_flags & pos))
+		return POLLERR; /* irq has quit */
+
+	if (q->head != q->tail)
+		return POLLIN; /* irq generated */
+
+	return 0;
+}
+
+unsigned char mods_alloc_channel(void)
+{
+	struct mods_priv *pmp = get_all_data();
+	int i = 0;
+	unsigned char channel = MODS_CHANNEL_MAX + 1;
+	unsigned char max_channels = mods_get_multi_instance()
+					 ? MODS_CHANNEL_MAX : 1;
+
+	LOG_ENT();
+
+	for (i = 0; i < max_channels; i++) {
+		if (!test_and_set_bit(i, &pmp->channel_flags)) {
+			channel = i + 1;
+			mods_debug_printk(DEBUG_IOCTL,
+					  "open channel %u (bit mask 0x%lx)\n",
+					  (unsigned int)(i + 1),
+					  pmp->channel_flags);
+			break;
+		}
+
+	}
+
+	LOG_EXT();
+	return channel;
+}
+
+void mods_free_channel(unsigned char channel)
+{
+	struct mods_priv *pmp = get_all_data();
+	struct dev_irq_map *del = NULL;
+	struct dev_irq_map *next = NULL;
+	struct irq_q_info *q = &pmp->rec_info[channel - 1];
+
+	LOG_ENT();
+
+	/* Release all interrupts */
+	list_for_each_entry_safe(del, next, &pmp->irq_head[channel - 1], list) {
+		list_del(&del->list);
+		if (del->type == MODS_IRQ_TYPE_CPU) {
+			mods_warning_printk(
+				"CPU IRQ 0x%x is still hooked, unhooking\n",
+				del->apic_irq);
+		}
+#ifdef CONFIG_PCI
+		else {
+			mods_warning_printk(
+	"%s IRQ 0x%x for dev %04x:%x:%02x.%x is still hooked, unhooking\n",
+				(del->type == MODS_IRQ_TYPE_MSI)
+					? "MSI" : "INTx",
+				del->dev->irq,
+				(unsigned int)(pci_domain_nr(del->dev->bus)),
+				(unsigned int)(del->dev->bus->number),
+				(unsigned int)PCI_SLOT(del->dev->devfn),
+				(unsigned int)PCI_FUNC(del->dev->devfn));
+		}
+#endif
+		mods_free_map(del);
+	}
+
+	/* Clear queue */
+	memset(q, 0, sizeof(*q));
+
+	/* Indicate the channel is free */
+	clear_bit(channel - 1, &pmp->channel_flags);
+
+	mods_debug_printk(DEBUG_IOCTL, "closed channel %u\n",
+			  (unsigned int)channel);
+	LOG_EXT();
+}
+#ifdef CONFIG_PCI
+static int mods_register_pci_irq(struct file *pfile,
+				 struct MODS_REGISTER_IRQ_3 *p)
+{
+	struct pci_dev *dev;
+	unsigned int devfn;
+	unsigned char channel;
+	MODS_PRIV private_data = pfile->private_data;
+
+	LOG_ENT();
+
+	/* Identify the caller */
+	channel = MODS_GET_FILE_PRIVATE_ID(pfile);
+	WARN_ON(id_is_valid(channel) != OK);
+	if (id_is_valid(channel) != OK) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Get the PCI device structure for the specified device from kernel */
+	devfn = PCI_DEVFN(p->dev.device, p->dev.function);
+	dev = MODS_PCI_GET_SLOT(p->dev.domain, p->dev.bus, devfn);
+	if (!dev) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Determine if the interrupt is already hooked */
+	if (mods_lookup_irq(0, dev, 0) == IRQ_FOUND) {
+		mods_error_printk(
+		 "IRQ for dev %04x:%x:%02x.%x has already been registered\n",
+			(unsigned int)p->dev.domain,
+			(unsigned int)p->dev.bus,
+			(unsigned int)p->dev.device,
+			(unsigned int)p->dev.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Determine if the device supports MSI */
+	if (p->irq_type == MODS_IRQ_TYPE_MSI) {
+#ifdef CONFIG_PCI_MSI
+		if (pci_find_capability(dev, PCI_CAP_ID_MSI) == 0) {
+			mods_error_printk(
+				"dev %04x:%x:%02x.%x does not support MSI\n",
+				(unsigned int)p->dev.domain,
+				(unsigned int)p->dev.bus,
+				(unsigned int)p->dev.device,
+				(unsigned int)p->dev.function);
+			LOG_EXT();
+			return -EINVAL;
+		}
+#else
+		mods_error_printk("the kernel does not support MSI!\n");
+		return -EINVAL;
+#endif
+	}
+
+	/* Enable device on the PCI bus */
+	if (mods_enable_device(private_data, dev)) {
+		mods_error_printk("unable to enable dev %04x:%x:%02x.%x\n",
+				  (unsigned int)p->dev.domain,
+				  (unsigned int)p->dev.bus,
+				  (unsigned int)p->dev.device,
+				  (unsigned int)p->dev.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Enable MSI */
+#ifdef CONFIG_PCI_MSI
+	if (p->irq_type == MODS_IRQ_TYPE_MSI) {
+		if (pci_enable_msi(dev) != 0) {
+			mods_error_printk(
+				"unable to enable MSI on dev %04x:%x:%02x.%x\n",
+				(unsigned int)p->dev.domain,
+				(unsigned int)p->dev.bus,
+				(unsigned int)p->dev.device,
+				(unsigned int)p->dev.function);
+			return -EINVAL;
+		}
+	}
+#endif
+
+	/* Register interrupt */
+	if (add_irq_map(channel, dev, dev->irq, p) != OK) {
+#ifdef CONFIG_PCI_MSI
+		if (p->irq_type == MODS_IRQ_TYPE_MSI)
+			pci_disable_msi(dev);
+#endif
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	return OK;
+}
+#endif /* CONFIG_PCI */
+
+static int mods_register_cpu_irq(struct file *pfile,
+				 struct MODS_REGISTER_IRQ_3 *p)
+{
+	unsigned char channel;
+	unsigned int irq;
+
+	LOG_ENT();
+
+	irq = p->dev.bus;
+
+	/* Identify the caller */
+	channel = MODS_GET_FILE_PRIVATE_ID(pfile);
+	WARN_ON(id_is_valid(channel) != OK);
+	if (id_is_valid(channel) != OK) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Determine if the interrupt is already hooked */
+	if (mods_lookup_irq(0, 0, irq) == IRQ_FOUND) {
+		mods_error_printk("CPU IRQ 0x%x has already been registered\n",
+				  irq);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Register interrupt */
+	if (add_irq_map(channel, 0, irq, p) != OK) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	return OK;
+}
+
+#ifdef CONFIG_PCI
+static int mods_unregister_pci_irq(struct file *pfile,
+				   struct MODS_REGISTER_IRQ_2 *p)
+{
+	struct mods_priv *pmp = get_all_data();
+	struct dev_irq_map *del = NULL;
+	struct dev_irq_map *next;
+	struct pci_dev *dev;
+	unsigned int devfn;
+	unsigned char channel;
+
+	LOG_ENT();
+
+	/* Identify the caller */
+	channel = MODS_GET_FILE_PRIVATE_ID(pfile);
+	WARN_ON(id_is_valid(channel) != OK);
+	if (id_is_valid(channel) != OK) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Get the PCI device structure for the specified device from kernel */
+	devfn = PCI_DEVFN(p->dev.device, p->dev.function);
+	dev = MODS_PCI_GET_SLOT(p->dev.domain, p->dev.bus, devfn);
+	if (!dev) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Determine if the interrupt is already hooked by this client */
+	if (mods_lookup_irq(channel, dev, 0) == IRQ_NOT_FOUND) {
+		mods_error_printk(
+			"IRQ for dev %04x:%x:%02x.%x not hooked\n",
+			(unsigned int)p->dev.domain,
+			(unsigned int)p->dev.bus,
+			(unsigned int)p->dev.device,
+			(unsigned int)p->dev.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Delete device interrupt from the list */
+	list_for_each_entry_safe(del, next, &pmp->irq_head[channel - 1], list) {
+		if (dev == del->dev) {
+			if (del->type != p->type) {
+				mods_error_printk("wrong IRQ type passed\n");
+				LOG_EXT();
+				return -EINVAL;
+			}
+			list_del(&del->list);
+			mods_debug_printk(DEBUG_ISR,
+				"%04x:%x:%02x.%x unregistered %s IRQ 0x%x\n",
+				(unsigned int)p->dev.domain,
+				(unsigned int)p->dev.bus,
+				(unsigned int)p->dev.device,
+				(unsigned int)p->dev.function,
+				(del->type == MODS_IRQ_TYPE_MSI)
+					  ? "MSI" : "INTx",
+				del->dev->irq);
+			mods_free_map(del);
+			break;
+		}
+	}
+
+	LOG_EXT();
+	return OK;
+}
+#endif
+
+static int mods_unregister_cpu_irq(struct file *pfile,
+				   struct MODS_REGISTER_IRQ_2 *p)
+{
+	struct mods_priv *pmp = get_all_data();
+	struct dev_irq_map *del = NULL;
+	struct dev_irq_map *next;
+	unsigned int irq;
+	unsigned char channel;
+
+	LOG_ENT();
+
+	irq = p->dev.bus;
+
+	/* Identify the caller */
+	channel = MODS_GET_FILE_PRIVATE_ID(pfile);
+	WARN_ON(id_is_valid(channel) != OK);
+	if (id_is_valid(channel) != OK) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Determine if the interrupt is already hooked by this client */
+	if (mods_lookup_irq(channel, 0, irq) == IRQ_NOT_FOUND) {
+		mods_error_printk(
+			"IRQ 0x%x not hooked, can't unhook\n",
+			irq);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Delete device interrupt from the list */
+	list_for_each_entry_safe(del, next, &pmp->irq_head[channel - 1], list) {
+		if ((irq == del->apic_irq) && (del->dev == 0)) {
+			if (del->type != p->type) {
+				mods_error_printk("wrong IRQ type passed\n");
+				LOG_EXT();
+				return -EINVAL;
+			}
+			list_del(&del->list);
+			mods_debug_printk(DEBUG_ISR,
+					  "unregistered CPU IRQ 0x%x\n",
+					  irq);
+			mods_free_map(del);
+			break;
+		}
+	}
+
+	LOG_EXT();
+	return OK;
+}
+
+/*************************
+ * ESCAPE CALL FUNCTIONS *
+ *************************/
+
+
+int esc_mods_register_irq_3(struct file *pfile,
+			    struct MODS_REGISTER_IRQ_3 *p)
+{
+	if (p->irq_type == MODS_IRQ_TYPE_CPU)
+		return mods_register_cpu_irq(pfile, p);
+#ifdef CONFIG_PCI
+	return mods_register_pci_irq(pfile, p);
+#else
+	mods_error_printk("PCI not available\n");
+	return -EINVAL;
+#endif
+}
+
+int esc_mods_register_irq_2(struct file *pfile,
+			    struct MODS_REGISTER_IRQ_2 *p)
+{
+	struct MODS_REGISTER_IRQ_3 irq_data = { {0} };
+
+	irq_data.dev = p->dev;
+	irq_data.irq_type = p->type;
+	if (p->type == MODS_IRQ_TYPE_CPU)
+		return mods_register_cpu_irq(pfile, &irq_data);
+#ifdef CONFIG_PCI
+	{
+
+	/* Get the PCI device structure for the specified device from kernel */
+	unsigned int devfn;
+	struct pci_dev *dev;
+
+	devfn = PCI_DEVFN(p->dev.device, p->dev.function);
+	dev  = MODS_PCI_GET_SLOT(p->dev.domain, p->dev.bus, devfn);
+	if (!dev) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+	/* initialize the new entry to behave like old implementation */
+	irq_data.mask_info_cnt = 0;
+	if ((p->type == MODS_IRQ_TYPE_INT) && is_nvidia_device(dev)) {
+		irq_data.aperture_addr = pci_resource_start(dev, 0);
+		irq_data.aperture_size = 0x200;
+	}
+
+	return mods_register_pci_irq(pfile, &irq_data);
+	}
+#else
+	mods_error_printk("PCI not available\n");
+	return -EINVAL;
+#endif
+}
+
+int esc_mods_register_irq(struct file *pfile,
+			  struct MODS_REGISTER_IRQ *p)
+{
+	struct MODS_REGISTER_IRQ_2 register_irq = { {0} };
+
+	register_irq.dev.domain		= 0;
+	register_irq.dev.bus		= p->dev.bus;
+	register_irq.dev.device		= p->dev.device;
+	register_irq.dev.function	= p->dev.function;
+	register_irq.type		= p->type;
+
+	return esc_mods_register_irq_2(pfile, &register_irq);
+}
+
+int esc_mods_unregister_irq_2(struct file *pfile,
+				  struct MODS_REGISTER_IRQ_2 *p)
+{
+	if (p->type == MODS_IRQ_TYPE_CPU)
+		return mods_unregister_cpu_irq(pfile, p);
+#ifdef CONFIG_PCI
+	return mods_unregister_pci_irq(pfile, p);
+#else
+	return -EINVAL;
+#endif
+}
+
+int esc_mods_unregister_irq(struct file *pfile,
+				struct MODS_REGISTER_IRQ *p)
+{
+	struct MODS_REGISTER_IRQ_2 register_irq = { {0} };
+
+	register_irq.dev.domain		= 0;
+	register_irq.dev.bus		= p->dev.bus;
+	register_irq.dev.device		= p->dev.device;
+	register_irq.dev.function	= p->dev.function;
+	register_irq.type		= p->type;
+
+	return esc_mods_unregister_irq_2(pfile, &register_irq);
+}
+
+int esc_mods_query_irq_2(struct file *pfile, struct MODS_QUERY_IRQ_2 *p)
+{
+	unsigned char channel;
+	struct irq_q_info *q = NULL;
+	struct mods_priv *pmp = get_all_data();
+	unsigned int i = 0;
+	unsigned long flags = 0;
+	unsigned int cur_time = get_cur_time();
+
+	/* Lock IRQ queue */
+	LOG_ENT();
+	spin_lock_irqsave(&pmp->lock, flags);
+
+	/* Identify the caller */
+	channel = MODS_GET_FILE_PRIVATE_ID(pfile);
+	WARN_ON(id_is_valid(channel) != OK);
+	if (id_is_valid(channel) != OK) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Clear return array */
+	memset(p->irq_list, 0xFF, sizeof(p->irq_list));
+
+	/* Fill in return array with IRQ information */
+	q = &pmp->rec_info[channel - 1];
+	for (i = 0;
+		 (q->head != q->tail) && (i < MODS_MAX_IRQS);
+		 q->head++, i++) {
+
+		unsigned int    index = q->head & (MODS_MAX_IRQS - 1);
+		struct pci_dev *dev   = q->data[index].dev;
+
+		if (dev) {
+			p->irq_list[i].dev.domain = pci_domain_nr(dev->bus);
+			p->irq_list[i].dev.bus = dev->bus->number;
+			p->irq_list[i].dev.device = PCI_SLOT(dev->devfn);
+			p->irq_list[i].dev.function = PCI_FUNC(dev->devfn);
+		} else {
+			p->irq_list[i].dev.domain = 0;
+			p->irq_list[i].dev.bus = q->data[index].irq;
+			p->irq_list[i].dev.device = 0xFFU;
+			p->irq_list[i].dev.function = 0xFFU;
+		}
+		p->irq_list[i].delay = cur_time - q->data[index].time;
+
+		/* Print info about IRQ status returned */
+		if (dev) {
+			mods_debug_printk(DEBUG_ISR_DETAILED,
+		   "retrieved IRQ dev %04x:%x:%02x.%x, time=%uus, delay=%uus\n",
+				(unsigned int)p->irq_list[i].dev.domain,
+				(unsigned int)p->irq_list[i].dev.bus,
+				(unsigned int)p->irq_list[i].dev.device,
+				(unsigned int)p->irq_list[i].dev.function,
+				q->data[index].time,
+				p->irq_list[i].delay);
+		} else {
+			mods_debug_printk(DEBUG_ISR_DETAILED,
+				"retrieved IRQ 0x%x, time=%uus, delay=%uus\n",
+				(unsigned int)p->irq_list[i].dev.bus,
+				q->data[index].time,
+				p->irq_list[i].delay);
+		}
+	}
+
+	/* Indicate if there are more IRQs pending */
+	if (q->head != q->tail)
+		p->more = 1;
+
+	/* Unlock IRQ queue */
+	spin_unlock_irqrestore(&pmp->lock, flags);
+	LOG_EXT();
+
+	return OK;
+}
+
+int esc_mods_query_irq(struct file *pfile,
+			   struct MODS_QUERY_IRQ *p)
+{
+	int retval, i;
+	struct MODS_QUERY_IRQ_2 query_irq = { { {0} } };
+
+	retval = esc_mods_query_irq_2(pfile, &query_irq);
+	if (retval)
+		return retval;
+
+	for (i = 0; i < MODS_MAX_IRQS; i++) {
+		p->irq_list[i].dev.bus    = query_irq.irq_list[i].dev.bus;
+		p->irq_list[i].dev.device = query_irq.irq_list[i].dev.device;
+		p->irq_list[i].dev.function
+					  = query_irq.irq_list[i].dev.function;
+		p->irq_list[i].delay	  = query_irq.irq_list[i].delay;
+	}
+	p->more = query_irq.more;
+	return OK;
+}
+
+int esc_mods_set_irq_multimask(struct file *pfile,
+				struct MODS_SET_IRQ_MULTIMASK *p)
+{
+	struct mods_priv *pmp = get_all_data();
+	struct pci_dev *dev = 0;
+	unsigned long flags = 0;
+	unsigned char channel;
+	u32 irq = ~0U;
+	int ret = -EINVAL;
+	int update_state_reg = 0;
+
+	LOG_ENT();
+
+	/* Identify the caller */
+	channel = MODS_GET_FILE_PRIVATE_ID(pfile);
+	WARN_ON(id_is_valid(channel) != OK);
+	if (id_is_valid(channel) != OK) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Print info */
+	if (p->irq_type == MODS_IRQ_TYPE_CPU) {
+		mods_debug_printk(
+			DEBUG_ISR,
+			"set CPU IRQ 0x%x mask &0x%llx |0x%llx addr=0x%llx\n",
+			(unsigned int)p->dev.bus,
+			p->mask_info[0].and_mask, p->mask_info[0].or_mask,
+			p->aperture_addr + p->mask_info[0].reg_offset);
+	} else {
+		mods_debug_printk(
+			DEBUG_ISR,
+"set %s IRQ mask dev %04x:%x:%02x.%x mask t%d &0x%llx |0x%llx addr=0x%llx\n",
+			p->irq_type == MODS_IRQ_TYPE_INT ? "INT" : "MSI",
+			(unsigned int)p->dev.domain,
+			(unsigned int)p->dev.bus,
+			(unsigned int)p->dev.device,
+			(unsigned int)p->dev.function,
+			p->mask_info[0].mask_type,
+			p->mask_info[0].and_mask,
+			p->mask_info[0].or_mask,
+			p->aperture_addr + p->mask_info[0].reg_offset);
+	}
+
+	/* Verify mask type */
+	if (p->mask_info[0].mask_type != MODS_MASK_TYPE_IRQ_DISABLE &&
+		p->mask_info[0].mask_type != MODS_MASK_TYPE_IRQ_DISABLE64) {
+		mods_error_printk("invalid mask type\n");
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Determine which interrupt is referenced */
+	if (p->irq_type == MODS_IRQ_TYPE_CPU)
+		irq = p->dev.bus;
+	else if (p->irq_type == MODS_IRQ_TYPE_INT) {
+#ifdef CONFIG_PCI
+		/* Get the PCI dev struct for the specified device from kernel*/
+		unsigned int devfn = PCI_DEVFN(p->dev.device, p->dev.function);
+
+		dev = MODS_PCI_GET_SLOT(p->dev.domain, p->dev.bus, devfn);
+		if (!dev) {
+			LOG_EXT();
+			return -EINVAL;
+		}
+		update_state_reg = is_nvidia_device(dev);
+		if (!update_state_reg) {
+			mods_error_printk(
+			"set_irq_multimask is only supported GPUs!\n");
+			LOG_EXT();
+			return -EINVAL;
+		}
+#else
+		mods_error_printk("PCI not available\n");
+		LOG_EXT();
+		return -EINVAL;
+#endif
+	} else {
+		mods_error_printk("set_irq_multimask not supported for MSI!\n");
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Lock IRQ queue */
+	spin_lock_irqsave(&pmp->lock, flags);
+	{
+	struct dev_irq_map *t = NULL;
+	struct dev_irq_map *next = NULL;
+	struct irq_mask_info *im = NULL;
+	struct mods_mask_info *mm = NULL;
+
+	list_for_each_entry_safe(t, next, &pmp->irq_head[channel-1], list) {
+		if ((dev && (t->dev == dev)) ||
+		    (!dev && (t->apic_irq == irq))) {
+			u32   i   = 0;
+			char *bar = 0;
+
+			if (t->type != p->irq_type) {
+				mods_error_printk(
+				"IRQ type does not match registered IRQ\n");
+				break;
+			}
+			if (t->dev_irq_aperture) {
+				iounmap(t->dev_irq_aperture);
+				t->dev_irq_aperture = 0;
+				t->mask_info_cnt = 0;
+				t->mask_info[0].dev_irq_mask_reg = 0;
+				t->mask_info[0].dev_irq_disable_reg = 0;
+				t->mask_info[0].dev_irq_state = 0;
+				mods_warning_printk("resetting IRQ mask\n");
+			}
+			bar = ioremap_nocache(p->aperture_addr,
+					      p->aperture_size);
+			if (!bar) {
+				mods_error_printk(
+				"unable to remap specified aperture\n");
+				break;
+			}
+
+			t->dev_irq_aperture = bar;
+			t->mask_info_cnt = p->mask_info_cnt;
+			for (i = 0; i < p->mask_info_cnt; i++) {
+				im = &t->mask_info[i];
+				mm = &p->mask_info[i];
+				im->dev_irq_disable_reg =
+				    (u32 *)(bar + mm->reg_offset);
+				im->dev_irq_mask_reg =
+				    (u32 *)(bar + mm->reg_offset);
+				im->irq_and_mask = mm->and_mask;
+				im->irq_or_mask = mm->or_mask;
+				im->mask_type = mm->mask_type;
+				if (update_state_reg) {
+					im->dev_irq_state =
+					    (u32 *)(bar+0x100);
+					im->dev_irq_mask_reg =
+					    (u32 *)(bar+0x140);
+				} else {
+					im->dev_irq_state = 0;
+					im->dev_irq_mask_reg = 0;
+				}
+			}
+			ret = OK;
+			break;
+		}
+	}
+	}
+	/* Unlock IRQ queue */
+	spin_unlock_irqrestore(&pmp->lock, flags);
+	LOG_EXT();
+
+	return ret;
+}
+
+int esc_mods_set_irq_mask_2(struct file *pfile,
+				struct MODS_SET_IRQ_MASK_2 *p)
+{
+	struct MODS_SET_IRQ_MULTIMASK set_irq_multimask = {0};
+
+	set_irq_multimask.aperture_addr	= p->aperture_addr;
+	set_irq_multimask.aperture_size	= p->aperture_size;
+	set_irq_multimask.mask_info_cnt = 1;
+	set_irq_multimask.mask_info[0].reg_offset = p->reg_offset;
+	set_irq_multimask.mask_info[0].and_mask	  = p->and_mask;
+	set_irq_multimask.mask_info[0].or_mask	  = p->or_mask;
+	set_irq_multimask.mask_info[0].mask_type  = p->mask_type;
+	set_irq_multimask.dev.domain	= p->dev.domain;
+	set_irq_multimask.dev.bus	= p->dev.bus;
+	set_irq_multimask.dev.device	= p->dev.device;
+	set_irq_multimask.dev.function	= p->dev.function;
+	set_irq_multimask.irq_type	= p->irq_type;
+
+	return esc_mods_set_irq_multimask(pfile, &set_irq_multimask);
+}
+
+int esc_mods_set_irq_mask(struct file *pfile,
+			  struct MODS_SET_IRQ_MASK *p)
+{
+	struct MODS_SET_IRQ_MULTIMASK set_irq_multimask = {0};
+
+	set_irq_multimask.aperture_addr	= p->aperture_addr;
+	set_irq_multimask.aperture_size	= p->aperture_size;
+	set_irq_multimask.mask_info_cnt = 1;
+	set_irq_multimask.mask_info[0].reg_offset	= p->reg_offset;
+	set_irq_multimask.mask_info[0].and_mask		= p->and_mask;
+	set_irq_multimask.mask_info[0].or_mask		= p->or_mask;
+	set_irq_multimask.mask_info[0].mask_type	= p->mask_type;
+	set_irq_multimask.dev.domain	= 0;
+	set_irq_multimask.dev.bus	= p->dev.bus;
+	set_irq_multimask.dev.device	= p->dev.device;
+	set_irq_multimask.dev.function	= p->dev.function;
+	set_irq_multimask.irq_type	= p->irq_type;
+
+	return esc_mods_set_irq_multimask(pfile, &set_irq_multimask);
+}
+
+int esc_mods_irq_handled_2(struct file *pfile,
+			   struct MODS_REGISTER_IRQ_2 *p)
+{
+	struct mods_priv *pmp = get_all_data();
+	unsigned long flags = 0;
+	unsigned char channel;
+	u32 irq = p->dev.bus;
+	struct dev_irq_map *t = NULL;
+	struct dev_irq_map *next = NULL;
+	int ret = -EINVAL;
+
+	if (p->type != MODS_IRQ_TYPE_CPU)
+		return -EINVAL;
+
+	/* Lock IRQ queue */
+	LOG_ENT();
+	spin_lock_irqsave(&pmp->lock, flags);
+
+	/* Identify the caller */
+	channel = MODS_GET_FILE_PRIVATE_ID(pfile);
+	WARN_ON(id_is_valid(channel) != OK);
+	if (id_is_valid(channel) != OK) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	/* Print info */
+	mods_debug_printk(DEBUG_ISR_DETAILED,
+			  "mark CPU IRQ 0x%x handled\n", irq);
+
+	list_for_each_entry_safe(t, next, &pmp->irq_head[channel-1], list) {
+		if (t->apic_irq == irq) {
+			if (t->type != p->type) {
+				mods_error_printk(
+				"IRQ type doesn't match registered IRQ\n");
+			} else {
+				enable_irq(irq);
+				ret = OK;
+			}
+			break;
+		}
+	}
+
+	/* Unlock IRQ queue */
+	spin_unlock_irqrestore(&pmp->lock, flags);
+	LOG_EXT();
+
+	return ret;
+}
+
+int esc_mods_irq_handled(struct file *pfile,
+			 struct MODS_REGISTER_IRQ *p)
+{
+	struct MODS_REGISTER_IRQ_2 register_irq = { {0} };
+
+	register_irq.dev.domain		= 0;
+	register_irq.dev.bus		= p->dev.bus;
+	register_irq.dev.device		= p->dev.device;
+	register_irq.dev.function	= p->dev.function;
+	register_irq.type		= p->type;
+
+	return esc_mods_irq_handled_2(pfile, &register_irq);
+}
+
+#if defined(MODS_TEGRA) && defined(CONFIG_OF_IRQ) && defined(CONFIG_OF)
+int esc_mods_map_irq(struct file *pfile,
+					 struct MODS_DT_INFO *p)
+{
+	int ret;
+	/* the physical irq */
+	int hwirq;
+	/* platform device handle */
+	struct platform_device *pdev = NULL;
+	/* irq parameters */
+	struct of_phandle_args oirq;
+	/* Search for the node by device tree name */
+	struct device_node *np = of_find_node_by_name(NULL, p->dt_name);
+
+	/* Can be multiple nodes that share the same dt name, */
+	/* make sure you get the correct node matched by the device's full */
+	/* name in device tree (i.e. watchdog@30c0000 as opposed */
+	/* to watchdog) */
+	while (of_node_cmp(np->full_name, p->full_name) != 0)
+		np = of_find_node_by_name(np, p->dt_name);
+
+	p->irq = irq_of_parse_and_map(np, p->index);
+	ret = of_irq_parse_one(np, p->index, &oirq);
+	if (ret) {
+		mods_error_printk("Could not parse IRQ\n");
+		return -EINVAL;
+	}
+
+	hwirq = oirq.args[1];
+	/* Get the platform device handle */
+	pdev = of_find_device_by_node(np);
+
+	if (of_node_cmp(p->dt_name, "watchdog") == 0) {
+		/* Enable and unmask interrupt for watchdog */
+		struct resource *res_src = platform_get_resource(pdev,
+		IORESOURCE_MEM, 0);
+		struct resource *res_tke = platform_get_resource(pdev,
+		IORESOURCE_MEM, 2);
+		void __iomem *wdt_tke = devm_ioremap(&pdev->dev,
+		res_tke->start, resource_size(res_tke));
+		int wdt_index = ((res_src->start >> 16) & 0xF) - 0xc;
+
+		writel(TOP_TKE_TKEIE_WDT_MASK(wdt_index), wdt_tke +
+		TOP_TKE_TKEIE(hwirq));
+	}
+
+	/* enable the interrupt */
+	return 0;
+
+}
+#endif
diff --git a/drivers/misc/mods/mods_krnl.c b/drivers/misc/mods/mods_krnl.c
new file mode 100644
index 00000000..15f78666
--- /dev/null
+++ b/drivers/misc/mods/mods_krnl.c
@@ -0,0 +1,1582 @@
+/*
+ * mods_krnl.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2008-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mods_internal.h"
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <linux/miscdevice.h>
+#include <linux/screen_info.h>
+#include <linux/uaccess.h>
+#ifdef MODS_HAS_CONSOLE_LOCK
+#   include <linux/console.h>
+#endif
+
+/***********************************************************************
+ * mods_krnl_* functions, driver interfaces called by the Linux kernel *
+ ***********************************************************************/
+static int mods_krnl_open(struct inode *, struct file *);
+static int mods_krnl_close(struct inode *, struct file *);
+static unsigned int mods_krnl_poll(struct file *, poll_table *);
+static int mods_krnl_mmap(struct file *, struct vm_area_struct *);
+static long mods_krnl_ioctl(struct file *, unsigned int, unsigned long);
+
+/* character driver entry points */
+const struct file_operations mods_fops = {
+	.owner			= THIS_MODULE,
+	.open			= mods_krnl_open,
+	.release		= mods_krnl_close,
+	.poll			= mods_krnl_poll,
+	.mmap			= mods_krnl_mmap,
+	.unlocked_ioctl = mods_krnl_ioctl,
+#if defined(HAVE_COMPAT_IOCTL)
+	.compat_ioctl	= mods_krnl_ioctl,
+#endif
+};
+
+#define DEVICE_NAME "mods"
+
+struct miscdevice mods_dev = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = DEVICE_NAME,
+	.fops = &mods_fops
+};
+
+#if defined(MODS_CAN_REGISTER_PCI_DEV)
+static pci_ers_result_t mods_pci_error_detected(struct pci_dev *,
+						enum pci_channel_state);
+static pci_ers_result_t mods_pci_mmio_enabled(struct pci_dev *);
+static void mods_pci_resume(struct pci_dev *);
+
+struct pci_error_handlers mods_pci_error_handlers = {
+	.error_detected	= mods_pci_error_detected,
+	.mmio_enabled	= mods_pci_mmio_enabled,
+	.resume		= mods_pci_resume,
+};
+
+static const struct pci_device_id mods_pci_table[] = {
+	{
+		.vendor		= PCI_VENDOR_ID_NVIDIA,
+		.device		= PCI_ANY_ID,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.class		= (PCI_CLASS_DISPLAY_VGA << 8),
+		.class_mask	= ~0
+	},
+	{
+		.vendor		= PCI_VENDOR_ID_NVIDIA,
+		.device		= PCI_ANY_ID,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.class		= (PCI_CLASS_DISPLAY_3D << 8),
+		.class_mask	= ~0
+	},
+	{ }
+};
+
+static int mods_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+	return 0;
+}
+
+struct pci_driver mods_pci_driver = {
+	.name		= DEVICE_NAME,
+	.id_table	= mods_pci_table,
+	.probe		= mods_pci_probe,
+	.err_handler	= &mods_pci_error_handlers,
+};
+#endif
+
+/***********************************************
+ * module wide parameters and access functions *
+ * used to avoid globalization of variables    *
+ ***********************************************/
+static int debug = -0x80000000;
+static int multi_instance = MODS_MULTI_INSTANCE_DEFAULT_VALUE;
+
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+static int ppc_tce_bypass = MODS_PPC_TCE_BYPASS_DEFAULT;
+
+void mods_set_ppc_tce_bypass(int bypass)
+{
+	ppc_tce_bypass = bypass;
+}
+
+int mods_get_ppc_tce_bypass(void)
+{
+	return ppc_tce_bypass;
+}
+#endif
+
+void mods_set_debug_level(int mask)
+{
+	debug = mask;
+}
+
+int mods_get_debug_level(void)
+{
+	return debug;
+}
+
+int mods_check_debug_level(int mask)
+{
+	return ((debug & mask) == mask) ? 1 : 0;
+}
+
+void mods_set_multi_instance(int mi)
+{
+	multi_instance = (mi > 0) ? 1 : -1;
+}
+
+int mods_get_multi_instance(void)
+{
+	return multi_instance > 0;
+}
+
+/******************************
+ * INIT/EXIT MODULE FUNCTIONS *
+ ******************************/
+static int __init mods_init_module(void)
+{
+	int rc;
+
+	LOG_ENT();
+
+	rc = misc_register(&mods_dev);
+	if (rc < 0)
+		return -EBUSY;
+
+#if defined(MODS_CAN_REGISTER_PCI_DEV)
+	rc = pci_register_driver(&mods_pci_driver);
+	if (rc < 0)
+		return -EBUSY;
+#endif
+
+	mods_init_irq();
+
+#if defined(MODS_HAS_CLOCK)
+	mods_init_clock_api();
+#endif
+
+	rc = mods_create_debugfs(&mods_dev);
+	if (rc < 0)
+		return rc;
+
+	rc = mods_init_tegradc();
+	if (rc < 0)
+		return rc;
+
+	rc = mods_init_dmabuf();
+	if (rc < 0)
+		return rc;
+
+#if defined(MODS_TEGRA)
+	/* tegra prod */
+	mods_tegra_prod_init(&mods_dev);
+#endif
+
+	mods_info_printk("driver loaded, version %x.%02x\n",
+			 (MODS_DRIVER_VERSION>>8),
+			 (MODS_DRIVER_VERSION&0xFF));
+	LOG_EXT();
+	return OK;
+}
+
+static void __exit mods_exit_module(void)
+{
+	LOG_ENT();
+
+	mods_exit_dmabuf();
+
+	mods_exit_tegradc();
+
+	mods_remove_debugfs();
+
+	mods_cleanup_irq();
+
+#if defined(MODS_CAN_REGISTER_PCI_DEV)
+	pci_unregister_driver(&mods_pci_driver);
+#endif
+
+	misc_deregister(&mods_dev);
+
+#if defined(MODS_HAS_CLOCK)
+	mods_shutdown_clock_api();
+#endif
+
+	mods_info_printk("driver unloaded\n");
+	LOG_EXT();
+}
+
+/***************************
+ * KERNEL INTERFACE SET UP *
+ ***************************/
+module_init(mods_init_module);
+module_exit(mods_exit_module);
+
+MODULE_LICENSE("GPL");
+
+#define STRING_VALUE(x) #x
+#define MAKE_MODULE_VERSION(x, y) STRING_VALUE(x) "." STRING_VALUE(y)
+MODULE_VERSION(MAKE_MODULE_VERSION(MODS_DRIVER_VERSION_MAJOR,
+				   MODS_DRIVER_VERSION_MINOR));
+
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug,
+"debug bitflags (2=ioctl 4=pci 8=acpi 16=irq 32=mem 64=fun +256=detailed)");
+
+module_param(multi_instance, int, 0644);
+MODULE_PARM_DESC(multi_instance,
+	"allows more than one client to simultaneously open the driver");
+
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+module_param(ppc_tce_bypass, int, 0644);
+MODULE_PARM_DESC(ppc_tce_bypass,
+	"PPC TCE bypass (0=sys default, 1=force bypass, 2=force non bypass)");
+#endif
+
+/********************
+ * HELPER FUNCTIONS *
+ ********************/
+static int id_is_valid(unsigned char channel)
+{
+	if (channel <= 0 || channel > MODS_CHANNEL_MAX)
+		return -EINVAL;
+
+	return OK;
+}
+
+static void mods_disable_all_devices(struct mods_file_private_data *priv)
+{
+#ifdef CONFIG_PCI
+	while (priv->enabled_devices != 0) {
+		struct en_dev_entry *old = priv->enabled_devices;
+
+		pci_disable_device(old->dev);
+		priv->enabled_devices = old->next;
+		kfree(old);
+	}
+#else
+	WARN_ON(priv->enabled_devices != 0);
+#endif
+}
+
+/*********************
+ * MAPPING FUNCTIONS *
+ *********************/
+static int mods_register_mapping(
+	struct file          *fp,
+	struct MODS_MEM_INFO *p_mem_info,
+	u64                   dma_addr,
+	u64                   virtual_address,
+	u32                   mapping_length)
+{
+	struct SYS_MAP_MEMORY *p_map_mem;
+	MODS_PRIV private_data = fp->private_data;
+
+	LOG_ENT();
+
+	p_map_mem = kmalloc(sizeof(*p_map_mem), GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!p_map_mem)) {
+		LOG_EXT();
+		return -ENOMEM;
+	}
+	memset(p_map_mem, 0, sizeof(*p_map_mem));
+
+	p_map_mem->dma_addr = dma_addr;
+	p_map_mem->virtual_addr = virtual_address;
+	p_map_mem->mapping_length = mapping_length;
+	p_map_mem->p_mem_info = p_mem_info;
+
+	list_add(&p_map_mem->list, private_data->mods_mapping_list);
+
+	mods_debug_printk(DEBUG_MEM_DETAILED,
+	    "map alloc %p as %p: phys 0x%llx, virt 0x%llx, size 0x%x\n",
+	    p_mem_info, p_map_mem, dma_addr, virtual_address, mapping_length);
+
+	LOG_EXT();
+	return OK;
+}
+
+static void mods_unregister_mapping(struct file *fp, u64 virtual_address)
+{
+	struct SYS_MAP_MEMORY *p_map_mem;
+	MODS_PRIV private_data = fp->private_data;
+
+	struct list_head  *head = private_data->mods_mapping_list;
+	struct list_head  *iter;
+
+	LOG_ENT();
+
+	list_for_each(iter, head) {
+		p_map_mem = list_entry(iter, struct SYS_MAP_MEMORY, list);
+
+		if (p_map_mem->virtual_addr == virtual_address) {
+			/* remove from the list */
+			list_del(iter);
+
+			/* free our data struct which keeps track of mapping */
+			kfree(p_map_mem);
+
+			return;
+		}
+	}
+	LOG_EXT();
+}
+
+static void mods_unregister_all_mappings(struct file *fp)
+{
+	struct SYS_MAP_MEMORY *p_map_mem;
+	MODS_PRIV private_data = fp->private_data;
+
+	struct list_head  *head = private_data->mods_mapping_list;
+	struct list_head  *iter;
+	struct list_head  *tmp;
+
+	LOG_ENT();
+
+	list_for_each_safe(iter, tmp, head) {
+		p_map_mem = list_entry(iter, struct SYS_MAP_MEMORY, list);
+		mods_unregister_mapping(fp, p_map_mem->virtual_addr);
+	}
+
+	LOG_EXT();
+}
+
+static pgprot_t mods_get_prot(u32 mem_type, pgprot_t prot)
+{
+	switch (mem_type) {
+	case MODS_MEMORY_CACHED:
+		return prot;
+
+	case MODS_MEMORY_UNCACHED:
+		return MODS_PGPROT_UC(prot);
+
+	case MODS_MEMORY_WRITECOMBINE:
+		return MODS_PGPROT_WC(prot);
+
+	default:
+		mods_warning_printk("unsupported memory type: %u\n",
+				    mem_type);
+		return prot;
+	}
+}
+
+static pgprot_t mods_get_prot_for_range(struct file *fp, u64 dma_addr,
+					u64 size, pgprot_t prot)
+{
+	MODS_PRIV private_data = fp->private_data;
+
+	if ((dma_addr == private_data->mem_type.dma_addr) &&
+		(size == private_data->mem_type.size)) {
+
+		return mods_get_prot(private_data->mem_type.type, prot);
+	}
+	return prot;
+}
+
+const char *mods_get_prot_str(u32 mem_type)
+{
+	switch (mem_type) {
+	case MODS_MEMORY_CACHED:
+		return "WB";
+
+	case MODS_MEMORY_UNCACHED:
+		return "UC";
+
+	case MODS_MEMORY_WRITECOMBINE:
+		return "WC";
+
+	default:
+		return "unknown";
+	}
+}
+
+static const char *mods_get_prot_str_for_range(struct file *fp,
+					       u64          dma_addr,
+					       u64          size)
+{
+	MODS_PRIV private_data = fp->private_data;
+
+	if ((dma_addr == private_data->mem_type.dma_addr) &&
+		(size == private_data->mem_type.size)) {
+
+		return mods_get_prot_str(private_data->mem_type.type);
+	}
+	return "default";
+}
+/********************
+ * PCI ERROR FUNCTIONS *
+ ********************/
+#if defined(MODS_CAN_REGISTER_PCI_DEV)
+static pci_ers_result_t mods_pci_error_detected(struct pci_dev *dev,
+						enum pci_channel_state state)
+{
+	mods_debug_printk(DEBUG_PCICFG,
+			  "pci_error_detected %04x:%x:%02x.%x\n",
+			  pci_domain_nr(dev->bus),
+			  dev->bus->number,
+			  PCI_SLOT(dev->devfn),
+			  PCI_FUNC(dev->devfn));
+
+	return PCI_ERS_RESULT_CAN_RECOVER;
+}
+
+static pci_ers_result_t mods_pci_mmio_enabled(struct pci_dev *dev)
+{
+	mods_debug_printk(DEBUG_PCICFG,
+			  "pci_mmio_enabled %04x:%x:%02x.%x\n",
+			  pci_domain_nr(dev->bus),
+			  dev->bus->number,
+			  PCI_SLOT(dev->devfn),
+			  PCI_FUNC(dev->devfn));
+
+	return PCI_ERS_RESULT_NEED_RESET;
+}
+
+static void mods_pci_resume(struct pci_dev *dev)
+{
+	mods_debug_printk(DEBUG_PCICFG,
+			  "pci_resume %04x:%x:%02x.%x\n",
+			  pci_domain_nr(dev->bus),
+			  dev->bus->number,
+			  PCI_SLOT(dev->devfn),
+			  PCI_FUNC(dev->devfn));
+}
+#endif
+
+/********************
+ * KERNEL FUNCTIONS *
+ ********************/
+static void mods_krnl_vma_open(struct vm_area_struct *vma)
+{
+	struct mods_vm_private_data *vma_private_data;
+
+	LOG_ENT();
+	mods_debug_printk(DEBUG_MEM_DETAILED,
+			  "open vma, virt 0x%lx, phys 0x%llx\n",
+			  vma->vm_start,
+			  (u64)(MODS_VMA_PGOFF(vma) << PAGE_SHIFT));
+
+	if (MODS_VMA_PRIVATE(vma)) {
+		vma_private_data = MODS_VMA_PRIVATE(vma);
+		atomic_inc(&vma_private_data->usage_count);
+	}
+	LOG_EXT();
+}
+
+static void mods_krnl_vma_close(struct vm_area_struct *vma)
+{
+	LOG_ENT();
+
+	if (MODS_VMA_PRIVATE(vma)) {
+		struct mods_vm_private_data *vma_private_data
+			= MODS_VMA_PRIVATE(vma);
+		if (atomic_dec_and_test(&vma_private_data->usage_count)) {
+			MODS_PRIV private_data =
+				vma_private_data->fp->private_data;
+
+			if (unlikely(mutex_lock_interruptible(
+						&private_data->mtx))) {
+				LOG_EXT();
+				return;
+			}
+
+			/* we need to unregister the mapping */
+			mods_unregister_mapping(vma_private_data->fp,
+						vma->vm_start);
+			mods_debug_printk(DEBUG_MEM_DETAILED,
+					  "closed vma, virt 0x%lx\n",
+					  vma->vm_start);
+			MODS_VMA_PRIVATE(vma) = NULL;
+			kfree(vma_private_data);
+
+			mutex_unlock(&private_data->mtx);
+		}
+	}
+	LOG_EXT();
+}
+
+static struct vm_operations_struct mods_krnl_vm_ops = {
+	.open	= mods_krnl_vma_open,
+	.close	= mods_krnl_vma_close
+};
+
+static int mods_krnl_open(struct inode *ip, struct file *fp)
+{
+	struct list_head *mods_alloc_list;
+	struct list_head *mods_mapping_list;
+	struct list_head *mods_pci_res_map_list;
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+	struct list_head *mods_ppc_tce_bypass_list;
+#endif
+	struct mods_file_private_data *private_data;
+	int id = 0;
+
+	LOG_ENT();
+
+	mods_alloc_list = kmalloc(sizeof(struct list_head),
+				  GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!mods_alloc_list)) {
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+	mods_mapping_list = kmalloc(sizeof(struct list_head),
+				    GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!mods_mapping_list)) {
+		kfree(mods_alloc_list);
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+	mods_pci_res_map_list = kmalloc(sizeof(struct list_head),
+					GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!mods_pci_res_map_list)) {
+		kfree(mods_alloc_list);
+		kfree(mods_mapping_list);
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+	mods_ppc_tce_bypass_list =
+		kmalloc(sizeof(struct list_head), GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!mods_ppc_tce_bypass_list)) {
+		kfree(mods_alloc_list);
+		kfree(mods_mapping_list);
+		kfree(mods_pci_res_map_list);
+		LOG_EXT();
+		return -ENOMEM;
+	}
+#endif
+
+	private_data = kmalloc(sizeof(*private_data),
+			       GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!private_data)) {
+		kfree(mods_alloc_list);
+		kfree(mods_mapping_list);
+		kfree(mods_pci_res_map_list);
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+		kfree(mods_ppc_tce_bypass_list);
+#endif
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+	id = mods_alloc_channel();
+	if (id_is_valid(id) != OK) {
+		mods_error_printk("too many clients\n");
+		kfree(mods_alloc_list);
+		kfree(mods_mapping_list);
+		kfree(mods_pci_res_map_list);
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+		kfree(mods_ppc_tce_bypass_list);
+#endif
+		kfree(private_data);
+		LOG_EXT();
+		return -EBUSY;
+	}
+
+	private_data->mods_id = id;
+	mods_irq_dev_set_pri(id, private_data);
+
+	INIT_LIST_HEAD(mods_alloc_list);
+	INIT_LIST_HEAD(mods_mapping_list);
+	INIT_LIST_HEAD(mods_pci_res_map_list);
+	private_data->mods_alloc_list = mods_alloc_list;
+	private_data->mods_mapping_list = mods_mapping_list;
+	private_data->mods_pci_res_map_list = mods_pci_res_map_list;
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+	INIT_LIST_HEAD(mods_ppc_tce_bypass_list);
+	private_data->mods_ppc_tce_bypass_list = mods_ppc_tce_bypass_list;
+#endif
+	private_data->enabled_devices = 0;
+	private_data->mem_type.dma_addr = 0;
+	private_data->mem_type.size = 0;
+	private_data->mem_type.type = 0;
+
+	mutex_init(&private_data->mtx);
+
+	init_waitqueue_head(&private_data->interrupt_event);
+
+	fp->private_data = private_data;
+
+	mods_info_printk("driver opened\n");
+	LOG_EXT();
+	return OK;
+}
+
+static int mods_krnl_close(struct inode *ip, struct file *fp)
+{
+	MODS_PRIV private_data = fp->private_data;
+	unsigned char id = MODS_GET_FILE_PRIVATE_ID(fp);
+	int ret = OK;
+
+	LOG_ENT();
+
+	WARN_ON(id_is_valid(id) != OK);
+	if (id_is_valid(id) != OK) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	mods_free_channel(id);
+	mods_irq_dev_clr_pri(id);
+
+	mods_unregister_all_mappings(fp);
+	ret = mods_unregister_all_alloc(fp);
+	if (ret)
+		mods_error_printk("failed to free all memory\n");
+	ret = MODS_UNREGISTER_PCI_MAP(fp);
+	if (ret)
+		mods_error_printk("failed to free pci mappings\n");
+
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+	ret = mods_unregister_all_ppc_tce_bypass(fp);
+	if (ret)
+		mods_error_printk("failed to restore dma bypass\n");
+#endif
+
+	mods_disable_all_devices(private_data);
+
+	kfree(private_data->mods_alloc_list);
+	kfree(private_data->mods_mapping_list);
+	kfree(private_data->mods_pci_res_map_list);
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+	kfree(private_data->mods_ppc_tce_bypass_list);
+#endif
+	kfree(private_data);
+
+	mods_info_printk("driver closed\n");
+	LOG_EXT();
+	return ret;
+}
+
+static unsigned int mods_krnl_poll(struct file *fp, poll_table *wait)
+{
+	unsigned int mask = 0;
+	MODS_PRIV private_data = fp->private_data;
+	unsigned char id = MODS_GET_FILE_PRIVATE_ID(fp);
+
+	if (!(fp->f_flags & O_NONBLOCK)) {
+		mods_debug_printk(DEBUG_ISR_DETAILED, "poll wait\n");
+		poll_wait(fp, &private_data->interrupt_event, wait);
+	}
+	/* if any interrupts pending then check intr, POLLIN on irq */
+	mask |= mods_irq_event_check(id);
+	mods_debug_printk(DEBUG_ISR_DETAILED, "poll mask 0x%x\n", mask);
+	return mask;
+}
+
+static int mods_krnl_map_inner(struct file *fp, struct vm_area_struct *vma);
+
+static int mods_krnl_mmap(struct file *fp, struct vm_area_struct *vma)
+{
+	struct mods_vm_private_data *vma_private_data;
+
+	LOG_ENT();
+
+	vma->vm_ops = &mods_krnl_vm_ops;
+
+	vma_private_data = kmalloc(sizeof(*vma_private_data),
+				   GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!vma_private_data)) {
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+	/* set private data for vm_area_struct */
+	atomic_set(&vma_private_data->usage_count, 0);
+	vma_private_data->fp = fp;
+	MODS_VMA_PRIVATE(vma) = vma_private_data;
+
+	/* call for the first time open function */
+	mods_krnl_vma_open(vma);
+
+	{
+		int ret = OK;
+		MODS_PRIV private_data = fp->private_data;
+
+		if (unlikely(mutex_lock_interruptible(&private_data->mtx)))
+			ret = -EINTR;
+		else {
+			ret = mods_krnl_map_inner(fp, vma);
+			mutex_unlock(&private_data->mtx);
+		}
+		LOG_EXT();
+		return ret;
+	}
+}
+
+static int mods_krnl_map_inner(struct file *fp, struct vm_area_struct *vma)
+{
+	u64                   req_pa     = MODS_VMA_OFFSET(vma);
+	struct MODS_MEM_INFO *p_mem_info = mods_find_alloc(fp, req_pa);
+	u32                   req_pages  = MODS_VMA_SIZE(vma) >> PAGE_SHIFT;
+
+	if ((req_pa             & ~PAGE_MASK) != 0 ||
+	    (MODS_VMA_SIZE(vma) & ~PAGE_MASK) != 0) {
+		mods_error_printk("requested mapping is not page-aligned\n");
+		return -EINVAL;
+	}
+
+	/* system memory */
+	if (p_mem_info) {
+		u32                     first, i;
+		struct MODS_PHYS_CHUNK *pt         = p_mem_info->pages;
+		u32                     have_pages = 0;
+		unsigned long           map_va     = 0;
+		const pgprot_t          prot       =
+		    mods_get_prot(p_mem_info->cache_type, vma->vm_page_prot);
+
+		/* Find the beginning of the requested range */
+		for (first = 0; first < p_mem_info->max_chunks; first++) {
+			u64 dma_addr;
+
+			if (!pt[first].allocated)
+				continue;
+			dma_addr = pt[first].dma_addr;
+			if ((req_pa >= dma_addr) &&
+			    (req_pa <  dma_addr + (PAGE_SIZE << pt->order))) {
+				break;
+			}
+		}
+
+		if (first == p_mem_info->max_chunks) {
+			mods_error_printk("can't satisfy requested mapping\n");
+			return -EINVAL;
+		}
+
+		/* Count how many remaining pages we have in the allocation */
+		for (i = first; i < p_mem_info->max_chunks; i++) {
+			if (!pt[i].allocated)
+				break;
+			if (i == first) {
+				u64 aoffs      = req_pa - pt[i].dma_addr;
+				u32 skip_pages = aoffs >> PAGE_SHIFT;
+
+				have_pages -= skip_pages;
+			}
+			have_pages += 1U << pt[i].order;
+		}
+
+		if (have_pages < req_pages) {
+			mods_error_printk("requested mapping exceeds bounds\n");
+			return -EINVAL;
+		}
+
+		/* Map pages into VA space */
+		map_va     = vma->vm_start;
+		have_pages = req_pages;
+		for (i = first; have_pages > 0; i++) {
+			u64 map_pa    = MODS_DMA_TO_PHYS(pt[i].dma_addr);
+			u32 map_size  = PAGE_SIZE << pt[i].order;
+			u32 map_pages = 1U << pt[i].order;
+
+			if (!pt[i].allocated)
+				break;
+
+			if (i == first) {
+				u64 aoffs = req_pa - pt[i].dma_addr;
+
+				map_pa    += aoffs;
+				map_size  -= aoffs;
+				map_pages -= aoffs >> PAGE_SHIFT;
+			}
+
+			if (map_pages > have_pages) {
+				map_size  = have_pages << PAGE_SHIFT;
+				map_pages = have_pages;
+			}
+
+			mods_debug_printk(DEBUG_MEM_DETAILED,
+			    "remap va 0x%lx pfn 0x%x size 0x%x pages 0x%x\n",
+			    map_va, (unsigned int)(map_pa>>PAGE_SHIFT),
+			    map_size, map_pages);
+
+			if (remap_pfn_range(vma,
+					    map_va,
+					    map_pa>>PAGE_SHIFT,
+					    map_size,
+					    prot)) {
+				mods_error_printk("failed to map memory\n");
+				return -EAGAIN;
+			}
+
+			map_va     += map_size;
+			have_pages -= map_pages;
+		}
+
+		/* MODS_VMA_OFFSET(vma) can change so it can't be used
+		 * to register the mapping
+		 */
+		mods_register_mapping(fp,
+				      p_mem_info,
+				      pt[first].dma_addr,
+				      vma->vm_start,
+				      MODS_VMA_SIZE(vma));
+
+	} else {
+		/* device memory */
+
+		mods_debug_printk(DEBUG_MEM,
+		    "map dev: phys 0x%llx, virt 0x%lx, size 0x%x, %s\n",
+		    req_pa,
+		    (unsigned long)vma->vm_start,
+		    (unsigned int)MODS_VMA_SIZE(vma),
+		    mods_get_prot_str_for_range(fp, req_pa,
+						MODS_VMA_SIZE(vma)));
+
+		if (io_remap_pfn_range(
+				vma,
+				vma->vm_start,
+				req_pa>>PAGE_SHIFT,
+				MODS_VMA_SIZE(vma),
+				mods_get_prot_for_range(
+					fp,
+					req_pa,
+					MODS_VMA_SIZE(vma),
+					vma->vm_page_prot))) {
+			mods_error_printk("failed to map device memory\n");
+			return -EAGAIN;
+		}
+
+		mods_register_mapping(fp,
+				      NULL,
+				      req_pa,
+				      vma->vm_start,
+				      MODS_VMA_SIZE(vma));
+	}
+	return OK;
+}
+
+/*************************
+ * ESCAPE CALL FUNCTIONS *
+ *************************/
+
+int esc_mods_get_api_version(struct file *pfile, struct MODS_GET_VERSION *p)
+{
+	p->version = MODS_DRIVER_VERSION;
+	return OK;
+}
+
+int esc_mods_get_kernel_version(struct file *pfile, struct MODS_GET_VERSION *p)
+{
+	p->version = MODS_KERNEL_VERSION;
+	return OK;
+}
+
+int esc_mods_set_driver_para(struct file *pfile, struct MODS_SET_PARA *p)
+{
+	int rc = OK;
+	return rc;
+}
+
+int esc_mods_get_screen_info(struct file *pfile, struct MODS_SCREEN_INFO *p)
+{
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) || defined(CONFIG_PPC64)
+	return -EINVAL;
+#else
+	p->orig_video_mode = screen_info.orig_video_mode;
+	p->orig_video_is_vga = screen_info.orig_video_isVGA;
+	p->lfb_width = screen_info.lfb_width;
+	p->lfb_height = screen_info.lfb_height;
+	p->lfb_depth = screen_info.lfb_depth;
+	p->lfb_base = screen_info.lfb_base;
+	p->lfb_size = screen_info.lfb_size;
+	p->lfb_linelength = screen_info.lfb_linelength;
+	return OK;
+#endif
+}
+
+int esc_mods_lock_console(struct file *pfile)
+{
+#if defined(MODS_HAS_CONSOLE_LOCK)
+	console_lock();
+	return OK;
+#else
+	return -EINVAL;
+#endif
+}
+
+int esc_mods_unlock_console(struct file *pfile)
+{
+#if defined(MODS_HAS_CONSOLE_LOCK)
+	console_unlock();
+	return OK;
+#else
+	return -EINVAL;
+#endif
+}
+
+/**************
+ * IO control *
+ **************/
+
+static long mods_krnl_ioctl(struct file  *fp,
+			    unsigned int  cmd,
+			    unsigned long i_arg)
+{
+	int ret = 0;
+	void *arg_copy = 0;
+	void *arg = (void *) i_arg;
+	int arg_size;
+	char buf[64];
+
+	LOG_ENT();
+
+	arg_size = _IOC_SIZE(cmd);
+
+	if (arg_size > (int)sizeof(buf)) {
+		arg_copy = kmalloc(arg_size, GFP_KERNEL | __GFP_NORETRY);
+		if (unlikely(!arg_copy)) {
+			LOG_EXT();
+			return -ENOMEM;
+		}
+	} else if (arg_size > 0)
+		arg_copy = buf;
+
+	if ((arg_size > 0) && copy_from_user(arg_copy, arg, arg_size)) {
+		mods_error_printk("failed to copy ioctl data\n");
+		kfree(arg_copy);
+		LOG_EXT();
+		return -EFAULT;
+	}
+
+#define MODS_IOCTL(code, function, argtype)\
+	({\
+	do {\
+		mods_debug_printk(DEBUG_IOCTL, "ioctl(" #code ")\n");\
+		if (arg_size != sizeof(struct argtype)) {\
+			ret = -EINVAL;\
+			mods_error_printk( \
+				"invalid parameter passed to ioctl " #code \
+				"\n");\
+		} else {\
+			ret = function(fp, (struct argtype *)arg_copy);\
+			if ((ret == OK) && \
+			    copy_to_user(arg, arg_copy, arg_size)) {\
+				ret = -EFAULT;\
+				mods_error_printk( \
+					"copying return value for ioctl " \
+					#code " to user space failed\n");\
+			} \
+		} \
+	} while (0);\
+	})
+
+#define MODS_IOCTL_NORETVAL(code, function, argtype)\
+	({\
+	do {\
+		mods_debug_printk(DEBUG_IOCTL, "ioctl(" #code ")\n");\
+		if (arg_size != sizeof(struct argtype)) {\
+			ret = -EINVAL;\
+			mods_error_printk( \
+				"invalid parameter passed to ioctl " #code \
+				"\n");\
+		} else {\
+			ret = function(fp, (struct argtype *)arg_copy);\
+		} \
+	} while (0);\
+	})
+
+#define MODS_IOCTL_VOID(code, function)\
+	({\
+	do {\
+		mods_debug_printk(DEBUG_IOCTL, "ioctl(" #code ")\n");\
+		if (arg_size != 0) {\
+			ret = -EINVAL;\
+			mods_error_printk( \
+				"invalid parameter passed to ioctl " #code \
+				"\n");\
+		} else {\
+			ret = function(fp);\
+		} \
+	} while (0);\
+	})
+
+	switch (cmd) {
+
+#ifdef CONFIG_PCI
+	case MODS_ESC_FIND_PCI_DEVICE:
+		MODS_IOCTL(MODS_ESC_FIND_PCI_DEVICE,
+			   esc_mods_find_pci_dev, MODS_FIND_PCI_DEVICE);
+		break;
+
+	case MODS_ESC_FIND_PCI_DEVICE_2:
+		MODS_IOCTL(MODS_ESC_FIND_PCI_DEVICE_2,
+			   esc_mods_find_pci_dev_2,
+			   MODS_FIND_PCI_DEVICE_2);
+		break;
+
+	case MODS_ESC_FIND_PCI_CLASS_CODE:
+		MODS_IOCTL(MODS_ESC_FIND_PCI_CLASS_CODE,
+			   esc_mods_find_pci_class_code,
+			   MODS_FIND_PCI_CLASS_CODE);
+		break;
+
+	case MODS_ESC_FIND_PCI_CLASS_CODE_2:
+		MODS_IOCTL(MODS_ESC_FIND_PCI_CLASS_CODE_2,
+			   esc_mods_find_pci_class_code_2,
+			   MODS_FIND_PCI_CLASS_CODE_2);
+		break;
+
+	case MODS_ESC_PCI_GET_BAR_INFO:
+		MODS_IOCTL(MODS_ESC_PCI_GET_BAR_INFO,
+			   esc_mods_pci_get_bar_info,
+			   MODS_PCI_GET_BAR_INFO);
+		break;
+
+	case MODS_ESC_PCI_GET_BAR_INFO_2:
+		MODS_IOCTL(MODS_ESC_PCI_GET_BAR_INFO_2,
+			   esc_mods_pci_get_bar_info_2,
+			   MODS_PCI_GET_BAR_INFO_2);
+		break;
+
+	case MODS_ESC_PCI_GET_IRQ:
+		MODS_IOCTL(MODS_ESC_PCI_GET_IRQ,
+			   esc_mods_pci_get_irq,
+			   MODS_PCI_GET_IRQ);
+		break;
+
+	case MODS_ESC_PCI_GET_IRQ_2:
+		MODS_IOCTL(MODS_ESC_PCI_GET_IRQ_2,
+			   esc_mods_pci_get_irq_2,
+			   MODS_PCI_GET_IRQ_2);
+		break;
+
+	case MODS_ESC_PCI_READ:
+		MODS_IOCTL(MODS_ESC_PCI_READ, esc_mods_pci_read, MODS_PCI_READ);
+		break;
+
+	case MODS_ESC_PCI_READ_2:
+		MODS_IOCTL(MODS_ESC_PCI_READ_2,
+			   esc_mods_pci_read_2, MODS_PCI_READ_2);
+		break;
+
+	case MODS_ESC_PCI_WRITE:
+		MODS_IOCTL_NORETVAL(MODS_ESC_PCI_WRITE,
+				    esc_mods_pci_write, MODS_PCI_WRITE);
+		break;
+
+	case MODS_ESC_PCI_WRITE_2:
+		MODS_IOCTL_NORETVAL(MODS_ESC_PCI_WRITE_2,
+				    esc_mods_pci_write_2,
+				    MODS_PCI_WRITE_2);
+		break;
+
+	case MODS_ESC_PCI_BUS_ADD_DEVICES:
+		MODS_IOCTL_NORETVAL(MODS_ESC_PCI_BUS_ADD_DEVICES,
+				    esc_mods_pci_bus_add_dev,
+				    MODS_PCI_BUS_ADD_DEVICES);
+		break;
+
+	case MODS_ESC_PCI_HOT_RESET:
+		MODS_IOCTL_NORETVAL(MODS_ESC_PCI_HOT_RESET,
+				    esc_mods_pci_hot_reset,
+				    MODS_PCI_HOT_RESET);
+		break;
+
+	case MODS_ESC_PIO_READ:
+		MODS_IOCTL(MODS_ESC_PIO_READ,
+			   esc_mods_pio_read, MODS_PIO_READ);
+		break;
+
+	case MODS_ESC_PIO_WRITE:
+		MODS_IOCTL_NORETVAL(MODS_ESC_PIO_WRITE,
+				    esc_mods_pio_write, MODS_PIO_WRITE);
+		break;
+
+	case MODS_ESC_DEVICE_NUMA_INFO:
+		MODS_IOCTL(MODS_ESC_DEVICE_NUMA_INFO,
+			   esc_mods_device_numa_info,
+			   MODS_DEVICE_NUMA_INFO);
+		break;
+
+	case MODS_ESC_DEVICE_NUMA_INFO_2:
+		MODS_IOCTL(MODS_ESC_DEVICE_NUMA_INFO_2,
+			   esc_mods_device_numa_info_2,
+			   MODS_DEVICE_NUMA_INFO_2);
+		break;
+
+	case MODS_ESC_PCI_MAP_RESOURCE:
+		MODS_IOCTL(MODS_ESC_PCI_MAP_RESOURCE,
+			   esc_mods_pci_map_resource,
+			   MODS_PCI_MAP_RESOURCE);
+		break;
+
+	case MODS_ESC_PCI_UNMAP_RESOURCE:
+		MODS_IOCTL(MODS_ESC_PCI_UNMAP_RESOURCE,
+			   esc_mods_pci_unmap_resource,
+			   MODS_PCI_UNMAP_RESOURCE);
+		break;
+#endif
+
+	case MODS_ESC_ALLOC_PAGES:
+		MODS_IOCTL(MODS_ESC_ALLOC_PAGES,
+			   esc_mods_alloc_pages, MODS_ALLOC_PAGES);
+		break;
+
+	case MODS_ESC_DEVICE_ALLOC_PAGES:
+		MODS_IOCTL(MODS_ESC_DEVICE_ALLOC_PAGES,
+			   esc_mods_device_alloc_pages,
+			   MODS_DEVICE_ALLOC_PAGES);
+		break;
+
+	case MODS_ESC_DEVICE_ALLOC_PAGES_2:
+		MODS_IOCTL(MODS_ESC_DEVICE_ALLOC_PAGES_2,
+			   esc_mods_device_alloc_pages_2,
+			   MODS_DEVICE_ALLOC_PAGES_2);
+		break;
+
+	case MODS_ESC_FREE_PAGES:
+		MODS_IOCTL(MODS_ESC_FREE_PAGES,
+			   esc_mods_free_pages, MODS_FREE_PAGES);
+		break;
+
+	case MODS_ESC_GET_PHYSICAL_ADDRESS:
+		MODS_IOCTL(MODS_ESC_GET_PHYSICAL_ADDRESS,
+			   esc_mods_get_phys_addr,
+			   MODS_GET_PHYSICAL_ADDRESS);
+		break;
+
+	case MODS_ESC_GET_MAPPED_PHYSICAL_ADDRESS:
+		MODS_IOCTL(MODS_ESC_GET_MAPPED_PHYSICAL_ADDRESS,
+			   esc_mods_get_mapped_phys_addr,
+			   MODS_GET_PHYSICAL_ADDRESS);
+		break;
+
+	case MODS_ESC_GET_MAPPED_PHYSICAL_ADDRESS_2:
+		MODS_IOCTL(MODS_ESC_GET_MAPPED_PHYSICAL_ADDRESS_2,
+			   esc_mods_get_mapped_phys_addr_2,
+			   MODS_GET_PHYSICAL_ADDRESS_2);
+		break;
+
+	case MODS_ESC_SET_MEMORY_TYPE:
+		MODS_IOCTL_NORETVAL(MODS_ESC_SET_MEMORY_TYPE,
+				    esc_mods_set_mem_type,
+				    MODS_MEMORY_TYPE);
+		break;
+
+	case MODS_ESC_VIRTUAL_TO_PHYSICAL:
+		MODS_IOCTL(MODS_ESC_VIRTUAL_TO_PHYSICAL,
+			   esc_mods_virtual_to_phys,
+			   MODS_VIRTUAL_TO_PHYSICAL);
+		break;
+
+	case MODS_ESC_PHYSICAL_TO_VIRTUAL:
+		MODS_IOCTL(MODS_ESC_PHYSICAL_TO_VIRTUAL,
+			   esc_mods_phys_to_virtual, MODS_PHYSICAL_TO_VIRTUAL);
+		break;
+
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+	case MODS_ESC_SET_PPC_TCE_BYPASS:
+		MODS_IOCTL(MODS_ESC_SET_PPC_TCE_BYPASS,
+			   esc_mods_set_ppc_tce_bypass,
+			   MODS_SET_PPC_TCE_BYPASS);
+		break;
+
+	case MODS_ESC_GET_ATS_ADDRESS_RANGE:
+		MODS_IOCTL(MODS_ESC_GET_ATS_ADDRESS_RANGE,
+			   esc_mods_get_ats_address_range,
+			   MODS_GET_ATS_ADDRESS_RANGE);
+		break;
+#endif
+
+	case MODS_ESC_DMA_MAP_MEMORY:
+		MODS_IOCTL(MODS_ESC_DMA_MAP_MEMORY,
+			   esc_mods_dma_map_memory,
+			   MODS_DMA_MAP_MEMORY);
+		break;
+
+	case MODS_ESC_DMA_UNMAP_MEMORY:
+		MODS_IOCTL(MODS_ESC_DMA_UNMAP_MEMORY,
+			   esc_mods_dma_unmap_memory,
+			   MODS_DMA_MAP_MEMORY);
+		break;
+
+	case MODS_ESC_IRQ_REGISTER:
+	case MODS_ESC_MSI_REGISTER:
+		ret = -EINVAL;
+		break;
+
+	case MODS_ESC_MAP_INTERRUPT:
+#if defined(MODS_TEGRA) && defined(CONFIG_OF_IRQ) && defined(CONFIG_OF)
+		MODS_IOCTL(MODS_ESC_MAP_INTERRUPT,
+				esc_mods_map_irq, MODS_DT_INFO);
+#endif
+		break;
+
+	case MODS_ESC_REGISTER_IRQ:
+		MODS_IOCTL_NORETVAL(MODS_ESC_REGISTER_IRQ,
+				esc_mods_register_irq, MODS_REGISTER_IRQ);
+		break;
+
+	case MODS_ESC_REGISTER_IRQ_2:
+		MODS_IOCTL_NORETVAL(MODS_ESC_REGISTER_IRQ_2,
+				esc_mods_register_irq_2, MODS_REGISTER_IRQ_2);
+		break;
+
+	case MODS_ESC_REGISTER_IRQ_3:
+		MODS_IOCTL_NORETVAL(MODS_ESC_REGISTER_IRQ_3,
+				esc_mods_register_irq_3, MODS_REGISTER_IRQ_3);
+		break;
+
+	case MODS_ESC_UNREGISTER_IRQ:
+		MODS_IOCTL_NORETVAL(MODS_ESC_UNREGISTER_IRQ,
+				    esc_mods_unregister_irq, MODS_REGISTER_IRQ);
+		break;
+
+	case MODS_ESC_UNREGISTER_IRQ_2:
+		MODS_IOCTL_NORETVAL(MODS_ESC_UNREGISTER_IRQ_2,
+				    esc_mods_unregister_irq_2,
+				    MODS_REGISTER_IRQ_2);
+		break;
+
+	case MODS_ESC_QUERY_IRQ:
+		MODS_IOCTL(MODS_ESC_QUERY_IRQ,
+			   esc_mods_query_irq, MODS_QUERY_IRQ);
+		break;
+
+	case MODS_ESC_QUERY_IRQ_2:
+		MODS_IOCTL(MODS_ESC_QUERY_IRQ_2,
+			   esc_mods_query_irq_2, MODS_QUERY_IRQ_2);
+		break;
+
+	case MODS_ESC_SET_IRQ_MASK:
+		MODS_IOCTL_NORETVAL(MODS_ESC_SET_IRQ_MASK,
+				    esc_mods_set_irq_mask, MODS_SET_IRQ_MASK);
+		break;
+
+	case MODS_ESC_SET_IRQ_MASK_2:
+		MODS_IOCTL_NORETVAL(MODS_ESC_SET_IRQ_MASK_2,
+				    esc_mods_set_irq_mask_2,
+				    MODS_SET_IRQ_MASK_2);
+		break;
+
+	case MODS_ESC_SET_IRQ_MULTIMASK:
+		MODS_IOCTL_NORETVAL(MODS_ESC_SET_IRQ_MULTIMASK,
+				    esc_mods_set_irq_multimask,
+				    MODS_SET_IRQ_MULTIMASK);
+		break;
+
+	case MODS_ESC_IRQ_HANDLED:
+		MODS_IOCTL_NORETVAL(MODS_ESC_IRQ_HANDLED,
+				    esc_mods_irq_handled, MODS_REGISTER_IRQ);
+		break;
+
+	case MODS_ESC_IRQ_HANDLED_2:
+		MODS_IOCTL_NORETVAL(MODS_ESC_IRQ_HANDLED_2,
+				    esc_mods_irq_handled_2,
+				    MODS_REGISTER_IRQ_2);
+		break;
+
+#ifdef CONFIG_ACPI
+	case MODS_ESC_EVAL_ACPI_METHOD:
+		MODS_IOCTL(MODS_ESC_EVAL_ACPI_METHOD,
+			   esc_mods_eval_acpi_method, MODS_EVAL_ACPI_METHOD);
+		break;
+
+	case MODS_ESC_EVAL_DEV_ACPI_METHOD:
+		MODS_IOCTL(MODS_ESC_EVAL_DEV_ACPI_METHOD,
+			   esc_mods_eval_dev_acpi_method,
+			   MODS_EVAL_DEV_ACPI_METHOD);
+		break;
+
+	case MODS_ESC_EVAL_DEV_ACPI_METHOD_2:
+		MODS_IOCTL(MODS_ESC_EVAL_DEV_ACPI_METHOD_2,
+			   esc_mods_eval_dev_acpi_method_2,
+			   MODS_EVAL_DEV_ACPI_METHOD_2);
+		break;
+
+	case MODS_ESC_ACPI_GET_DDC:
+		MODS_IOCTL(MODS_ESC_ACPI_GET_DDC,
+			   esc_mods_acpi_get_ddc, MODS_ACPI_GET_DDC);
+		break;
+
+	case MODS_ESC_ACPI_GET_DDC_2:
+		MODS_IOCTL(MODS_ESC_ACPI_GET_DDC_2,
+			   esc_mods_acpi_get_ddc_2, MODS_ACPI_GET_DDC_2);
+		break;
+
+#else
+	case MODS_ESC_EVAL_ACPI_METHOD:
+		/* fallthrough */
+	case MODS_ESC_EVAL_DEV_ACPI_METHOD:
+		/* fallthrough */
+	case MODS_ESC_EVAL_DEV_ACPI_METHOD_2:
+		/* fallthrough */
+	case MODS_ESC_ACPI_GET_DDC:
+		/* fallthrough */
+	case MODS_ESC_ACPI_GET_DDC_2:
+		/* Silent failure to avoid clogging kernel log */
+		ret = -EINVAL;
+		break;
+#endif
+	case MODS_ESC_GET_API_VERSION:
+		MODS_IOCTL(MODS_ESC_GET_API_VERSION,
+			   esc_mods_get_api_version, MODS_GET_VERSION);
+		break;
+
+	case MODS_ESC_GET_KERNEL_VERSION:
+		MODS_IOCTL(MODS_ESC_GET_KERNEL_VERSION,
+			   esc_mods_get_kernel_version, MODS_GET_VERSION);
+		break;
+
+	case MODS_ESC_SET_DRIVER_PARA:
+		MODS_IOCTL_NORETVAL(MODS_ESC_SET_DRIVER_PARA,
+				    esc_mods_set_driver_para, MODS_SET_PARA);
+		break;
+
+#if defined(MODS_HAS_CLOCK)
+	case MODS_ESC_GET_CLOCK_HANDLE:
+		MODS_IOCTL(MODS_ESC_GET_CLOCK_HANDLE,
+			   esc_mods_get_clock_handle, MODS_GET_CLOCK_HANDLE);
+		break;
+
+	case MODS_ESC_SET_CLOCK_RATE:
+		MODS_IOCTL_NORETVAL(MODS_ESC_SET_CLOCK_RATE,
+				    esc_mods_set_clock_rate, MODS_CLOCK_RATE);
+		break;
+
+	case MODS_ESC_GET_CLOCK_RATE:
+		MODS_IOCTL(MODS_ESC_GET_CLOCK_RATE,
+			   esc_mods_get_clock_rate, MODS_CLOCK_RATE);
+		break;
+
+	case MODS_ESC_GET_CLOCK_MAX_RATE:
+		MODS_IOCTL(MODS_ESC_GET_CLOCK_MAX_RATE,
+			   esc_mods_get_clock_max_rate, MODS_CLOCK_RATE);
+		break;
+
+	case MODS_ESC_SET_CLOCK_MAX_RATE:
+		MODS_IOCTL_NORETVAL(MODS_ESC_SET_CLOCK_MAX_RATE,
+				    esc_mods_set_clock_max_rate,
+				    MODS_CLOCK_RATE);
+		break;
+
+	case MODS_ESC_SET_CLOCK_PARENT:
+		MODS_IOCTL_NORETVAL(MODS_ESC_SET_CLOCK_PARENT,
+				    esc_mods_set_clock_parent,
+				    MODS_CLOCK_PARENT);
+		break;
+
+	case MODS_ESC_GET_CLOCK_PARENT:
+		MODS_IOCTL(MODS_ESC_GET_CLOCK_PARENT,
+			   esc_mods_get_clock_parent, MODS_CLOCK_PARENT);
+		break;
+
+	case MODS_ESC_ENABLE_CLOCK:
+		MODS_IOCTL_NORETVAL(MODS_ESC_ENABLE_CLOCK,
+				    esc_mods_enable_clock, MODS_CLOCK_HANDLE);
+		break;
+
+	case MODS_ESC_DISABLE_CLOCK:
+		MODS_IOCTL_NORETVAL(MODS_ESC_DISABLE_CLOCK,
+				    esc_mods_disable_clock, MODS_CLOCK_HANDLE);
+		break;
+
+	case MODS_ESC_IS_CLOCK_ENABLED:
+		MODS_IOCTL(MODS_ESC_IS_CLOCK_ENABLED,
+			   esc_mods_is_clock_enabled, MODS_CLOCK_ENABLED);
+		break;
+
+	case MODS_ESC_CLOCK_RESET_ASSERT:
+		MODS_IOCTL_NORETVAL(MODS_ESC_CLOCK_RESET_ASSERT,
+				    esc_mods_clock_reset_assert,
+				    MODS_CLOCK_HANDLE);
+		break;
+
+	case MODS_ESC_CLOCK_RESET_DEASSERT:
+		MODS_IOCTL_NORETVAL(MODS_ESC_CLOCK_RESET_DEASSERT,
+				    esc_mods_clock_reset_deassert,
+				    MODS_CLOCK_HANDLE);
+		break;
+#endif
+#if defined(MODS_TEGRA)
+	case MODS_ESC_FLUSH_CPU_CACHE_RANGE:
+		MODS_IOCTL_NORETVAL(MODS_ESC_FLUSH_CPU_CACHE_RANGE,
+				    esc_mods_flush_cpu_cache_range,
+				    MODS_FLUSH_CPU_CACHE_RANGE);
+		break;
+	case MODS_ESC_DMA_ALLOC_COHERENT:
+		MODS_IOCTL(MODS_ESC_DMA_ALLOC_COHERENT,
+			   esc_mods_dma_alloc_coherent,
+			   MODS_DMA_COHERENT_MEM_HANDLE);
+		break;
+	case MODS_ESC_DMA_FREE_COHERENT:
+		MODS_IOCTL(MODS_ESC_DMA_FREE_COHERENT,
+			   esc_mods_dma_free_coherent,
+			   MODS_DMA_COHERENT_MEM_HANDLE);
+		break;
+	case MODS_ESC_DMA_COPY_TO_USER:
+		MODS_IOCTL(MODS_ESC_DMA_COPY_TO_USER,
+			   esc_mods_dma_copy_to_user,
+			   MODS_DMA_COPY_TO_USER);
+		break;
+#if defined(CONFIG_DMA_ENGINE)
+	case MODS_ESC_DMA_REQUEST_HANDLE:
+		MODS_IOCTL(MODS_ESC_DMA_REQUEST_HANDLE,
+			   esc_mods_dma_request_channel,
+			   MODS_DMA_HANDLE);
+		break;
+	case MODS_ESC_DMA_RELEASE_HANDLE:
+		MODS_IOCTL_NORETVAL(MODS_ESC_DMA_RELEASE_HANDLE,
+			   esc_mods_dma_release_channel,
+			   MODS_DMA_HANDLE);
+		break;
+	case MODS_ESC_DMA_ISSUE_PENDING:
+		MODS_IOCTL_NORETVAL(MODS_ESC_DMA_ISSUE_PENDING,
+				    esc_mods_dma_async_issue_pending,
+				    MODS_DMA_HANDLE);
+		break;
+	case MODS_ESC_DMA_SET_CONFIG:
+		MODS_IOCTL_NORETVAL(MODS_ESC_DMA_SET_CONFIG,
+				    esc_mods_dma_set_config,
+				    MODS_DMA_CHANNEL_CONFIG);
+		break;
+	case MODS_ESC_DMA_TX_SUBMIT:
+		MODS_IOCTL(MODS_ESC_DMA_TX_SUBMIT,
+			   esc_mods_dma_submit_request,
+			   MODS_DMA_TX_DESC);
+		break;
+	case MODS_ESC_DMA_TX_WAIT:
+		MODS_IOCTL(MODS_MODS_ESC_DMA_TX_WAIT,
+			   esc_mods_dma_wait,
+			   MODS_DMA_WAIT_DESC);
+		break;
+#endif
+#ifdef CONFIG_TEGRA_DC
+	case MODS_ESC_TEGRA_DC_CONFIG_POSSIBLE:
+		MODS_IOCTL(MODS_ESC_TEGRA_DC_CONFIG_POSSIBLE,
+				   esc_mods_tegra_dc_config_possible,
+				   MODS_TEGRA_DC_CONFIG_POSSIBLE);
+		break;
+	case MODS_ESC_TEGRA_DC_SETUP_SD:
+		MODS_IOCTL_NORETVAL(MODS_ESC_TEGRA_DC_SETUP_SD,
+				    esc_mods_tegra_dc_setup_sd,
+				    MODS_TEGRA_DC_SETUP_SD);
+		break;
+#endif
+#ifdef MODS_HAS_NET
+	case MODS_ESC_NET_FORCE_LINK:
+		MODS_IOCTL(MODS_ESC_NET_FORCE_LINK,
+			   esc_mods_net_force_link, MODS_NET_DEVICE_NAME);
+		break;
+#endif
+#endif
+	case MODS_ESC_MEMORY_BARRIER:
+		MODS_IOCTL_VOID(MODS_ESC_MEMORY_BARRIER,
+				esc_mods_memory_barrier);
+		break;
+
+#ifdef MODS_TEGRA
+	case MODS_ESC_DMABUF_GET_PHYSICAL_ADDRESS:
+		MODS_IOCTL(MODS_ESC_DMABUF_GET_PHYSICAL_ADDRESS,
+			   esc_mods_dmabuf_get_phys_addr,
+			   MODS_DMABUF_GET_PHYSICAL_ADDRESS);
+		break;
+#endif
+#ifdef CONFIG_TEGRA_NVADSP
+	case MODS_ESC_ADSP_LOAD:
+		MODS_IOCTL_VOID(MODS_ESC_ADSP_LOAD,
+				esc_mods_adsp_load);
+		break;
+
+	case MODS_ESC_ADSP_START:
+		MODS_IOCTL_VOID(MODS_ESC_ADSP_START,
+				esc_mods_adsp_start);
+		break;
+
+	case MODS_ESC_ADSP_STOP:
+		MODS_IOCTL_VOID(MODS_ESC_ADSP_STOP,
+				esc_mods_adsp_stop);
+		break;
+
+	case MODS_ESC_ADSP_RUN_APP:
+		MODS_IOCTL_NORETVAL(MODS_ESC_ADSP_RUN_APP,
+				    esc_mods_adsp_run_app,
+				    MODS_ADSP_RUN_APP_INFO);
+		break;
+#endif
+	case MODS_ESC_GET_SCREEN_INFO:
+		MODS_IOCTL(MODS_ESC_GET_SCREEN_INFO,
+			   esc_mods_get_screen_info, MODS_SCREEN_INFO);
+		break;
+	case MODS_ESC_LOCK_CONSOLE:
+		MODS_IOCTL_VOID(MODS_ESC_LOCK_CONSOLE,
+			   esc_mods_lock_console);
+		break;
+	case MODS_ESC_UNLOCK_CONSOLE:
+		MODS_IOCTL_VOID(MODS_ESC_UNLOCK_CONSOLE,
+			   esc_mods_unlock_console);
+		break;
+
+#if defined(MODS_TEGRA)
+	case MODS_ESC_TEGRA_PROD_IS_SUPPORTED:
+		MODS_IOCTL(MODS_ESC_TEGRA_PROD_IS_SUPPORTED,
+			   esc_mods_tegra_prod_is_supported,
+			   MODS_TEGRA_PROD_IS_SUPPORTED);
+		break;
+
+	case MODS_ESC_TEGRA_PROD_SET_PROD_ALL:
+		MODS_IOCTL_NORETVAL(MODS_ESC_TEGRA_PROD_SET_PROD_ALL,
+				    esc_mods_tegra_prod_set_prod_all,
+				    MODS_TEGRA_PROD_SET_TUPLE);
+		break;
+
+	case MODS_ESC_TEGRA_PROD_SET_PROD_BOOT:
+		MODS_IOCTL_NORETVAL(MODS_ESC_TEGRA_PROD_SET_PROD_BOOT,
+				    esc_mods_tegra_prod_set_prod_boot,
+				    MODS_TEGRA_PROD_SET_TUPLE);
+		break;
+
+	case MODS_ESC_TEGRA_PROD_SET_PROD_BY_NAME:
+		MODS_IOCTL_NORETVAL(MODS_ESC_TEGRA_PROD_SET_PROD_BY_NAME,
+				    esc_mods_tegra_prod_set_prod_by_name,
+				    MODS_TEGRA_PROD_SET_TUPLE);
+		break;
+
+	case MODS_ESC_TEGRA_PROD_SET_PROD_EXACT:
+		MODS_IOCTL_NORETVAL(MODS_ESC_TEGRA_PROD_SET_PROD_EXACT,
+				    esc_mods_tegra_prod_set_prod_exact,
+				    MODS_TEGRA_PROD_SET_TUPLE);
+		break;
+
+	case MODS_ESC_TEGRA_PROD_ITERATE_DT:
+		MODS_IOCTL(MODS_ESC_TEGRA_PROD_ITERATE_DT,
+			   esc_mods_tegra_prod_iterate_dt,
+			   MODS_TEGRA_PROD_ITERATOR);
+		break;
+#endif
+
+	default:
+		mods_error_printk("unrecognized ioctl (0x%x)\n", cmd);
+		ret = -EINVAL;
+		break;
+	}
+
+	if (arg_size > (int)sizeof(buf))
+		kfree(arg_copy);
+
+	LOG_EXT();
+	return ret;
+}
diff --git a/drivers/misc/mods/mods_mem.c b/drivers/misc/mods/mods_mem.c
new file mode 100644
index 00000000..430583b5
--- /dev/null
+++ b/drivers/misc/mods/mods_mem.c
@@ -0,0 +1,1808 @@
+/*
+ * mods_mem.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2008-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mods_internal.h"
+
+#include <linux/pagemap.h>
+
+#ifdef CONFIG_BIGPHYS_AREA
+#include <linux/bigphysarea.h>
+#endif
+
+#if defined(MODS_HAS_SET_DMA_MASK)
+#include <linux/dma-mapping.h>
+#include <linux/of.h>
+#endif
+
+static int mods_post_alloc(struct MODS_PHYS_CHUNK *pt,
+			   u64			   phys_addr,
+			   struct MODS_MEM_INFO   *p_mem_info);
+static void mods_pre_free(struct MODS_PHYS_CHUNK *pt,
+			  struct MODS_MEM_INFO	 *p_mem_info);
+
+/****************************
+ * DMA MAP HELPER FUNCTIONS *
+ ****************************/
+
+/* Unmap a page if it was mapped */
+static void mods_dma_unmap_page(struct MODS_DMA_MAP *p_dma_map,
+				struct MODS_MAP_CHUNK *pm)
+{
+	if (!pm->pt)
+		return;
+
+	pci_unmap_page(p_dma_map->dev,
+		       pm->map_addr,
+		       (1U<<pm->pt->order)*PAGE_SIZE,
+		       DMA_BIDIRECTIONAL);
+
+	mods_debug_printk(DEBUG_MEM_DETAILED,
+		"Unmapped map_addr=0x%llx dma_addr=0x%llx on dev %x:%x:%x.%x\n",
+		(unsigned long long)pm->map_addr,
+		(unsigned long long)pm->pt->dma_addr,
+		pci_domain_nr(p_dma_map->dev->bus),
+		p_dma_map->dev->bus->number,
+		PCI_SLOT(p_dma_map->dev->devfn),
+		PCI_FUNC(p_dma_map->dev->devfn));
+}
+
+/* Unmap and delete the specified DMA mapping */
+static int mods_dma_unmap_and_free(struct MODS_MEM_INFO *p_mem_info,
+				   struct MODS_DMA_MAP *p_del_map)
+
+{
+	struct MODS_DMA_MAP *p_dma_map;
+
+	struct list_head  *head;
+	struct list_head  *iter;
+
+	head = p_mem_info->dma_map_list;
+
+	list_for_each(iter, head) {
+		p_dma_map = list_entry(iter, struct MODS_DMA_MAP, list);
+
+		/* find the mapping to delete and remove it from the list */
+		if (p_del_map == p_dma_map) {
+			list_del(iter);
+
+			/* Safeguard check, all mappings should have a *
+			 * non-null device
+			 */
+			if (p_dma_map->dev != NULL) {
+				int i;
+
+				for (i = p_mem_info->max_chunks; i > 0; ) {
+					struct MODS_MAP_CHUNK *pm;
+					--i;
+					pm = &p_dma_map->mapping[i];
+					mods_dma_unmap_page(p_dma_map, pm);
+				}
+			}
+
+			kfree(p_dma_map);
+
+			return OK;
+		}
+	}
+
+	mods_error_printk("failed to unmap and free %p\n",
+			  p_del_map);
+	return -EINVAL;
+}
+
+/* Unmap and delete all DMA mappings on the specified allocation */
+int mods_dma_unmap_all(struct MODS_MEM_INFO *p_mem_info,
+		       struct pci_dev *p_pci_dev)
+{
+	struct list_head *head = p_mem_info->dma_map_list;
+	struct list_head *iter;
+	struct list_head *tmp;
+
+	if (!p_mem_info->dma_map_list)
+		return OK;
+
+	list_for_each_safe(iter, tmp, head) {
+		struct MODS_DMA_MAP *p_dma_map;
+		int ret;
+
+		p_dma_map = list_entry(iter, struct MODS_DMA_MAP, list);
+
+		if (!p_pci_dev || (p_dma_map->dev == p_pci_dev)) {
+			ret = mods_dma_unmap_and_free(p_mem_info, p_dma_map);
+			if (ret || p_pci_dev)
+				return ret;
+		}
+	}
+
+	return OK;
+}
+
+/* DMA map all pages in an allocation */
+static void mods_dma_map_pages(struct MODS_MEM_INFO *p_mem_info,
+			       struct MODS_DMA_MAP *p_dma_map)
+{
+	int i;
+
+	for (i = p_mem_info->max_chunks; i > 0; ) {
+		struct MODS_MAP_CHUNK *pm;
+		struct MODS_PHYS_CHUNK *pt;
+		--i;
+		pm = &p_dma_map->mapping[i];
+		pt = &p_mem_info->pages[i];
+		if (!pt->allocated)
+			continue;
+
+		pm->pt = pt;
+		pm->map_addr = pci_map_page(p_dma_map->dev,
+			pt->p_page,
+			0,
+			(1U << pt->order) * PAGE_SIZE,
+			DMA_BIDIRECTIONAL);
+
+		mods_debug_printk(DEBUG_MEM_DETAILED,
+			"%s : Mapped map_addr=0x%llx, dma_addr=0x%llx on dev %x:%x:%x.%x\n",
+			__func__,
+			(unsigned long long)pm->map_addr,
+			(unsigned long long)pt->dma_addr,
+			pci_domain_nr(p_dma_map->dev->bus),
+			p_dma_map->dev->bus->number,
+			PCI_SLOT(p_dma_map->dev->devfn),
+			PCI_FUNC(p_dma_map->dev->devfn));
+	}
+}
+
+/* Create a DMA map on the specified allocation for the pci device.  Lazy *
+ * initialize the map list structure if one does not yet exist.
+ */
+static int mods_create_dma_map(struct MODS_MEM_INFO *p_mem_info,
+			       struct pci_dev *p_pci_dev)
+{
+	struct MODS_DMA_MAP *p_dma_map;
+	int list_allocated = 0;
+	u32    alloc_size;
+
+	if (!p_mem_info->dma_map_list) {
+		p_mem_info->dma_map_list = kmalloc(sizeof(struct list_head),
+						   GFP_KERNEL | __GFP_NORETRY);
+		if (unlikely(!p_mem_info->dma_map_list))
+			return -ENOMEM;
+		INIT_LIST_HEAD(p_mem_info->dma_map_list);
+		list_allocated = 1;
+	}
+
+	alloc_size = sizeof(*p_dma_map) +
+		     (p_mem_info->max_chunks - 1) *
+		     sizeof(struct MODS_MAP_CHUNK);
+
+	p_dma_map = kmalloc(alloc_size, GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!p_dma_map)) {
+		mods_error_printk("failed to allocate device map data\n");
+		if (list_allocated) {
+			kfree(p_mem_info->dma_map_list);
+			p_mem_info->dma_map_list = NULL;
+			return -ENOMEM;
+		}
+	}
+
+	memset(p_dma_map, 0, alloc_size);
+
+	p_dma_map->dev = p_pci_dev;
+	mods_dma_map_pages(p_mem_info, p_dma_map);
+	list_add(&p_dma_map->list, p_mem_info->dma_map_list);
+
+	return OK;
+}
+
+/* Find the dma mapping chunk for the specified memory.  If p_phys_chunk is *
+ * NULL then the first mapped chunk is returned.
+ */
+static struct MODS_MAP_CHUNK *mods_find_dma_map_chunk(
+					struct MODS_MEM_INFO *p_mem_info,
+					struct pci_dev  *p_pci_dev,
+					struct MODS_PHYS_CHUNK *p_phys_chunk)
+{
+	struct MODS_DMA_MAP *p_dma_map;
+	struct list_head  *head;
+	struct list_head  *iter;
+	int i;
+
+	head = p_mem_info->dma_map_list;
+	if (!head)
+		return NULL;
+
+	list_for_each(iter, head) {
+		p_dma_map = list_entry(iter, struct MODS_DMA_MAP, list);
+		if (p_dma_map->dev == p_pci_dev) {
+
+			if (!p_phys_chunk)
+				return &p_dma_map->mapping[0];
+
+			for (i = p_mem_info->max_chunks; i > 0;) {
+				struct MODS_MAP_CHUNK *pm;
+				--i;
+				pm = &p_dma_map->mapping[i];
+				if (pm->pt == p_phys_chunk)
+					return pm;
+			}
+		}
+	}
+	return NULL;
+}
+
+#if !defined(MODS_TEGRA) || defined(CONFIG_CPA)
+static int mods_set_mem_type(u64 virt_addr, u64 pages, u32 type)
+{
+	if (type == MODS_MEMORY_UNCACHED)
+		return MODS_SET_MEMORY_UC(virt_addr, pages);
+	else if (type == MODS_MEMORY_WRITECOMBINE)
+		return MODS_SET_MEMORY_WC(virt_addr, pages);
+	return 0;
+}
+#endif
+
+static int mods_restore_mem_type(u64 virt_addr,
+				 u64 pages,
+				 u32 type_override)
+{
+	if ((type_override == MODS_MEMORY_UNCACHED) ||
+			(type_override == MODS_MEMORY_WRITECOMBINE)) {
+		return MODS_SET_MEMORY_WB(virt_addr, pages);
+	}
+	return 0;
+}
+
+static void mods_restore_cache(struct MODS_MEM_INFO *p_mem_info)
+{
+	unsigned int i;
+
+	for (i = 0; i < p_mem_info->max_chunks; i++) {
+		struct MODS_PHYS_CHUNK *pt = &p_mem_info->pages[i];
+
+		if (!pt->allocated)
+			break;
+
+		mods_pre_free(pt, p_mem_info);
+	}
+}
+
+static void mods_free_pages(struct MODS_MEM_INFO *p_mem_info)
+{
+	unsigned int i;
+
+	/* release in reverse order */
+	for (i = p_mem_info->max_chunks; i > 0; ) {
+		struct MODS_PHYS_CHUNK *pt;
+		--i;
+		pt = &p_mem_info->pages[i];
+		if (!pt->allocated)
+			continue;
+
+#ifdef CONFIG_BIGPHYS_AREA
+		if (p_mem_info->alloc_type == MODS_ALLOC_TYPE_BIGPHYS_AREA) {
+			bigphysarea_free_pages((void *)
+					       p_mem_info->logical_addr);
+		} else
+#endif
+			__free_pages(pt->p_page, pt->order);
+	}
+}
+
+static gfp_t mods_alloc_flags(struct MODS_MEM_INFO *p_mem_info)
+{
+	gfp_t flags = GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN;
+
+#ifdef MODS_HAS_DEV_TO_NUMA_NODE
+	flags |= __GFP_THISNODE;
+#endif
+
+	if (p_mem_info->alloc_type != MODS_ALLOC_TYPE_NON_CONTIG)
+		flags |= __GFP_COMP;
+	if ((p_mem_info->addr_bits & 0xFF) == 32)
+#ifdef MODS_HAS_DMA32
+		flags |= __GFP_DMA32;
+#else
+		flags |= __GFP_DMA;
+#endif
+	else
+		flags |= __GFP_HIGHMEM;
+
+	return flags;
+}
+
+static int mods_alloc_contig_sys_pages(struct MODS_MEM_INFO *p_mem_info)
+{
+	u64 phys_addr;
+	u64 end_addr  = 0;
+	u32 order     = 0;
+
+	LOG_ENT();
+
+	while ((1U << order) < p_mem_info->num_pages)
+		order++;
+	p_mem_info->pages[0].order = order;
+
+	p_mem_info->pages[0].p_page = alloc_pages_node(
+			p_mem_info->numa_node,
+			mods_alloc_flags(p_mem_info),
+			order);
+
+#ifdef CONFIG_BIGPHYS_AREA
+	if (!p_mem_info->pages[0].p_page) {
+		mods_debug_printk(DEBUG_MEM, "falling back to bigphysarea\n");
+		p_mem_info->logical_addr = (u64)
+			bigphysarea_alloc_pages(1U << order, 0, GFP_KERNEL);
+		p_mem_info->alloc_type = MODS_ALLOC_TYPE_BIGPHYS_AREA;
+	}
+#endif
+
+	if (!p_mem_info->pages[0].p_page &&
+	    p_mem_info->logical_addr == 0) {
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+	p_mem_info->pages[0].allocated = 1;
+
+#ifdef CONFIG_BIGPHYS_AREA
+	if (p_mem_info->alloc_type == MODS_ALLOC_TYPE_BIGPHYS_AREA) {
+		phys_addr = __pa(p_mem_info->logical_addr);
+	} else
+#endif
+		phys_addr = page_to_phys(p_mem_info->pages[0].p_page);
+	if (phys_addr == 0) {
+		mods_error_printk("failed to determine physical address\n");
+		mods_free_pages(p_mem_info);
+		p_mem_info->logical_addr = 0;
+		LOG_EXT();
+		return -ENOMEM;
+	}
+	p_mem_info->pages[0].dma_addr = MODS_PHYS_TO_DMA(phys_addr);
+
+	mods_debug_printk(DEBUG_MEM,
+	    "alloc contig 0x%lx bytes%s, 2^%u pages, %s, phys 0x%llx\n",
+	    (unsigned long)p_mem_info->length,
+	    p_mem_info->alloc_type == MODS_ALLOC_TYPE_BIGPHYS_AREA ?
+		" bigphys" : "",
+	    p_mem_info->pages[0].order,
+	    mods_get_prot_str(p_mem_info->cache_type),
+	    (unsigned long long)p_mem_info->pages[0].dma_addr);
+
+	end_addr = p_mem_info->pages[0].dma_addr + p_mem_info->length;
+	if (((p_mem_info->addr_bits & 0xFF) == 32) &&
+	    (end_addr > 0x100000000ULL)) {
+		mods_error_printk("allocation exceeds 32-bit addressing\n");
+		mods_free_pages(p_mem_info);
+		p_mem_info->logical_addr = 0;
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+	if (mods_post_alloc(p_mem_info->pages, phys_addr, p_mem_info)) {
+		mods_free_pages(p_mem_info);
+		p_mem_info->logical_addr = 0;
+		LOG_EXT();
+		return -EINVAL;
+	}
+	LOG_EXT();
+	return 0;
+}
+
+static int mods_get_max_order_needed(u32 num_pages)
+{
+	int order = 0;
+
+	while (order < 10 && (1U<<(order+1)) <= num_pages)
+		++order;
+	return order;
+}
+
+static int mods_alloc_noncontig_sys_pages(struct MODS_MEM_INFO *p_mem_info)
+{
+	u32 pages_left = p_mem_info->num_pages;
+	u32 num_chunks = 0;
+
+	LOG_ENT();
+
+	memset(p_mem_info->pages, 0,
+	       p_mem_info->max_chunks * sizeof(p_mem_info->pages[0]));
+
+	/* alloc pages */
+	while (pages_left > 0) {
+		u64 phys_addr = 0;
+		int order     = mods_get_max_order_needed(pages_left);
+		struct MODS_PHYS_CHUNK *pt = &p_mem_info->pages[num_chunks];
+
+		for ( ; order >= 0; --order) {
+			pt->p_page = alloc_pages_node(
+					p_mem_info->numa_node,
+					mods_alloc_flags(p_mem_info),
+					(unsigned int)order);
+			if (pt->p_page)
+				break;
+		}
+
+		if (!pt->p_page) {
+			mods_error_printk("out of memory\n");
+			goto failed;
+		}
+		pt->allocated = 1;
+
+		pages_left -= 1U << order;
+		pt->order = (u32)order;
+
+		phys_addr = page_to_phys(pt->p_page);
+		if (phys_addr == 0) {
+			mods_error_printk("phys addr lookup failed\n");
+			goto failed;
+		}
+		pt->dma_addr = MODS_PHYS_TO_DMA(phys_addr);
+		mods_debug_printk(DEBUG_MEM,
+		    "alloc 0x%lx bytes [%u], 2^%u pages, %s, phys 0x%llx\n",
+		    (unsigned long)p_mem_info->length,
+		    (unsigned int)num_chunks,
+		    pt->order,
+		    mods_get_prot_str(p_mem_info->cache_type),
+		    (unsigned long long)pt->dma_addr);
+
+		++num_chunks;
+
+		if (mods_post_alloc(pt, phys_addr, p_mem_info))
+			goto failed;
+	}
+
+	return 0;
+
+failed:
+	mods_restore_cache(p_mem_info);
+	mods_free_pages(p_mem_info);
+	return -ENOMEM;
+}
+
+static int mods_register_alloc(struct file          *fp,
+			       struct MODS_MEM_INFO *p_mem_info)
+{
+	MODS_PRIV private_data = fp->private_data;
+
+	if (unlikely(mutex_lock_interruptible(&private_data->mtx)))
+		return -EINTR;
+	list_add(&p_mem_info->list, private_data->mods_alloc_list);
+	mutex_unlock(&private_data->mtx);
+	return OK;
+}
+
+static int mods_unregister_and_free(struct file          *fp,
+				    struct MODS_MEM_INFO *p_del_mem)
+{
+	struct MODS_MEM_INFO *p_mem_info;
+	MODS_PRIV             private_data = fp->private_data;
+	struct list_head     *head;
+	struct list_head     *iter;
+
+	mods_debug_printk(DEBUG_MEM_DETAILED, "free %p\n", p_del_mem);
+
+	if (unlikely(mutex_lock_interruptible(&private_data->mtx)))
+		return -EINTR;
+
+	head = private_data->mods_alloc_list;
+
+	list_for_each(iter, head) {
+		p_mem_info = list_entry(iter, struct MODS_MEM_INFO, list);
+
+		if (p_del_mem == p_mem_info) {
+			list_del(iter);
+
+			mutex_unlock(&private_data->mtx);
+
+			mods_dma_unmap_all(p_mem_info, NULL);
+			mods_restore_cache(p_mem_info);
+			mods_free_pages(p_mem_info);
+
+			kfree(p_mem_info);
+
+			return OK;
+		}
+	}
+
+	mutex_unlock(&private_data->mtx);
+
+	mods_error_printk("failed to unregister allocation %p\n",
+			  p_del_mem);
+	return -EINVAL;
+}
+
+int mods_unregister_all_alloc(struct file *fp)
+{
+	MODS_PRIV         private_data = fp->private_data;
+	struct list_head *head         = private_data->mods_alloc_list;
+	struct list_head *iter;
+	struct list_head *tmp;
+
+	list_for_each_safe(iter, tmp, head) {
+		struct MODS_MEM_INFO *p_mem_info;
+		int ret;
+
+		p_mem_info = list_entry(iter, struct MODS_MEM_INFO, list);
+		ret = mods_unregister_and_free(fp, p_mem_info);
+		if (ret)
+			return ret;
+	}
+
+	return OK;
+}
+
+/* Returns an offset within an allocation deduced from physical address.
+ * If dma address doesn't belong to the allocation, returns non-zero.
+ */
+int mods_get_alloc_offset(struct MODS_MEM_INFO *p_mem_info,
+			  u64			dma_addr,
+			  u32		       *ret_offs)
+{
+	u32 i;
+	u64 offset = 0;
+
+	for (i = 0; i < p_mem_info->max_chunks; i++) {
+		struct MODS_PHYS_CHUNK *pt = &p_mem_info->pages[i];
+		u64 addr = pt->dma_addr;
+		u32 size = PAGE_SIZE << pt->order;
+
+		if (!pt->allocated)
+			break;
+
+		if (dma_addr >= addr &&
+		    dma_addr <  addr + size) {
+			*ret_offs = dma_addr - addr + offset;
+			return 0;
+		}
+
+		offset += size;
+	}
+
+	/* The physical address doesn't belong to the allocation */
+	return -EINVAL;
+}
+
+struct MODS_MEM_INFO *mods_find_alloc(struct file *fp, u64 phys_addr)
+{
+	MODS_PRIV             private_data = fp->private_data;
+	struct list_head     *plist_head   = private_data->mods_alloc_list;
+	struct list_head     *plist_iter;
+	struct MODS_MEM_INFO *p_mem_info;
+	u32		      offset;
+
+	list_for_each(plist_iter, plist_head) {
+		p_mem_info = list_entry(plist_iter,
+					struct MODS_MEM_INFO,
+					list);
+		if (!mods_get_alloc_offset(p_mem_info, phys_addr, &offset))
+			return p_mem_info;
+	}
+
+	/* The physical address doesn't belong to any allocation */
+	return NULL;
+}
+
+static u32 mods_estimate_max_chunks(u32 num_pages)
+{
+	u32 max_chunks = 0;
+	u32 bit_scan;
+
+	/* Count each contiguous block <=256KB */
+	for (bit_scan = num_pages; bit_scan && max_chunks < 6; bit_scan >>= 1)
+		++max_chunks;
+
+	/* Count remaining contiguous blocks >256KB */
+	max_chunks += bit_scan;
+
+	/* 4x slack for medium memory fragmentation */
+	max_chunks <<= 2;
+
+	/* No sense to allocate more chunks than pages */
+	if (max_chunks > num_pages)
+		max_chunks = num_pages;
+
+	/* Now, if memory is heavily fragmented, we are screwed */
+
+	return max_chunks;
+}
+
+static struct MODS_PHYS_CHUNK *mods_find_phys_chunk(
+					struct MODS_MEM_INFO *p_mem_info,
+					u32 offset,
+					u32 *chunk_offset)
+{
+	struct MODS_PHYS_CHUNK	*pt = NULL;
+	u32			pages_left;
+	u32			page_offs;
+	u32			i;
+
+	if (!p_mem_info)
+		return NULL;
+
+	pages_left = offset >> PAGE_SHIFT;
+	page_offs  = offset & (~PAGE_MASK);
+
+	for (i = 0; i < p_mem_info->max_chunks; i++) {
+		u32 num_pages;
+
+		pt = &p_mem_info->pages[i];
+		if (!pt->allocated)
+			break;
+
+		num_pages = 1U << pt->order;
+		if (pages_left < num_pages)
+			break;
+		pages_left -= num_pages;
+		pt = NULL;
+	}
+
+	*chunk_offset = (pages_left << PAGE_SHIFT) + page_offs;
+	return pt;
+}
+
+/************************
+ * ESCAPE CALL FUNCTONS *
+ ************************/
+
+int esc_mods_device_alloc_pages_2(struct file	*fp,
+				  struct MODS_DEVICE_ALLOC_PAGES_2 *p)
+{
+	struct MODS_MEM_INFO *p_mem_info = NULL;
+	u32    num_pages;
+	u32    alloc_size;
+	u32    max_chunks;
+	int    ret = OK;
+	struct pci_dev *dev = NULL;
+
+	LOG_ENT();
+
+	if (!p->num_bytes) {
+		mods_error_printk("zero bytes requested\n");
+		ret = -EINVAL;
+		goto failed;
+	}
+
+	mods_debug_printk(
+		DEBUG_MEM_DETAILED,
+		"alloc 0x%x bytes %s %s\n",
+		p->num_bytes,
+		p->contiguous ? "contiguous" : "noncontiguous",
+		mods_get_prot_str(p->attrib));
+
+	switch (p->attrib) {
+	case MODS_MEMORY_CACHED:
+#if !defined(CONFIG_PPC64)
+	case MODS_MEMORY_UNCACHED:
+	case MODS_MEMORY_WRITECOMBINE:
+#endif
+		break;
+
+	default:
+		mods_error_printk("invalid memory type: %u\n",
+				  p->attrib);
+		ret = -ENOMEM;
+		goto failed;
+	}
+
+	num_pages = (p->num_bytes >> PAGE_SHIFT) +
+		    ((p->num_bytes & ~PAGE_MASK) ? 1 : 0);
+	if (p->contiguous)
+		max_chunks = 1;
+	else
+		max_chunks = mods_estimate_max_chunks(num_pages);
+	alloc_size = sizeof(*p_mem_info) +
+		     (max_chunks - 1) * sizeof(struct MODS_PHYS_CHUNK);
+
+	p_mem_info = kmalloc(alloc_size, GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!p_mem_info)) {
+		mods_error_printk("failed to allocate auxiliary 0x%x bytes\n",
+				  alloc_size);
+		ret = -ENOMEM;
+		goto failed;
+	}
+
+	p_mem_info->max_chunks   = max_chunks;
+	p_mem_info->alloc_type	 = p->contiguous
+		? MODS_ALLOC_TYPE_CONTIG : MODS_ALLOC_TYPE_NON_CONTIG;
+	p_mem_info->cache_type	 = p->attrib;
+	p_mem_info->length	 = p->num_bytes;
+	p_mem_info->logical_addr = 0;
+	p_mem_info->addr_bits	 = p->address_bits;
+	p_mem_info->num_pages	 = num_pages;
+	p_mem_info->numa_node    = numa_node_id();
+	p_mem_info->dma_map_list = NULL;
+	p_mem_info->dev          = NULL;
+
+	if (p->pci_device.bus || p->pci_device.device) {
+		unsigned int devfn = PCI_DEVFN(p->pci_device.device,
+					       p->pci_device.function);
+		dev = MODS_PCI_GET_SLOT(p->pci_device.domain,
+					p->pci_device.bus,
+					devfn);
+		if (!dev) {
+			ret = -EINVAL;
+			goto failed;
+		}
+
+		p_mem_info->dev = dev;
+#if defined(MODS_HAS_DEV_TO_NUMA_NODE)
+		p_mem_info->numa_node = dev_to_node(&dev->dev);
+#endif
+		mods_debug_printk(DEBUG_MEM_DETAILED,
+			"affinity %x:%x.%x node %d\n",
+			p->pci_device.bus,
+			p->pci_device.device,
+			p->pci_device.function,
+			p_mem_info->numa_node);
+	}
+
+	p->memory_handle = 0;
+
+	if (p->contiguous) {
+		if (mods_alloc_contig_sys_pages(p_mem_info)) {
+			mods_error_printk(
+				"failed to alloc 0x%x contiguous bytes\n",
+				p_mem_info->length);
+			ret = -ENOMEM;
+			goto failed;
+		}
+	} else {
+		if (mods_alloc_noncontig_sys_pages(p_mem_info)) {
+			mods_error_printk(
+			    "failed to alloc 0x%x noncontiguous bytes\n",
+			    p_mem_info->length);
+			ret = -ENOMEM;
+			goto failed;
+		}
+	}
+
+#if defined(CONFIG_PPC64)
+	/* Backwards compatibility : this is normally done through
+	 * MODS_ESC_DMA_MAP_MEMORY
+	 */
+	if (dev && mods_create_dma_map(p_mem_info, dev)) {
+		mods_error_printk("failed to create dma map\n");
+		ret = -ENOMEM;
+		goto failed;
+	}
+#endif
+
+	p->memory_handle = (u64)(size_t)p_mem_info;
+
+	mods_debug_printk(DEBUG_MEM_DETAILED, "alloc %p\n", p_mem_info);
+
+	ret = mods_register_alloc(fp, p_mem_info);
+	LOG_EXT();
+	return ret;
+failed:
+	if (p_mem_info) {
+		kfree(p_mem_info->dma_map_list);
+		kfree(p_mem_info);
+	}
+	LOG_EXT();
+	return ret;
+}
+
+int esc_mods_device_alloc_pages(struct file                    *fp,
+				struct MODS_DEVICE_ALLOC_PAGES *p)
+{
+	int retval;
+	struct MODS_DEVICE_ALLOC_PAGES_2 dev_alloc_pages = {0};
+
+	LOG_ENT();
+
+	dev_alloc_pages.num_bytes		= p->num_bytes;
+	dev_alloc_pages.contiguous		= p->contiguous;
+	dev_alloc_pages.address_bits		= p->address_bits;
+	dev_alloc_pages.attrib			= p->attrib;
+	dev_alloc_pages.pci_device.domain	= 0;
+	dev_alloc_pages.pci_device.bus		= p->pci_device.bus;
+	dev_alloc_pages.pci_device.device	= p->pci_device.device;
+	dev_alloc_pages.pci_device.function	= p->pci_device.function;
+
+	retval = esc_mods_device_alloc_pages_2(fp, &dev_alloc_pages);
+	if (!retval)
+		p->memory_handle = dev_alloc_pages.memory_handle;
+
+	LOG_EXT();
+	return retval;
+}
+
+int esc_mods_alloc_pages(struct file *fp, struct MODS_ALLOC_PAGES *p)
+{
+	int retval;
+	struct MODS_DEVICE_ALLOC_PAGES_2 dev_alloc_pages;
+
+	LOG_ENT();
+
+	dev_alloc_pages.num_bytes	    = p->num_bytes;
+	dev_alloc_pages.contiguous	    = p->contiguous;
+	dev_alloc_pages.address_bits	    = p->address_bits;
+	dev_alloc_pages.attrib		    = p->attrib;
+	dev_alloc_pages.pci_device.domain   = 0;
+	dev_alloc_pages.pci_device.bus	    = 0;
+	dev_alloc_pages.pci_device.device   = 0;
+	dev_alloc_pages.pci_device.function = 0;
+
+	retval = esc_mods_device_alloc_pages_2(fp, &dev_alloc_pages);
+	if (!retval)
+		p->memory_handle = dev_alloc_pages.memory_handle;
+
+	LOG_EXT();
+	return retval;
+}
+
+int esc_mods_free_pages(struct file *fp, struct MODS_FREE_PAGES *p)
+{
+	int ret;
+
+	LOG_ENT();
+
+	ret = mods_unregister_and_free(fp,
+	    (struct MODS_MEM_INFO *)(size_t)p->memory_handle);
+
+	LOG_EXT();
+
+	return ret;
+}
+
+int esc_mods_set_mem_type(struct file *fp, struct MODS_MEMORY_TYPE *p)
+{
+	struct MODS_MEM_INFO *p_mem_info;
+	MODS_PRIV             private_data = fp->private_data;
+
+	LOG_ENT();
+
+	switch (p->type) {
+	case MODS_MEMORY_CACHED:
+	case MODS_MEMORY_UNCACHED:
+	case MODS_MEMORY_WRITECOMBINE:
+		break;
+
+	default:
+		mods_error_printk("unsupported memory type: %u\n", p->type);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	if (unlikely(mutex_lock_interruptible(&private_data->mtx))) {
+		LOG_EXT();
+		return -EINTR;
+	}
+
+	p_mem_info = mods_find_alloc(fp, p->physical_address);
+	if (p_mem_info) {
+		mutex_unlock(&private_data->mtx);
+		mods_error_printk("cannot set mem type on phys addr 0x%llx\n",
+				  p->physical_address);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	private_data->mem_type.dma_addr = p->physical_address;
+	private_data->mem_type.size     = p->size;
+	private_data->mem_type.type     = p->type;
+
+	mutex_unlock(&private_data->mtx);
+
+	LOG_EXT();
+	return OK;
+}
+
+int esc_mods_get_phys_addr(struct file *fp, struct MODS_GET_PHYSICAL_ADDRESS *p)
+{
+	struct MODS_MEM_INFO	*p_mem_info;
+	struct MODS_PHYS_CHUNK	*pt = NULL;
+	u32			chunk_offset;
+
+	LOG_ENT();
+
+	p_mem_info = (struct MODS_MEM_INFO *)(size_t)p->memory_handle;
+	pt = mods_find_phys_chunk(p_mem_info, p->offset, &chunk_offset);
+
+	if (!pt || !pt->allocated) {
+		mods_error_printk("invalid offset requested\n");
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	p->physical_address = pt->dma_addr + chunk_offset;
+	mods_debug_printk(DEBUG_MEM_DETAILED,
+		"get phys: %p+0x%x -> 0x%llx\n",
+		p_mem_info, p->offset, p->physical_address);
+	LOG_EXT();
+	return 0;
+}
+
+int esc_mods_get_mapped_phys_addr(struct file *fp,
+				  struct MODS_GET_PHYSICAL_ADDRESS *p)
+{
+	int retval;
+	struct MODS_GET_PHYSICAL_ADDRESS_2 get_mapped_phys_addr_2;
+	struct MODS_MEM_INFO *p_mem_info;
+
+	LOG_ENT();
+
+	memset(&get_mapped_phys_addr_2, 0,
+	       sizeof(struct MODS_GET_PHYSICAL_ADDRESS_2));
+	get_mapped_phys_addr_2.memory_handle	     = p->memory_handle;
+	get_mapped_phys_addr_2.offset	             = p->offset;
+	p_mem_info = (struct MODS_MEM_INFO *)(size_t)p->memory_handle;
+	if (p_mem_info->dev) {
+		get_mapped_phys_addr_2.pci_device.domain   =
+			pci_domain_nr(p_mem_info->dev->bus);
+		get_mapped_phys_addr_2.pci_device.bus	   =
+			p_mem_info->dev->bus->number;
+		get_mapped_phys_addr_2.pci_device.device   =
+			PCI_SLOT(p_mem_info->dev->devfn);
+		get_mapped_phys_addr_2.pci_device.function =
+			PCI_FUNC(p_mem_info->dev->devfn);
+	}
+
+	retval = esc_mods_get_mapped_phys_addr_2(fp, &get_mapped_phys_addr_2);
+	if (!retval)
+		p->physical_address = get_mapped_phys_addr_2.physical_address;
+
+	LOG_EXT();
+	return retval;
+}
+
+int esc_mods_get_mapped_phys_addr_2(struct file *fp,
+				  struct MODS_GET_PHYSICAL_ADDRESS_2 *p)
+{
+	struct pci_dev         *dev = NULL;
+	struct MODS_MEM_INFO   *p_mem_info;
+	struct MODS_PHYS_CHUNK *pt;
+	struct MODS_MAP_CHUNK  *pm;
+	u32			chunk_offset;
+
+	p_mem_info = (struct MODS_MEM_INFO *)(size_t)p->memory_handle;
+	pt = mods_find_phys_chunk(p_mem_info, p->offset, &chunk_offset);
+
+	if (!pt || !pt->allocated) {
+		mods_error_printk("invalid offset requested\n");
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	if (p->pci_device.bus || p->pci_device.device) {
+		unsigned int devfn = PCI_DEVFN(p->pci_device.device,
+					       p->pci_device.function);
+		dev = MODS_PCI_GET_SLOT(p->pci_device.domain,
+					p->pci_device.bus,
+					devfn);
+	}
+
+	if (!dev) {
+		mods_debug_printk(DEBUG_MEM_DETAILED,
+				  "get mapped phys: %p+0x%x -> 0x%llx\n",
+				  p_mem_info, p->offset, p->physical_address);
+		p->physical_address = pt->dma_addr + chunk_offset;
+		LOG_EXT();
+		return OK;
+	}
+
+	pm = mods_find_dma_map_chunk(p_mem_info, dev, pt);
+	if (!pm) {
+		mods_error_printk("invalid device mapping requested\n");
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	p->physical_address = pm->map_addr + chunk_offset;
+	mods_debug_printk(DEBUG_MEM_DETAILED,
+		"get mapped phys: %p+0x%x -> 0x%llx\n",
+		p_mem_info, p->offset, p->physical_address);
+	LOG_EXT();
+	return 0;
+}
+
+int esc_mods_virtual_to_phys(struct file *fp,
+			     struct MODS_VIRTUAL_TO_PHYSICAL *p)
+{
+	struct MODS_GET_PHYSICAL_ADDRESS get_phys_addr;
+	MODS_PRIV         private_data = fp->private_data;
+	struct list_head *head;
+	struct list_head *iter;
+
+	LOG_ENT();
+
+	if (unlikely(mutex_lock_interruptible(&private_data->mtx))) {
+		LOG_EXT();
+		return -EINTR;
+	}
+
+	head = private_data->mods_mapping_list;
+
+	list_for_each(iter, head) {
+		struct SYS_MAP_MEMORY *p_map_mem;
+		u64		       begin, end;
+		u32                    phys_offs;
+
+		p_map_mem = list_entry(iter, struct SYS_MAP_MEMORY, list);
+
+		begin = p_map_mem->virtual_addr;
+		end   = p_map_mem->virtual_addr + p_map_mem->mapping_length;
+
+		if (p->virtual_address >= begin && p->virtual_address < end) {
+
+			u32 virt_offs = p->virtual_address - begin;
+			int ret;
+
+			/* device memory mapping */
+			if (!p_map_mem->p_mem_info) {
+				p->physical_address = p_map_mem->dma_addr
+						      + virt_offs;
+				mutex_unlock(&private_data->mtx);
+
+				mods_debug_printk(DEBUG_MEM_DETAILED,
+				    "get phys: map %p virt 0x%llx -> 0x%llx\n",
+				    p_map_mem, p->virtual_address,
+				    p->physical_address);
+
+				LOG_EXT();
+				return OK;
+			}
+
+			if (mods_get_alloc_offset(p_map_mem->p_mem_info,
+						  p_map_mem->dma_addr,
+						  &phys_offs) != OK)
+				break;
+
+			get_phys_addr.memory_handle =
+				(u64)(size_t)p_map_mem->p_mem_info;
+			get_phys_addr.offset = virt_offs + phys_offs;
+
+			mutex_unlock(&private_data->mtx);
+
+			ret = esc_mods_get_phys_addr(fp, &get_phys_addr);
+			if (ret != OK)
+				return ret;
+
+			p->physical_address = get_phys_addr.physical_address;
+
+			mods_debug_printk(DEBUG_MEM_DETAILED,
+			    "get phys: map %p virt 0x%llx -> 0x%llx\n",
+			    p_map_mem, p->virtual_address, p->physical_address);
+
+			LOG_EXT();
+			return OK;
+		}
+	}
+
+	mutex_unlock(&private_data->mtx);
+
+	mods_error_printk("invalid virtual address\n");
+	return -EINVAL;
+}
+
+int esc_mods_phys_to_virtual(struct file *fp,
+			     struct MODS_PHYSICAL_TO_VIRTUAL *p)
+{
+	struct SYS_MAP_MEMORY *p_map_mem;
+	MODS_PRIV              private_data = fp->private_data;
+	struct list_head      *head;
+	struct list_head      *iter;
+	u32	               offset;
+	u32	               map_offset;
+
+	LOG_ENT();
+
+	if (unlikely(mutex_lock_interruptible(&private_data->mtx))) {
+		LOG_EXT();
+		return -EINTR;
+	}
+
+	head = private_data->mods_mapping_list;
+
+	list_for_each(iter, head) {
+		p_map_mem = list_entry(iter, struct SYS_MAP_MEMORY, list);
+
+		/* device memory mapping */
+		if (!p_map_mem->p_mem_info) {
+			u64 end = p_map_mem->dma_addr
+				+ p_map_mem->mapping_length;
+			if (p->physical_address <  p_map_mem->dma_addr ||
+			    p->physical_address >= end)
+				continue;
+
+			offset = p->physical_address
+				 - p_map_mem->dma_addr;
+			p->virtual_address = p_map_mem->virtual_addr
+					     + offset;
+			mutex_unlock(&private_data->mtx);
+
+			mods_debug_printk(DEBUG_MEM_DETAILED,
+			    "get virt: map %p phys 0x%llx -> 0x%llx\n",
+			    p_map_mem, p->physical_address, p->virtual_address);
+
+			LOG_EXT();
+			return OK;
+		}
+
+		/* offset from the beginning of the allocation */
+		if (mods_get_alloc_offset(p_map_mem->p_mem_info,
+					  p->physical_address,
+					  &offset))
+			continue;
+
+		/* offset from the beginning of the mapping */
+		if (mods_get_alloc_offset(p_map_mem->p_mem_info,
+					  p_map_mem->dma_addr,
+					  &map_offset))
+			continue;
+
+		if ((offset >= map_offset) &&
+		    (offset <  map_offset + p_map_mem->mapping_length)) {
+			p->virtual_address = p_map_mem->virtual_addr
+					   + offset - map_offset;
+
+			mutex_unlock(&private_data->mtx);
+			mods_debug_printk(DEBUG_MEM_DETAILED,
+			    "get virt: map %p phys 0x%llx -> 0x%llx\n",
+			    p_map_mem, p->physical_address, p->virtual_address);
+
+			LOG_EXT();
+			return OK;
+		}
+	}
+	mutex_unlock(&private_data->mtx);
+	mods_error_printk("phys addr 0x%llx is not mapped\n",
+			  p->physical_address);
+	return -EINVAL;
+}
+
+int esc_mods_memory_barrier(struct file *fp)
+{
+#if defined(CONFIG_ARM)
+	/* Full memory barrier on ARMv7 */
+	wmb();
+	return OK;
+#else
+	return -EINVAL;
+#endif
+}
+
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+static struct PPC_TCE_BYPASS *mods_find_ppc_tce_bypass(struct file *fp,
+						       struct pci_dev *dev)
+{
+	MODS_PRIV              private_data = fp->private_data;
+	struct list_head      *plist_head;
+	struct list_head      *plist_iter;
+	struct PPC_TCE_BYPASS *p_ppc_tce_bypass;
+
+	plist_head = private_data->mods_ppc_tce_bypass_list;
+
+	list_for_each(plist_iter, plist_head) {
+		p_ppc_tce_bypass = list_entry(plist_iter,
+					  struct PPC_TCE_BYPASS,
+					  list);
+		if (dev == p_ppc_tce_bypass->dev)
+			return p_ppc_tce_bypass;
+	}
+
+	/* The device has never had its dma mask changed */
+	return NULL;
+}
+
+static int mods_register_ppc_tce_bypass(struct file    *fp,
+				    struct pci_dev *dev,
+				    u64 original_mask)
+{
+	MODS_PRIV              private_data = fp->private_data;
+	struct PPC_TCE_BYPASS *p_ppc_tce_bypass;
+
+	/* only register the first time in order to restore the true actual dma
+	 * mask
+	 */
+	if (mods_find_ppc_tce_bypass(fp, dev) != NULL) {
+		mods_debug_printk(DEBUG_MEM,
+		    "TCE bypass already registered on dev %x:%x:%x.%x\n",
+		    pci_domain_nr(dev->bus),
+		    dev->bus->number,
+		    PCI_SLOT(dev->devfn),
+		    PCI_FUNC(dev->devfn));
+		return OK;
+	}
+
+	if (unlikely(mutex_lock_interruptible(&private_data->mtx)))
+		return -EINTR;
+
+	p_ppc_tce_bypass = kmalloc(sizeof(struct PPC_TCE_BYPASS),
+				   GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!p_ppc_tce_bypass)) {
+		mods_error_printk("failed to allocate TCE bypass struct\n");
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+	p_ppc_tce_bypass->dev = dev;
+	p_ppc_tce_bypass->dma_mask = original_mask;
+
+	list_add(&p_ppc_tce_bypass->list,
+		 private_data->mods_ppc_tce_bypass_list);
+
+	mods_debug_printk(DEBUG_MEM,
+			"Registered TCE bypass on dev %x:%x:%x.%x\n",
+			pci_domain_nr(dev->bus),
+			dev->bus->number,
+			PCI_SLOT(dev->devfn),
+			PCI_FUNC(dev->devfn));
+	mutex_unlock(&private_data->mtx);
+	return OK;
+}
+
+static int mods_unregister_ppc_tce_bypass(struct file *fp, struct pci_dev *dev)
+{
+	struct PPC_TCE_BYPASS *p_ppc_tce_bypass;
+	MODS_PRIV              private_data = fp->private_data;
+	struct list_head      *head = private_data->mods_ppc_tce_bypass_list;
+	struct list_head      *iter;
+
+	LOG_ENT();
+
+	if (unlikely(mutex_lock_interruptible(&private_data->mtx)))
+		return -EINTR;
+
+	list_for_each(iter, head) {
+		p_ppc_tce_bypass =
+			list_entry(iter, struct PPC_TCE_BYPASS, list);
+
+		if (p_ppc_tce_bypass->dev == dev) {
+			int ret = 0;
+
+			list_del(iter);
+
+			mutex_unlock(&private_data->mtx);
+
+			ret = pci_set_dma_mask(p_ppc_tce_bypass->dev,
+					       p_ppc_tce_bypass->dma_mask);
+			dma_set_coherent_mask(&p_ppc_tce_bypass->dev->dev,
+					      dev->dma_mask);
+			mods_debug_printk(DEBUG_MEM,
+			    "Restored dma_mask on dev %x:%x:%x.%x to %llx\n",
+			    pci_domain_nr(p_ppc_tce_bypass->dev->bus),
+			    p_ppc_tce_bypass->dev->bus->number,
+			    PCI_SLOT(p_ppc_tce_bypass->dev->devfn),
+			    PCI_FUNC(p_ppc_tce_bypass->dev->devfn),
+			    p_ppc_tce_bypass->dma_mask);
+
+			kfree(p_ppc_tce_bypass);
+
+			LOG_EXT();
+			return ret;
+		}
+	}
+
+	mutex_unlock(&private_data->mtx);
+
+	mods_error_printk(
+		"Failed to unregister TCE bypass on dev %x:%x:%x.%x\n",
+		pci_domain_nr(dev->bus),
+		dev->bus->number,
+		PCI_SLOT(dev->devfn),
+		PCI_FUNC(dev->devfn));
+	LOG_EXT();
+
+	return -EINVAL;
+
+}
+
+int mods_unregister_all_ppc_tce_bypass(struct file *fp)
+{
+	MODS_PRIV         private_data = fp->private_data;
+	struct list_head *head         = private_data->mods_ppc_tce_bypass_list;
+	struct list_head *iter;
+	struct list_head *tmp;
+
+	list_for_each_safe(iter, tmp, head) {
+		struct PPC_TCE_BYPASS *p_ppc_tce_bypass;
+		int ret;
+
+		p_ppc_tce_bypass =
+			list_entry(iter, struct PPC_TCE_BYPASS, list);
+		ret = mods_unregister_ppc_tce_bypass(fp, p_ppc_tce_bypass->dev);
+		if (ret)
+			return ret;
+	}
+
+	return OK;
+}
+
+int esc_mods_set_ppc_tce_bypass(struct file *fp,
+			    struct MODS_SET_PPC_TCE_BYPASS *p)
+{
+	int ret = OK;
+	dma_addr_t dma_addr;
+	unsigned int devfn = PCI_DEVFN(p->pci_device.device,
+				       p->pci_device.function);
+	struct pci_dev *dev = MODS_PCI_GET_SLOT(p->pci_device.domain,
+						p->pci_device.bus,
+						devfn);
+	u64 original_dma_mask;
+	u32 bypass_mode = p->mode;
+	u32 cur_bypass_mode = MODS_PPC_TCE_BYPASS_OFF;
+	u64 dma_mask = DMA_BIT_MASK(64);
+
+	LOG_ENT();
+
+	if (!dev) {
+		mods_error_printk(
+		 "PCI device not found %x:%x:%x.%x\n",
+		 p->pci_device.domain,
+		 p->pci_device.bus,
+		 p->pci_device.device,
+		 p->pci_device.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	original_dma_mask = dev->dma_mask;
+
+	if (bypass_mode == MODS_PPC_TCE_BYPASS_DEFAULT)
+		bypass_mode = mods_get_ppc_tce_bypass();
+
+	if (original_dma_mask == DMA_BIT_MASK(64))
+		cur_bypass_mode = MODS_PPC_TCE_BYPASS_ON;
+
+
+	/*
+	 * Linux on IBM POWER8 offers 2 different DMA set-ups, sometimes
+	 * referred to as "windows".
+	 *
+	 * The "default window" provides a 2GB region of PCI address space
+	 * located below the 32-bit line. The IOMMU is used to provide a
+	 * "rich" mapping--any page in system memory can be mapped at an
+	 * arbitrary address within this window. The mappings are dynamic
+	 * and pass in and out of being as pci_map*()/pci_unmap*() calls
+	 * are made.
+	 *
+	 * Dynamic DMA Windows (sometimes "Huge DDW", also PPC TCE Bypass "ON")
+	 * provides a linear
+	 * mapping of the system's entire physical address space at some
+	 * fixed offset above the 59-bit line. IOMMU is still used, and
+	 * pci_map*()/pci_unmap*() are still required, but mappings are
+	 * static. They're effectively set up in advance, and any given
+	 * system page will always map to the same PCI bus address. I.e.
+	 *   physical 0x00000000xxxxxxxx => PCI 0x08000000xxxxxxxx
+	 *
+	 * Linux on POWER8 will only provide the DDW-style full linear
+	 * mapping when the driver claims support for 64-bit DMA addressing
+	 * (a pre-requisite because the PCI addresses used in this case will
+	 * be near the top of the 64-bit range). The linear mapping
+	 * is not available in all system configurations.
+	 *
+	 * Detect whether the linear mapping is present by claiming
+	 * 64-bit support and then mapping physical page 0. For historical
+	 * reasons, Linux on POWER8 will never map a page to PCI address 0x0.
+	 * In the "default window" case page 0 will be mapped to some
+	 * non-zero address below the 32-bit line.  In the
+	 * DDW/linear-mapping case, it will be mapped to address 0 plus
+	 * some high-order offset.
+	 *
+	 * If the linear mapping is present and sane then return the offset
+	 * as the starting address for all DMA mappings.
+	 */
+	if ((bypass_mode != MODS_PPC_TCE_BYPASS_DEFAULT) &&
+	    (cur_bypass_mode != bypass_mode)) {
+		/* Set DMA mask appropriately here */
+		if (bypass_mode == MODS_PPC_TCE_BYPASS_OFF)
+			dma_mask = p->device_dma_mask;
+
+		if (pci_set_dma_mask(dev, dma_mask) != 0) {
+			mods_error_printk(
+			  "pci_set_dma_mask failed on dev %x:%x:%x.%x\n",
+			  p->pci_device.domain,
+			  p->pci_device.bus,
+			  p->pci_device.device,
+			  p->pci_device.function);
+			LOG_EXT();
+			return -EINVAL;
+		}
+	}
+
+	dma_addr = pci_map_single(dev, NULL, 1, DMA_BIDIRECTIONAL);
+	if (pci_dma_mapping_error(dev, dma_addr)) {
+		pci_set_dma_mask(dev, original_dma_mask);
+		mods_error_printk(
+			"pci_map_single failed on dev %x:%x:%x.%x\n",
+			p->pci_device.domain,
+			p->pci_device.bus,
+			p->pci_device.device,
+			p->pci_device.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+	pci_unmap_single(dev, dma_addr, 1, DMA_BIDIRECTIONAL);
+
+	if (bypass_mode == MODS_PPC_TCE_BYPASS_ON) {
+		bool bBypassFailed = false;
+
+		/*
+		 * From IBM: "For IODA2, native DMA bypass or KVM TCE-based
+		 * implementation of full 64-bit DMA support will establish a
+		 * window in address-space with the high 14 bits being constant
+		 * and the bottom up-to-50 bits varying with the mapping."
+		 *
+		 * Unfortunately, we don't have any good interfaces or
+		 * definitions from the kernel to get information about the DMA
+		 * offset assigned by OS. However, we have been told that the
+		 * offset will be defined by the top 14 bits of the address,
+		 * and bits 40-49 will not vary for any DMA mappings until 1TB
+		 * of system memory is surpassed; this limitation is essential
+		 * for us to function properly since our current GPUs only
+		 * support 40 physical address bits. We are in a fragile place
+		 * where we need to tell the OS that we're capable of 64-bit
+		 * addressing, while relying on the assumption that the top 24
+		 * bits will not vary in this case.
+		 *
+		 * The way we try to compute the window, then, is mask the trial
+		 * mapping against the DMA capabilities of the device. That way,
+		 * devices with greater addressing capabilities will only take
+		 * the bits it needs to define the window.
+		 */
+		if ((dma_addr & DMA_BIT_MASK(32)) != 0) {
+			/*
+			 * Huge DDW not available - page 0 mapped to non-zero
+			 * address below the 32-bit line.
+			 */
+			mods_warning_printk(
+			    "Enabling PPC TCE bypass mode failed due to platform on device %x:%x:%x.%x\n",
+			    p->pci_device.domain,
+			    p->pci_device.bus,
+			    p->pci_device.device,
+			    p->pci_device.function);
+			bBypassFailed = true;
+		} else if ((dma_addr & original_dma_mask) != 0) {
+			/*
+			 * The physical window straddles our addressing limit
+			 * boundary, e.g., for an adapter that can address up to
+			 * 1TB, the window crosses the 40-bit limit so that the
+			 * lower end of the range has different bits 63:40 than
+			 * the higher end of the range. We can only handle a
+			 * single, static value for bits 63:40, so we must fall
+			 * back here.
+			 */
+			mods_warning_printk(
+			    "Enabling PPC TCE bypass mode failed due to memory size on device %x:%x:%x.%x\n",
+			    p->pci_device.domain,
+			    p->pci_device.bus,
+			    p->pci_device.device,
+			    p->pci_device.function);
+			bBypassFailed = true;
+		}
+		if (bBypassFailed)
+			pci_set_dma_mask(dev, original_dma_mask);
+	}
+
+	mods_debug_printk(DEBUG_MEM,
+	    "%s ppc tce bypass on device %x:%x:%x.%x with dma mask 0x%llx\n",
+	    (dev->dma_mask == DMA_BIT_MASK(64)) ? "Enabled" : "Disabled",
+	    p->pci_device.domain,
+	    p->pci_device.bus,
+	    p->pci_device.device,
+	    p->pci_device.function,
+	    dev->dma_mask);
+
+	p->dma_base_address = dma_addr & ~(p->device_dma_mask);
+
+	mods_debug_printk(DEBUG_MEM,
+		"dma base address 0x%0llx on device %x:%x:%x.%x\n",
+		p->dma_base_address,
+		p->pci_device.domain,
+		p->pci_device.bus,
+		p->pci_device.device,
+		p->pci_device.function);
+
+	/* Update the coherent mask to match */
+	dma_set_coherent_mask(&dev->dev, dev->dma_mask);
+
+	if (original_dma_mask != dev->dma_mask)
+		ret = mods_register_ppc_tce_bypass(fp, dev, original_dma_mask);
+
+	LOG_EXT();
+	return ret;
+}
+#endif
+
+int esc_mods_dma_map_memory(struct file *fp,
+			    struct MODS_DMA_MAP_MEMORY *p)
+{
+	struct MODS_MEM_INFO	*p_mem_info;
+	struct MODS_MAP_CHUNK   *p_map_chunk;
+	struct pci_dev          *p_pci_dev;
+	unsigned int devfn = PCI_DEVFN(p->pci_device.device,
+				       p->pci_device.function);
+
+	LOG_ENT();
+
+	p_mem_info = (struct MODS_MEM_INFO *)(size_t)p->memory_handle;
+	p_pci_dev = MODS_PCI_GET_SLOT(p->pci_device.domain,
+				p->pci_device.bus,
+				devfn);
+
+	if (!p_pci_dev) {
+		mods_error_printk("pci device not found\n");
+		return -EINVAL;
+	}
+
+	p_map_chunk = mods_find_dma_map_chunk(p_mem_info, p_pci_dev, NULL);
+	if (p_map_chunk) {
+		mods_debug_printk(DEBUG_MEM_DETAILED,
+			"memory %p already mapped to dev %x:%x:%x.%x\n",
+			p_mem_info,
+			p->pci_device.domain,
+				p->pci_device.bus,
+				p->pci_device.device,
+				p->pci_device.function);
+		LOG_EXT();
+		return 0;
+	}
+
+	if (mods_create_dma_map(p_mem_info, p_pci_dev)) {
+		mods_error_printk("failed to create dma map\n");
+		return -ENOMEM;
+	}
+
+	LOG_EXT();
+	return 0;
+}
+
+int esc_mods_dma_unmap_memory(struct file *fp,
+			      struct MODS_DMA_MAP_MEMORY *p)
+{
+	struct MODS_MEM_INFO	*p_mem_info;
+	struct pci_dev          *p_pci_dev;
+	unsigned int devfn = PCI_DEVFN(p->pci_device.device,
+				       p->pci_device.function);
+	int ret;
+
+	LOG_ENT();
+
+	p_mem_info = (struct MODS_MEM_INFO *)(size_t)p->memory_handle;
+	p_pci_dev = MODS_PCI_GET_SLOT(p->pci_device.domain,
+				p->pci_device.bus,
+				devfn);
+
+	if (!p_pci_dev) {
+		mods_error_printk("pci device not found\n");
+		return -EINVAL;
+	}
+
+	ret = mods_dma_unmap_all(p_mem_info, p_pci_dev);
+	LOG_EXT();
+	return ret;
+}
+
+#ifdef MODS_TEGRA
+
+static void clear_contiguous_cache
+(
+	u64 virt_start,
+	u64 virt_end,
+	u64 phys_start,
+	u64 phys_end
+)
+{
+	/* We are expecting virt_end and phys_end to point to the first address
+	 * of the next range
+	 */
+	u32 size = virt_end - virt_start;
+
+	WARN_ON(size != phys_end - phys_start);
+	size += (~virt_end + 1) & (~PAGE_MASK);  /* Align up to page boundary */
+
+	mods_debug_printk(DEBUG_MEM_DETAILED,
+	    "clear cache virt 0x%llx phys 0x%llx size 0x%x\n",
+	    virt_start, phys_start, size);
+
+#ifdef CONFIG_ARM64
+	/* Flush L1 cache */
+	__flush_dcache_area((void *)(size_t)(virt_start), size);
+#else
+	/* Flush L1 cache */
+	__cpuc_flush_dcache_area((void *)(size_t)(virt_start), size);
+
+	/* Now flush L2 cache. */
+	outer_flush_range(phys_start, phys_end);
+#endif
+}
+
+static void clear_entry_cache_mappings
+(
+	struct SYS_MAP_MEMORY *p_map_mem,
+	u64		       virt_offs,
+	u64		       virt_offs_end
+)
+{
+	struct MODS_MEM_INFO *p_mem_info = p_map_mem->p_mem_info;
+	u64	     cur_vo = p_map_mem->virtual_addr;
+	unsigned int i;
+
+	if (!p_mem_info)
+		return;
+
+	if (p_mem_info->cache_type != MODS_MEMORY_CACHED)
+		return;
+
+	for (i = 0; i < p_mem_info->max_chunks; i++) {
+		struct MODS_PHYS_CHUNK *pt = &p_mem_info->pages[i];
+		u64 cur_vo_end = cur_vo + (PAGE_SIZE << pt->order);
+
+		if (!pt->allocated)
+			break;
+
+		if (virt_offs_end <= cur_vo)
+			break;
+
+		if (virt_offs < cur_vo_end) {
+			u64 clear_vo	 = virt_offs;
+			u64 clear_vo_end = virt_offs_end;
+			u64 clear_pa;
+			u64 clear_pa_end;
+
+			if (clear_vo < cur_vo)
+				clear_vo = cur_vo;
+
+			if (clear_vo_end > cur_vo_end)
+				clear_vo_end = cur_vo_end;
+
+			clear_pa = MODS_DMA_TO_PHYS(pt->dma_addr);
+			if (clear_vo > cur_vo)
+				clear_pa += clear_vo - cur_vo;
+
+			clear_pa_end = clear_pa + (clear_vo_end - clear_vo);
+
+			mods_debug_printk(DEBUG_MEM_DETAILED,
+			    "clear cache %p [%u]\n", p_mem_info, i);
+
+			clear_contiguous_cache(clear_vo,
+					       clear_vo_end,
+					       clear_pa,
+					       clear_pa_end);
+		}
+
+		cur_vo = cur_vo_end;
+	}
+}
+
+int esc_mods_flush_cpu_cache_range(struct file *fp,
+				   struct MODS_FLUSH_CPU_CACHE_RANGE *p)
+{
+	MODS_PRIV         private_data = fp->private_data;
+	struct list_head *head;
+	struct list_head *iter;
+
+	if (irqs_disabled() || in_interrupt() ||
+	    p->virt_addr_start > p->virt_addr_end ||
+	    p->flags == MODS_INVALIDATE_CPU_CACHE) {
+
+		mods_debug_printk(DEBUG_MEM_DETAILED, "cannot clear cache\n");
+		return -EINVAL;
+	}
+
+	if (unlikely(mutex_lock_interruptible(&private_data->mtx))) {
+		LOG_EXT();
+		return -EINTR;
+	}
+
+	head = private_data->mods_mapping_list;
+
+	list_for_each(iter, head) {
+		struct SYS_MAP_MEMORY *p_map_mem
+			= list_entry(iter, struct SYS_MAP_MEMORY, list);
+
+		u64 mapped_va = p_map_mem->virtual_addr;
+
+		/* Note: mapping end points to the first address of next range*/
+		u64 mapping_end = mapped_va + p_map_mem->mapping_length;
+
+		int start_on_page = p->virt_addr_start >= mapped_va
+				    && p->virt_addr_start < mapping_end;
+		int start_before_page = p->virt_addr_start < mapped_va;
+		int end_on_page = p->virt_addr_end >= mapped_va
+				  && p->virt_addr_end < mapping_end;
+		int end_after_page = p->virt_addr_end >= mapping_end;
+		u64 virt_start = p->virt_addr_start;
+
+		/* Kernel expects end to point to the first address of next
+		 * range
+		 */
+		u64 virt_end = p->virt_addr_end + 1;
+
+		if ((start_on_page || start_before_page)
+			&& (end_on_page || end_after_page)) {
+
+			if (!start_on_page)
+				virt_start = p_map_mem->virtual_addr;
+			if (!end_on_page)
+				virt_end = mapping_end;
+			clear_entry_cache_mappings(p_map_mem,
+						   virt_start,
+						   virt_end);
+		}
+	}
+	mutex_unlock(&private_data->mtx);
+	return OK;
+}
+
+#endif
+
+static int mods_post_alloc(struct MODS_PHYS_CHUNK *pt,
+			   u64			   phys_addr,
+			   struct MODS_MEM_INFO   *p_mem_info)
+{
+	u32 num_pages = 1U << pt->order;
+	u32 i;
+
+	for (i = 0; i < num_pages; i++) {
+		u64 ptr = 0;
+		int ret = 0;
+#ifdef CONFIG_BIGPHYS_AREA
+		if (p_mem_info->alloc_type == MODS_ALLOC_TYPE_BIGPHYS_AREA) {
+			ptr = p_mem_info->logical_addr + (i << PAGE_SHIFT);
+		} else
+#endif
+			ptr = (u64)(size_t)kmap(pt->p_page + i);
+		if (!ptr) {
+			mods_error_printk("kmap failed\n");
+			return -EINVAL;
+		}
+#if defined(MODS_TEGRA) && !defined(CONFIG_CPA)
+		clear_contiguous_cache(ptr,
+				ptr + PAGE_SIZE,
+				phys_addr + (i << PAGE_SHIFT),
+				phys_addr + ((i+1) << PAGE_SHIFT));
+#else
+		ret = mods_set_mem_type(ptr, 1, p_mem_info->cache_type);
+#endif
+#ifdef CONFIG_BIGPHYS_AREA
+		if (p_mem_info->alloc_type != MODS_ALLOC_TYPE_BIGPHYS_AREA)
+#endif
+			kunmap(pt->p_page + i);
+		if (ret) {
+			mods_error_printk("set cache type failed\n");
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+static void mods_pre_free(struct MODS_PHYS_CHUNK *pt,
+			  struct MODS_MEM_INFO	 *p_mem_info)
+{
+	u32 num_pages = 1U << pt->order;
+	u32 i;
+
+	for (i = 0; i < num_pages; i++) {
+		u64 ptr = 0;
+#ifdef CONFIG_BIGPHYS_AREA
+		if (p_mem_info->alloc_type == MODS_ALLOC_TYPE_BIGPHYS_AREA)
+			ptr = p_mem_info->logical_addr + (i << PAGE_SHIFT);
+		else
+#endif
+			ptr = (u64)(size_t)kmap(pt->p_page + i);
+		if (ptr)
+			mods_restore_mem_type(ptr, 1, p_mem_info->cache_type);
+#ifdef CONFIG_BIGPHYS_AREA
+		if (p_mem_info->alloc_type != MODS_ALLOC_TYPE_BIGPHYS_AREA)
+#endif
+			kunmap(pt->p_page + i);
+	}
+}
diff --git a/drivers/misc/mods/mods_netdevice.c b/drivers/misc/mods/mods_netdevice.c
new file mode 100644
index 00000000..8c7c7300
--- /dev/null
+++ b/drivers/misc/mods/mods_netdevice.c
@@ -0,0 +1,46 @@
+/*
+ * mods_net.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mods.h"
+#include "mods_internal.h"
+#include <linux/netdevice.h>
+
+int esc_mods_net_force_link(struct file *pfile, struct MODS_NET_DEVICE_NAME *p)
+{
+	struct net_device *ndev;
+
+	if (!p ||
+	    (strnlen(p->device_name, MAX_NET_DEVICE_NAME_LENGTH) == 0) ||
+	    (!memchr(p->device_name, '\0', MAX_NET_DEVICE_NAME_LENGTH))) {
+		mods_error_printk("invalid device name\n");
+		return -EINVAL;
+	}
+
+	for_each_netdev(&init_net, ndev)
+		if (!strcmp(ndev->name, p->device_name)) {
+			netif_carrier_on(ndev);
+			mods_info_printk("carrier forced on: %s\n",
+					 p->device_name);
+			return OK;
+		}
+
+	mods_error_printk("failed to find network device %s\n",
+			  p->device_name);
+	return -EINVAL;
+}
diff --git a/drivers/misc/mods/mods_pci.c b/drivers/misc/mods/mods_pci.c
new file mode 100644
index 00000000..f9eed9a0
--- /dev/null
+++ b/drivers/misc/mods/mods_pci.c
@@ -0,0 +1,925 @@
+/*
+ * mods_pci.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2008-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mods_internal.h"
+
+#include <linux/io.h>
+#include <linux/fs.h>
+
+/************************
+ * PCI HELPER FUNCTIONS *
+ ************************/
+
+static int mods_free_pci_res_map(struct file *fp,
+				 struct MODS_PCI_RES_MAP_INFO *p_del_map)
+{
+#if defined(MODS_HAS_PCI_MAP_RESOURCE)
+	struct MODS_PCI_RES_MAP_INFO *p_res_map;
+	MODS_PRIV                     private_data = fp->private_data;
+	struct list_head             *head;
+	struct list_head             *iter;
+
+	mods_debug_printk(DEBUG_PCICFG,
+			  "free pci resource map %p\n",
+			  p_del_map);
+
+	if (unlikely(mutex_lock_interruptible(&private_data->mtx)))
+		return -EINTR;
+
+	head = private_data->mods_pci_res_map_list;
+
+	list_for_each(iter, head) {
+		p_res_map =
+			list_entry(iter, struct MODS_PCI_RES_MAP_INFO, list);
+
+		if (p_del_map == p_res_map) {
+			list_del(iter);
+
+			mutex_unlock(&private_data->mtx);
+
+			pci_unmap_resource(p_res_map->dev,
+					   p_res_map->va,
+					   p_res_map->page_count * PAGE_SIZE,
+					   PCI_DMA_BIDIRECTIONAL);
+			mods_debug_printk(DEBUG_PCICFG,
+					  "unmapped pci resource at 0x%llx from %u:%u:%u.%u\n",
+					  p_res_map->va,
+					  pci_domain_nr(p_res_map->dev->bus),
+					  p_res_map->dev->bus->number,
+					  PCI_SLOT(p_res_map->dev->devfn),
+					  PCI_FUNC(p_res_map->dev->devfn));
+			kfree(p_res_map);
+			return OK;
+		}
+	}
+
+	mutex_unlock(&private_data->mtx);
+
+	mods_error_printk("failed to unregister pci resource mapping %p\n",
+			  p_del_map);
+	return -EINVAL;
+#else
+	return OK;
+#endif
+}
+
+int mods_unregister_all_pci_res_mappings(struct file *fp)
+{
+	MODS_PRIV         private_data = fp->private_data;
+	struct list_head *head         = private_data->mods_pci_res_map_list;
+	struct list_head *iter;
+	struct list_head *tmp;
+
+	list_for_each_safe(iter, tmp, head) {
+		struct MODS_PCI_RES_MAP_INFO *p_pci_res_map_info;
+		int ret;
+
+		p_pci_res_map_info =
+			list_entry(iter, struct MODS_PCI_RES_MAP_INFO, list);
+		ret = mods_free_pci_res_map(fp, p_pci_res_map_info);
+		if (ret)
+			return ret;
+	}
+
+	return OK;
+}
+
+/************************
+ * PCI ESCAPE FUNCTIONS *
+ ************************/
+
+int esc_mods_find_pci_dev_2(struct file *pfile,
+			    struct MODS_FIND_PCI_DEVICE_2 *p)
+{
+	struct pci_dev *dev;
+	int index = 0;
+
+	mods_debug_printk(DEBUG_PCICFG,
+			  "find pci dev %04x:%04x, index %d\n",
+			  (int) p->vendor_id,
+			  (int) p->device_id,
+			  (int) p->index);
+
+	dev = pci_get_device(p->vendor_id, p->device_id, NULL);
+
+	while (dev) {
+		if (index == p->index) {
+			p->pci_device.domain	= pci_domain_nr(dev->bus);
+			p->pci_device.bus	= dev->bus->number;
+			p->pci_device.device	= PCI_SLOT(dev->devfn);
+			p->pci_device.function	= PCI_FUNC(dev->devfn);
+			return OK;
+		}
+		dev = pci_get_device(p->vendor_id, p->device_id, dev);
+		index++;
+	}
+
+	return -EINVAL;
+}
+
+int esc_mods_find_pci_dev(struct file *pfile,
+			  struct MODS_FIND_PCI_DEVICE *p)
+{
+	struct pci_dev *dev;
+	int index = 0;
+
+	mods_debug_printk(DEBUG_PCICFG,
+			  "find pci dev %04x:%04x, index %d\n",
+			  (int) p->vendor_id,
+			  (int) p->device_id,
+			  (int) p->index);
+
+	dev = pci_get_device(p->vendor_id, p->device_id, NULL);
+
+	while (dev) {
+		if (index == p->index && pci_domain_nr(dev->bus) == 0) {
+			p->bus_number		= dev->bus->number;
+			p->device_number	= PCI_SLOT(dev->devfn);
+			p->function_number	= PCI_FUNC(dev->devfn);
+			return OK;
+		}
+		/* Only return devices in the first domain, but don't assume
+		 * that they're the first devices in the list
+		 */
+		if (pci_domain_nr(dev->bus) == 0)
+			index++;
+		dev = pci_get_device(p->vendor_id, p->device_id, dev);
+	}
+
+	return -EINVAL;
+}
+
+int esc_mods_find_pci_class_code_2(struct file *pfile,
+				   struct MODS_FIND_PCI_CLASS_CODE_2 *p)
+{
+	struct pci_dev *dev;
+	int index = 0;
+
+	mods_debug_printk(DEBUG_PCICFG, "find pci class code %04x, index %d\n",
+			  (int) p->class_code, (int) p->index);
+
+	dev = pci_get_class(p->class_code, NULL);
+
+	while (dev) {
+		if (index == p->index) {
+			p->pci_device.domain	= pci_domain_nr(dev->bus);
+			p->pci_device.bus	= dev->bus->number;
+			p->pci_device.device	= PCI_SLOT(dev->devfn);
+			p->pci_device.function	= PCI_FUNC(dev->devfn);
+			return OK;
+		}
+		dev = pci_get_class(p->class_code, dev);
+		index++;
+	}
+
+	return -EINVAL;
+}
+
+int esc_mods_find_pci_class_code(struct file *pfile,
+				 struct MODS_FIND_PCI_CLASS_CODE *p)
+{
+	struct pci_dev *dev;
+	int index = 0;
+
+	mods_debug_printk(DEBUG_PCICFG, "find pci class code %04x, index %d\n",
+			  (int) p->class_code, (int) p->index);
+
+	dev = pci_get_class(p->class_code, NULL);
+
+	while (dev) {
+		if (index == p->index && pci_domain_nr(dev->bus) == 0) {
+			p->bus_number		= dev->bus->number;
+			p->device_number	= PCI_SLOT(dev->devfn);
+			p->function_number	= PCI_FUNC(dev->devfn);
+			return OK;
+		}
+		/* Only return devices in the first domain, but don't assume
+		 * that they're the first devices in the list
+		 */
+		if (pci_domain_nr(dev->bus) == 0)
+			index++;
+		dev = pci_get_class(p->class_code, dev);
+	}
+
+	return -EINVAL;
+}
+
+int esc_mods_pci_get_bar_info_2(struct file *pfile,
+				struct MODS_PCI_GET_BAR_INFO_2 *p)
+{
+	struct pci_dev *dev;
+	unsigned int devfn, bar_resource_offset, i;
+#if !defined(MODS_HAS_IORESOURCE_MEM_64)
+	__u32 temp;
+#endif
+
+	devfn = PCI_DEVFN(p->pci_device.device, p->pci_device.function);
+	dev = MODS_PCI_GET_SLOT(p->pci_device.domain, p->pci_device.bus, devfn);
+
+	if (dev == NULL)
+		return -EINVAL;
+
+	mods_debug_printk(DEBUG_PCICFG,
+			  "pci get bar info %04x:%x:%02x:%x, bar index %d\n",
+			  (int) p->pci_device.domain,
+			  (int) p->pci_device.bus, (int) p->pci_device.device,
+			  (int) p->pci_device.function, (int) p->bar_index);
+
+	bar_resource_offset = 0;
+	for (i = 0; i < p->bar_index; i++) {
+#if defined(MODS_HAS_IORESOURCE_MEM_64)
+		if (pci_resource_flags(dev, bar_resource_offset)
+		    & IORESOURCE_MEM_64) {
+#else
+		pci_read_config_dword(dev,
+				      (PCI_BASE_ADDRESS_0
+				       + (bar_resource_offset * 4)),
+				      &temp);
+		if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+#endif
+			bar_resource_offset += 2;
+		} else {
+			bar_resource_offset += 1;
+		}
+	}
+	p->base_address = pci_resource_start(dev, bar_resource_offset);
+	p->bar_size	= pci_resource_len(dev, bar_resource_offset);
+
+	return OK;
+}
+
+int esc_mods_pci_get_bar_info(struct file *pfile,
+			      struct MODS_PCI_GET_BAR_INFO *p)
+{
+	int retval;
+	struct MODS_PCI_GET_BAR_INFO_2 get_bar_info = { {0} };
+
+	get_bar_info.pci_device.domain		= 0;
+	get_bar_info.pci_device.bus		= p->pci_device.bus;
+	get_bar_info.pci_device.device		= p->pci_device.device;
+	get_bar_info.pci_device.function	= p->pci_device.function;
+	get_bar_info.bar_index			= p->bar_index;
+
+	retval = esc_mods_pci_get_bar_info_2(pfile, &get_bar_info);
+	if (retval)
+		return retval;
+
+	p->base_address	= get_bar_info.base_address;
+	p->bar_size	= get_bar_info.bar_size;
+	return OK;
+}
+
+int esc_mods_pci_get_irq_2(struct file *pfile,
+			   struct MODS_PCI_GET_IRQ_2 *p)
+{
+	struct pci_dev *dev;
+	unsigned int devfn;
+
+	devfn = PCI_DEVFN(p->pci_device.device, p->pci_device.function);
+	dev = MODS_PCI_GET_SLOT(p->pci_device.domain, p->pci_device.bus, devfn);
+
+	if (dev == NULL)
+		return -EINVAL;
+
+	mods_debug_printk(DEBUG_PCICFG,
+			  "pci get irq %04x:%x:%02x:%x\n",
+			  (int) p->pci_device.domain,
+			  (int) p->pci_device.bus, (int) p->pci_device.device,
+			  (int) p->pci_device.function);
+
+	p->irq = dev->irq;
+
+	return OK;
+}
+
+int esc_mods_pci_get_irq(struct file *pfile,
+			 struct MODS_PCI_GET_IRQ *p)
+{
+	int retval;
+	struct MODS_PCI_GET_IRQ_2 get_irq = { {0} };
+
+	get_irq.pci_device.domain	= 0;
+	get_irq.pci_device.bus		= p->pci_device.bus;
+	get_irq.pci_device.device	= p->pci_device.device;
+	get_irq.pci_device.function	= p->pci_device.function;
+
+	retval = esc_mods_pci_get_irq_2(pfile, &get_irq);
+	if (retval)
+		return retval;
+
+	p->irq = get_irq.irq;
+	return OK;
+}
+
+int esc_mods_pci_read_2(struct file *pfile, struct MODS_PCI_READ_2 *p)
+{
+	struct pci_dev *dev;
+	unsigned int devfn;
+
+	devfn = PCI_DEVFN(p->pci_device.device, p->pci_device.function);
+	dev = MODS_PCI_GET_SLOT(p->pci_device.domain, p->pci_device.bus, devfn);
+
+	if (dev == NULL)
+		return -EINVAL;
+
+	mods_debug_printk(DEBUG_PCICFG,
+			  "pci read %04x:%x:%02x.%x, addr 0x%04x, size %d\n",
+			  (int) p->pci_device.domain,
+			  (int) p->pci_device.bus, (int) p->pci_device.device,
+			  (int) p->pci_device.function, (int) p->address,
+			  (int) p->data_size);
+
+	p->data = 0;
+	switch (p->data_size) {
+	case 1: {
+		    u8 value;
+
+		    pci_read_config_byte(dev, p->address, &value);
+		    p->data = value;
+		}
+		break;
+	case 2: {
+		    u16 value;
+
+		    pci_read_config_word(dev, p->address, &value);
+		    p->data = value;
+		}
+		break;
+	case 4:
+		pci_read_config_dword(dev, p->address, (u32 *) &p->data);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return OK;
+}
+
+int esc_mods_pci_read(struct file *pfile, struct MODS_PCI_READ *p)
+{
+	int retval;
+	struct MODS_PCI_READ_2 pci_read = { {0} };
+
+	pci_read.pci_device.domain	= 0;
+	pci_read.pci_device.bus		= p->bus_number;
+	pci_read.pci_device.device	= p->device_number;
+	pci_read.pci_device.function	= p->function_number;
+	pci_read.address		= p->address;
+	pci_read.data_size		= p->data_size;
+
+	retval = esc_mods_pci_read_2(pfile, &pci_read);
+	if (retval)
+		return retval;
+
+	p->data = pci_read.data;
+	return OK;
+}
+
+int esc_mods_pci_write_2(struct file *pfile, struct MODS_PCI_WRITE_2 *p)
+{
+	struct pci_dev *dev;
+	unsigned int devfn;
+
+	mods_debug_printk(DEBUG_PCICFG,
+		"pci write %04x:%x:%02x.%x, addr 0x%04x, size %d, data 0x%x\n",
+		(int) p->pci_device.domain,
+		(int) p->pci_device.bus, (int) p->pci_device.device,
+		(int) p->pci_device.function,
+		(int) p->address, (int) p->data_size, (int) p->data);
+
+	devfn = PCI_DEVFN(p->pci_device.device, p->pci_device.function);
+	dev = MODS_PCI_GET_SLOT(p->pci_device.domain, p->pci_device.bus, devfn);
+
+	if (dev == NULL) {
+		mods_error_printk(
+		  "pci write to %04x:%x:%02x.%x, addr 0x%04x, size %d failed\n",
+		    (unsigned int)p->pci_device.domain,
+		    (unsigned int)p->pci_device.bus,
+		    (unsigned int)p->pci_device.device,
+		    (unsigned int)p->pci_device.function,
+		    (unsigned int)p->address,
+		    (int)p->data_size);
+		return -EINVAL;
+	}
+
+	switch (p->data_size) {
+	case 1:
+		pci_write_config_byte(dev, p->address, p->data);
+		break;
+	case 2:
+		pci_write_config_word(dev, p->address, p->data);
+		break;
+	case 4:
+		pci_write_config_dword(dev, p->address, p->data);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return OK;
+}
+
+int esc_mods_pci_write(struct file *pfile,
+		       struct MODS_PCI_WRITE *p)
+{
+	struct MODS_PCI_WRITE_2 pci_write = { {0} };
+
+	pci_write.pci_device.domain	= 0;
+	pci_write.pci_device.bus	= p->bus_number;
+	pci_write.pci_device.device	= p->device_number;
+	pci_write.pci_device.function	= p->function_number;
+	pci_write.address		= p->address;
+	pci_write.data			= p->data;
+	pci_write.data_size		= p->data_size;
+
+	return esc_mods_pci_write_2(pfile, &pci_write);
+}
+
+int esc_mods_pci_bus_add_dev(struct file *pfile,
+			     struct MODS_PCI_BUS_ADD_DEVICES *scan)
+{
+#if defined(CONFIG_PCI)
+	mods_info_printk("scanning pci bus %x\n", scan->bus);
+
+	/* initiate a PCI bus scan to find hotplugged PCI devices in domain 0 */
+	pci_scan_child_bus(pci_find_bus(0, scan->bus));
+
+	/* add newly found devices */
+	pci_bus_add_devices(pci_find_bus(0, scan->bus));
+
+	return OK;
+#else
+	return -EINVAL;
+#endif
+}
+
+int esc_mods_pci_hot_reset(struct file *pfile,
+			   struct MODS_PCI_HOT_RESET *p)
+{
+#if defined(CONFIG_PPC64)
+	struct pci_dev *dev;
+	unsigned int devfn;
+	int retval;
+
+	mods_debug_printk(DEBUG_PCICFG,
+			  "pci_hot_reset %04x:%x:%02x.%x\n",
+			  (int) p->pci_device.domain,
+			  (int) p->pci_device.bus,
+			  (int) p->pci_device.device,
+			  (int) p->pci_device.function);
+
+	devfn = PCI_DEVFN(p->pci_device.device, p->pci_device.function);
+	dev = MODS_PCI_GET_SLOT(p->pci_device.domain, p->pci_device.bus, devfn);
+
+	if (dev == NULL) {
+		mods_error_printk(
+		    "pci_hot_reset cannot find pci device %04x:%x:%02x.%x\n",
+		    (unsigned int)p->pci_device.domain,
+		    (unsigned int)p->pci_device.bus,
+		    (unsigned int)p->pci_device.device,
+		    (unsigned int)p->pci_device.function);
+		return -EINVAL;
+	}
+
+	retval = pci_set_pcie_reset_state(dev, pcie_hot_reset);
+	if (retval) {
+		mods_error_printk(
+		    "pci_hot_reset failed on %04x:%x:%02x.%x\n",
+		    (unsigned int)p->pci_device.domain,
+		    (unsigned int)p->pci_device.bus,
+		    (unsigned int)p->pci_device.device,
+		    (unsigned int)p->pci_device.function);
+		return retval;
+	}
+
+	retval = pci_set_pcie_reset_state(dev, pcie_deassert_reset);
+	if (retval) {
+		mods_error_printk(
+		    "pci_hot_reset deassert failed on %04x:%x:%02x.%x\n",
+		    (unsigned int)p->pci_device.domain,
+		    (unsigned int)p->pci_device.bus,
+		    (unsigned int)p->pci_device.device,
+		    (unsigned int)p->pci_device.function);
+		return retval;
+	}
+
+	return OK;
+#else
+	return -EINVAL;
+#endif
+}
+
+/************************
+ * PIO ESCAPE FUNCTIONS *
+ ************************/
+
+int esc_mods_pio_read(struct file *pfile, struct MODS_PIO_READ *p)
+{
+	LOG_ENT();
+	switch (p->data_size) {
+	case 1:
+		p->data = inb(p->port);
+		break;
+	case 2:
+		p->data = inw(p->port);
+		break;
+	case 4:
+		p->data = inl(p->port);
+		break;
+	default:
+		return -EINVAL;
+	}
+	LOG_EXT();
+	return OK;
+}
+
+int esc_mods_pio_write(struct file *pfile, struct MODS_PIO_WRITE  *p)
+{
+	LOG_ENT();
+	switch (p->data_size) {
+	case 1:
+		outb(p->data, p->port);
+		break;
+	case 2:
+		outw(p->data, p->port);
+		break;
+	case 4:
+		outl(p->data, p->port);
+		break;
+	default:
+		return -EINVAL;
+	}
+	LOG_EXT();
+	return OK;
+}
+
+int esc_mods_device_numa_info_2(struct file *fp,
+				struct MODS_DEVICE_NUMA_INFO_2 *p)
+{
+#ifdef MODS_HAS_DEV_TO_NUMA_NODE
+	unsigned int devfn = PCI_DEVFN(p->pci_device.device,
+				       p->pci_device.function);
+	struct pci_dev *dev = MODS_PCI_GET_SLOT(p->pci_device.domain,
+						p->pci_device.bus, devfn);
+
+	LOG_ENT();
+
+	if (dev == NULL) {
+		mods_error_printk("PCI device %04x:%x:%02x.%x not found\n",
+				  p->pci_device.domain,
+				  p->pci_device.bus, p->pci_device.device,
+				  p->pci_device.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	p->node = dev_to_node(&dev->dev);
+	if (-1 != p->node) {
+		const unsigned long *maskp
+			= cpumask_bits(cpumask_of_node(p->node));
+		unsigned int i, word, bit, maskidx;
+
+		if (((nr_cpumask_bits + 31) / 32) > MAX_CPU_MASKS) {
+			mods_error_printk("too many CPUs (%d) for mask bits\n",
+					  nr_cpumask_bits);
+			LOG_EXT();
+			return -EINVAL;
+		}
+
+		for (i = 0, maskidx = 0;
+		     i < nr_cpumask_bits;
+		     i += 32, maskidx++) {
+			word = i / BITS_PER_LONG;
+			bit = i % BITS_PER_LONG;
+			p->node_cpu_mask[maskidx]
+				= (maskp[word] >> bit) & 0xFFFFFFFFUL;
+		}
+	}
+	p->node_count = num_possible_nodes();
+	p->cpu_count = num_possible_cpus();
+
+	LOG_EXT();
+	return OK;
+#else
+	return -EINVAL;
+#endif
+}
+
+int esc_mods_device_numa_info(struct file *fp,
+			      struct MODS_DEVICE_NUMA_INFO *p)
+{
+	int retval, i;
+	struct MODS_DEVICE_NUMA_INFO_2 numa_info = { {0} };
+
+	numa_info.pci_device.domain	= 0;
+	numa_info.pci_device.bus	= p->pci_device.bus;
+	numa_info.pci_device.device	= p->pci_device.device;
+	numa_info.pci_device.function	= p->pci_device.function;
+
+	retval = esc_mods_device_numa_info_2(fp, &numa_info);
+	if (retval)
+		return retval;
+
+	p->node				= numa_info.node;
+	p->node_count			= numa_info.node_count;
+	for (i = 0; i < MAX_CPU_MASKS; i++)
+		p->node_cpu_mask[i]	= numa_info.node_cpu_mask[i];
+	p->cpu_count			= numa_info.cpu_count;
+	return OK;
+}
+
+int esc_mods_pci_map_resource(struct file *fp,
+			      struct MODS_PCI_MAP_RESOURCE  *p)
+{
+#if defined(MODS_HAS_PCI_MAP_RESOURCE)
+	MODS_PRIV                     private_data = fp->private_data;
+	unsigned int                  devfn;
+	struct pci_dev               *rem_dev;
+	struct pci_dev               *loc_dev;
+	struct MODS_PCI_RES_MAP_INFO *p_res_map;
+
+	LOG_ENT();
+
+	devfn = PCI_DEVFN(p->local_pci_device.device,
+			  p->local_pci_device.function);
+	loc_dev = MODS_PCI_GET_SLOT(p->local_pci_device.domain,
+				    p->local_pci_device.bus, devfn);
+	if (!loc_dev) {
+		mods_error_printk("Local PCI device %04x:%x:%02x.%x not found\n",
+				  p->local_pci_device.domain,
+				  p->local_pci_device.bus,
+				  p->local_pci_device.device,
+				  p->local_pci_device.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	devfn = PCI_DEVFN(p->remote_pci_device.device,
+			  p->remote_pci_device.function);
+	rem_dev = MODS_PCI_GET_SLOT(p->remote_pci_device.domain,
+				    p->remote_pci_device.bus, devfn);
+	if (!rem_dev) {
+		mods_error_printk("Remote PCI device %04x:%x:%02x.%x not found\n",
+				  p->remote_pci_device.domain,
+				  p->remote_pci_device.bus,
+				  p->remote_pci_device.device,
+				  p->remote_pci_device.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	if ((p->resource_index >= DEVICE_COUNT_RESOURCE) ||
+	    !pci_resource_len(rem_dev, p->resource_index)) {
+		mods_error_printk(
+			"Resource %u on device %04x:%x:%02x.%x not found\n",
+			p->resource_index,
+			p->remote_pci_device.domain,
+			p->remote_pci_device.bus,
+			p->remote_pci_device.device,
+			p->remote_pci_device.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	if ((p->va < pci_resource_start(rem_dev, p->resource_index)) ||
+	    (p->va > pci_resource_end(rem_dev, p->resource_index)) ||
+	    (p->va + p->page_count * PAGE_SIZE >
+			pci_resource_end(rem_dev, p->resource_index))) {
+		mods_error_printk(
+			"bad resource address 0x%04x:%x:%02x.%x on device %u:%u:%u.%u\n"
+			(unsigned long long)p->va,
+			p->remote_pci_device.domain,
+			p->remote_pci_device.bus,
+			p->remote_pci_device.device,
+			p->remote_pci_device.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	p_res_map = kmalloc(sizeof(struct MODS_PCI_RES_MAP_INFO),
+			    GFP_KERNEL | __GFP_NORETRY);
+	if (unlikely(!p_res_map)) {
+		mods_error_printk("failed to allocate pci res map struct\n");
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+	p_res_map->dev = loc_dev;
+	p_res_map->page_count = p->page_count;
+	p_res_map->va = pci_map_resource(loc_dev,
+		&rem_dev->resource[resource_index],
+		p->va - pci_resource_start(rem_dev, p->resource_index),
+		p->page_count * PAGE_SIZE,
+		PCI_DMA_BIDIRECTIONAL);
+	p_res_map->va = p->va;
+	if (pci_dma_mapping_error(loc_dev, p_res_map->va)) {
+		kfree(p_res_map);
+		LOG_EXT();
+		return -ENOMEM;
+	}
+
+	if (unlikely(mutex_lock_interruptible(&private_data->mtx))) {
+		kfree(p_res_map);
+		LOG_EXT();
+		return -EINTR;
+	}
+	list_add(&p_res_map->list, private_data->mods_pci_res_map_list);
+	mutex_unlock(&private_data->mtx);
+
+	p->va = p_res_map->va;
+
+	mods_debug_printk(DEBUG_PCICFG,
+			  "mapped pci resource %u from %u:%u:%u.%u to %u:%u:%u.%u at 0x%llx\n",
+			  p->resource_index,
+			  p->remote_pci_device.domain,
+			  p->remote_pci_device.bus,
+			  p->remote_pci_device.device,
+			  p->remote_pci_device.function,
+			  p->local_pci_device.domain,
+			  p->local_pci_device.bus,
+			  p->local_pci_device.device,
+			  p->local_pci_device.function,
+			  p->va);
+#else
+	/*
+	 * We still return OK, in case the system is running an older kernel
+	 * with the IOMMU disabled. The va parameter will still contain the
+	 * input physical address, which is what the device should use in this
+	 * fallback case.
+	 */
+#endif
+	return OK;
+}
+
+int esc_mods_pci_unmap_resource(struct file *fp,
+				struct MODS_PCI_UNMAP_RESOURCE  *p)
+{
+#if defined(MODS_HAS_PCI_MAP_RESOURCE)
+	MODS_PRIV         private_data = fp->private_data;
+	unsigned int      devfn = PCI_DEVFN(p->pci_device.device,
+					    p->pci_device.function);
+	struct pci_dev   *dev   = MODS_PCI_GET_SLOT(p->pci_device.domain,
+						    p->pci_device.bus, devfn);
+	struct list_head *head  = private_data->mods_pci_res_map_list;
+	struct list_head *iter;
+	struct list_head *tmp;
+
+	LOG_ENT();
+
+	if (!dev) {
+		mods_error_printk("PCI device %04x:%x:%02x.%x not found\n",
+				  p->pci_device.domain,
+				  p->pci_device.bus,
+				  p->pci_device.device,
+				  p->pci_device.function);
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	list_for_each_safe(iter, tmp, head) {
+		struct MODS_PCI_RES_MAP_INFO *p_pci_res_map_info;
+
+		p_pci_res_map_info =
+		    list_entry(iter, struct MODS_PCI_RES_MAP_INFO, list);
+
+		if ((p_pci_res_map_info->dev == dev) &&
+		    (p_pci_res_map_info->va == p->va)) {
+			int ret = mods_free_pci_res_map(fp, p_pci_res_map_info);
+
+			LOG_EXT();
+			return ret;
+		}
+	}
+
+	mods_error_printk(
+		"PCI mapping 0x%llx on device %04x:%x:%02x.%x not found\n",
+		p->va,
+		p->pci_device.domain,
+		p->pci_device.bus,
+		p->pci_device.device,
+		p->pci_device.function);
+	return -EINVAL;
+#else
+	return OK;
+#endif
+}
+
+#if defined(MODS_HAS_SET_PPC_TCE_BYPASS)
+int esc_mods_get_ats_address_range(struct file *fp,
+				   struct MODS_GET_ATS_ADDRESS_RANGE *p)
+{
+	unsigned int	    devfn;
+	struct pci_dev	   *dev;
+	struct pci_dev	   *npu_dev;
+	struct device_node *mem_node = NULL;
+	const __u32	   *val32;
+	const __u64	   *val64;
+	int		    len;
+	int		    ret = -EINVAL;
+
+	LOG_ENT();
+
+	mods_debug_printk(DEBUG_PCICFG,
+			  "get ats addr, dev %04x:%x:%02x:%x, npu index %d\n",
+			  (int)p->pci_device.domain,
+			  (int)p->pci_device.bus,
+			  (int)p->pci_device.device,
+			  (int)p->pci_device.function,
+			  (int)p->npu_index);
+
+	devfn = PCI_DEVFN(p->pci_device.device, p->pci_device.function);
+	dev = MODS_PCI_GET_SLOT(p->pci_device.domain, p->pci_device.bus, devfn);
+	if (dev == NULL)  {
+		mods_error_printk("PCI device %04x:%x:%02x.%x not found\n",
+				  p->pci_device.domain,
+				  p->pci_device.bus,
+				  p->pci_device.device,
+				  p->pci_device.function);
+		goto exit;
+	}
+
+	npu_dev = pnv_pci_get_npu_dev(dev, p->npu_index);
+	if (npu_dev == NULL) {
+		mods_error_printk("NPU device for %04x:%x:%02x.%x not found\n",
+				  p->pci_device.domain,
+				  p->pci_device.bus,
+				  p->pci_device.device,
+				  p->pci_device.function);
+		goto exit;
+	}
+
+	p->npu_device.domain   = pci_domain_nr(npu_dev->bus);
+	p->npu_device.bus      = npu_dev->bus->number;
+	p->npu_device.device   = PCI_SLOT(npu_dev->devfn);
+	p->npu_device.function = PCI_FUNC(npu_dev->devfn);
+
+	mods_debug_printk(DEBUG_PCICFG,
+			  "Found NPU device %04x:%x:%02x.%x\n",
+			  p->npu_device.domain,
+			  p->npu_device.bus,
+			  p->npu_device.device,
+			  p->npu_device.function);
+
+	val32 = (const __u32 *)of_get_property(npu_dev->dev.of_node,
+					       "memory-region",
+					       &len);
+	if (!val32 || len < 4) {
+		mods_error_printk("Property memory-region for NPU not found\n");
+		goto exit;
+	}
+
+	mem_node = of_find_node_by_phandle(be32_to_cpu(*val32));
+	if (!mem_node) {
+		mods_error_printk("Node memory-region for NPU not found\n");
+		goto exit;
+	}
+
+	p->numa_memory_node = of_node_to_nid(mem_node);
+	if (p->numa_memory_node == NUMA_NO_NODE) {
+		mods_error_printk("NUMA node for NPU not found\n");
+		goto exit;
+	}
+
+	val64 = (const __u64 *)of_get_property(npu_dev->dev.of_node,
+					       "ibm,device-tgt-addr",
+					       &len);
+	if (!val64 || len < 8) {
+		mods_error_printk(
+			"Property ibm,device-tgt-addr for NPU not found\n");
+		goto exit;
+	}
+
+	p->phys_addr = be64_to_cpu(*val64);
+
+	val64 = (const __u64 *)of_get_property(mem_node, "reg", &len);
+	if (!val64 || len < 16) {
+		mods_error_printk("Property reg for memory region not found\n");
+		goto exit;
+	}
+
+	p->guest_addr    = be64_to_cpu(val64[0]);
+	p->aperture_size = be64_to_cpu(val64[1]);
+
+	ret = OK;
+
+exit:
+	if (mem_node)
+		of_node_put(mem_node);
+	LOG_EXT();
+	return ret;
+}
+#endif
diff --git a/drivers/misc/mods/mods_tegradc.c b/drivers/misc/mods/mods_tegradc.c
new file mode 100644
index 00000000..7ced39b7
--- /dev/null
+++ b/drivers/misc/mods/mods_tegradc.c
@@ -0,0 +1,346 @@
+/*
+ * mods_tegradc.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/uaccess.h>
+#include <../drivers/video/tegra/dc/dc_priv.h>
+#if defined(CONFIG_TEGRA_NVSD)
+#include <../drivers/video/tegra/dc/nvsd.h>
+#endif
+#include <video/tegra_dc_ext_kernel.h>
+#include <linux/platform/tegra/mc.h>
+#include "mods_internal.h"
+
+static void mods_tegra_dc_set_windowattr_basic(struct tegra_dc_win *win,
+		       const struct MODS_TEGRA_DC_WINDOW *mods_win)
+{
+	win->global_alpha = 0;
+	win->z            = 0;
+	win->stride       = 0;
+	win->stride_uv    = 0;
+
+	win->flags = TEGRA_WIN_FLAG_ENABLED;
+	if (mods_win->flags & MODS_TEGRA_DC_WINDOW_FLAG_TILED)
+		win->flags |= TEGRA_WIN_FLAG_TILED;
+#if defined(CONFIG_TEGRA_DC_SCAN_COLUMN)
+	if (mods_win->flags & MODS_TEGRA_DC_WINDOW_FLAG_SCAN_COL)
+		win->flags |= TEGRA_WIN_FLAG_SCAN_COLUMN;
+#endif
+
+	win->fmt = mods_win->pixformat;
+	win->x.full = mods_win->x;
+	win->y.full = mods_win->y;
+	win->w.full = mods_win->w;
+	win->h.full = mods_win->h;
+	/* XXX verify that this doesn't go outside display's active region */
+	win->out_x = mods_win->out_x;
+	win->out_y = mods_win->out_y;
+	win->out_w = mods_win->out_w;
+	win->out_h = mods_win->out_h;
+
+	mods_debug_printk(DEBUG_TEGRADC,
+		"mods_tegra_dc_set_windowattr_basic window %u:\n"
+		"\tflags : 0x%08x\n"
+		"\tfmt   : %u\n"
+		"\tinput : (%u, %u, %u, %u)\n"
+		"\toutput: (%u, %u, %u, %u)\n",
+		win->idx, win->flags, win->fmt, dfixed_trunc(win->x),
+		dfixed_trunc(win->y), dfixed_trunc(win->w),
+		dfixed_trunc(win->h), win->out_x, win->out_y, win->out_w,
+		win->out_h);
+}
+
+int esc_mods_tegra_dc_config_possible(struct file *fp,
+				struct MODS_TEGRA_DC_CONFIG_POSSIBLE *args)
+{
+	int i;
+	struct tegra_dc *dc = tegra_dc_get_dc(args->head);
+	struct tegra_dc_win *dc_wins[DC_N_WINDOWS];
+#ifndef CONFIG_TEGRA_ISOMGR
+	struct clk *emc_clk = 0;
+	unsigned long max_bandwidth = 0;
+	unsigned long current_emc_freq = 0;
+	unsigned long max_available_bandwidth = 0;
+#else
+	int ret = -EINVAL;
+#endif
+
+	LOG_ENT();
+
+	BUG_ON(args->win_num > tegra_dc_get_numof_dispwindows());
+
+	if (!dc) {
+		LOG_EXT();
+		return -EINVAL;
+	}
+
+	for (i = 0; i < args->win_num; i++) {
+		int idx = args->windows[i].index;
+
+		if (args->windows[i].flags &
+			MODS_TEGRA_DC_WINDOW_FLAG_ENABLED) {
+			mods_tegra_dc_set_windowattr_basic(&dc->tmp_wins[idx],
+							  &args->windows[i]);
+		} else {
+			dc->tmp_wins[idx].flags = 0;
+		}
+		dc_wins[i] = &dc->tmp_wins[idx];
+		mods_debug_printk(DEBUG_TEGRADC,
+			"head %u, using index %d for win %d\n",
+			args->head, i, idx);
+	}
+
+	mods_debug_printk(DEBUG_TEGRADC,
+		"head %u, dc->mode.pclk %u\n",
+		args->head, dc->mode.pclk);
+
+#ifndef CONFIG_TEGRA_ISOMGR
+	max_bandwidth = tegra_dc_get_bandwidth(dc_wins, args->win_num);
+
+	emc_clk = clk_get_sys("tegra_emc", "emc");
+	if (IS_ERR(emc_clk)) {
+		mods_debug_printk(DEBUG_TEGRADC,
+		"invalid clock specified when fetching EMC clock\n");
+	} else {
+		current_emc_freq = clk_get_rate(emc_clk);
+		current_emc_freq /= 1000;
+		max_available_bandwidth =
+			8 * tegra_emc_freq_req_to_bw(current_emc_freq);
+		max_available_bandwidth = (max_available_bandwidth / 100) * 50;
+	}
+
+	mods_debug_printk(DEBUG_TEGRADC,
+		"b/w needed %lu, b/w available %lu\n",
+		max_bandwidth, max_available_bandwidth);
+
+	args->possible = (max_bandwidth <= max_available_bandwidth);
+#else
+	ret = tegra_dc_bandwidth_negotiate_bw(dc, dc_wins, args->win_num);
+	args->possible = (ret == 0);
+#endif
+	for (i = 0; i < args->win_num; i++) {
+		args->windows[i].bandwidth = dc_wins[i]->new_bandwidth;
+		mods_debug_printk(DEBUG_TEGRADC,
+			"head %u, win %d, b/w %d\n",
+			args->head, dc_wins[i]->idx, dc_wins[i]->new_bandwidth);
+	}
+
+	LOG_EXT();
+	return 0;
+}
+
+#ifdef CONFIG_TEGRA_NVSD
+
+/* TODO Remove these constants and allocate memory dynamically based on
+ * tegra_dc_get_numof_dispheads once intermittent crash faced due to dynamic
+ * allocation is resolved
+ * TODO revisit for future tegra chips which may need more than 3 heads.
+ * Hopefully we move to dynamic allocation before that
+ */
+#if defined(CONFIG_TEGRA_NVDISPLAY)
+#define TEGRA_MAX_DC		3
+#else
+#define TEGRA_MAX_DC		2
+#endif
+
+static struct tegra_dc_sd_settings mods_sd_settings[TEGRA_MAX_DC];
+static struct tegra_dc_sd_settings *tegra_dc_saved_sd_settings[TEGRA_MAX_DC];
+
+/* Cache head count retrieved during mods_init_tegradc. */
+static int cachedHeadCount;
+
+#endif
+
+#define SD_KINIT_BIAS(x)  (((x) & 0x3) << 29)
+
+int esc_mods_tegra_dc_setup_sd(struct file *fp,
+	struct MODS_TEGRA_DC_SETUP_SD *args)
+{
+#if !defined(CONFIG_TEGRA_NVDISPLAY)
+	int i;
+	struct tegra_dc *dc = tegra_dc_get_dc(args->head);
+	struct tegra_dc_sd_settings *sd_settings = dc->out->sd_settings;
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
+	u32 val;
+#endif
+	u32 bw_idx;
+
+	LOG_ENT();
+
+	BUG_ON(args->head > tegra_dc_get_numof_dispheads());
+
+	sd_settings->enable = args->enable ? 1 : 0;
+	sd_settings->use_auto_pwm = false;
+	sd_settings->hw_update_delay = 0;
+
+	sd_settings->aggressiveness = args->aggressiveness;
+	sd_settings->bin_width = (1 << args->bin_width_log2);
+
+	sd_settings->phase_in_settings = 0;
+	sd_settings->phase_in_adjustments = 0;
+	sd_settings->cmd = 0;
+	sd_settings->final_agg = args->aggressiveness;
+	sd_settings->cur_agg_step = 0;
+	sd_settings->phase_settings_step = 0;
+	sd_settings->phase_adj_step = 0;
+	sd_settings->num_phase_in_steps = 0;
+
+	sd_settings->agg_priorities.agg[0] = args->aggressiveness;
+
+	sd_settings->use_vid_luma = args->use_vid_luma;
+	sd_settings->coeff.r = args->csc_r;
+	sd_settings->coeff.g = args->csc_g;
+	sd_settings->coeff.b = args->csc_b;
+
+	sd_settings->k_limit_enable = (args->klimit != 0);
+	sd_settings->k_limit = args->klimit;
+	sd_settings->sd_window_enable = true;
+
+	sd_settings->sd_window.h_position = args->win_x;
+	sd_settings->sd_window.v_position = args->win_y;
+	sd_settings->sd_window.h_size     = args->win_w;
+	sd_settings->sd_window.v_size     = args->win_h;
+
+	sd_settings->soft_clipping_enable    = true;
+	sd_settings->soft_clipping_threshold = args->soft_clipping_threshold;
+
+
+	sd_settings->smooth_k_enable = (args->smooth_k_inc != 0);
+	sd_settings->smooth_k_incr   = args->smooth_k_inc;
+
+	sd_settings->sd_proc_control = false;
+	sd_settings->soft_clipping_correction = false;
+	sd_settings->use_vpulse2 = false;
+
+	sd_settings->fc.time_limit = 0;
+	sd_settings->fc.threshold  = 0;
+
+	sd_settings->blp.time_constant = 1024;
+	sd_settings->blp.step          = 0;
+
+
+#ifdef CONFIG_TEGRA_SD_GEN2
+	bw_idx = 0;
+#else
+	bw_idx = args->bin_width_log2;
+#endif
+	for (i = 0; i < MODS_TEGRA_DC_SETUP_BLTF_SIZE; i++) {
+		sd_settings->bltf[bw_idx][i/4][i%4] =
+			args->bltf[i];
+	}
+
+	for (i = 0; i < MODS_TEGRA_DC_SETUP_SD_LUT_SIZE; i++) {
+		sd_settings->lut[bw_idx][i].r =
+			args->lut[i] & 0xff;
+		sd_settings->lut[bw_idx][i].g =
+			(args->lut[i] >> 8) & 0xff;
+		sd_settings->lut[bw_idx][i].b =
+			(args->lut[i] >> 16) & 0xff;
+	}
+
+#if defined(CONFIG_TEGRA_NVSD)
+	nvsd_init(dc, sd_settings);
+#endif
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
+	tegra_dc_io_start(dc);
+	val = tegra_dc_readl_exported(dc, DC_DISP_SD_CONTROL);
+	val &= ~SD_KINIT_BIAS(0);
+	val &= ~SD_CORRECTION_MODE_MAN;
+	tegra_dc_writel_exported(dc, val | SD_KINIT_BIAS(args->k_init_bias),
+		DC_DISP_SD_CONTROL);
+	tegra_dc_io_end(dc);
+#endif
+
+	if (dc->enabled) {
+		mutex_lock(&dc->lock);
+		tegra_dc_get(dc);
+		tegra_dc_writel_exported(dc, GENERAL_ACT_REQ,
+				DC_CMD_STATE_CONTROL);
+		tegra_dc_put(dc);
+		mutex_unlock(&dc->lock);
+	}
+
+	LOG_EXT();
+#endif
+	return 0;
+}
+
+int mods_init_tegradc(void)
+{
+#if defined(CONFIG_TEGRA_NVSD)
+	int i, nheads;
+	int ret = 0;
+
+	LOG_ENT();
+	nheads = tegra_dc_get_numof_dispheads();
+	cachedHeadCount = nheads;
+	memset(mods_sd_settings, 0,
+	       TEGRA_MAX_DC * sizeof(struct tegra_dc_sd_settings));
+
+	BUG_ON(nheads > TEGRA_MAX_DC);
+
+	for (i = 0; i < nheads; i++) {
+		struct tegra_dc *dc = tegra_dc_get_dc(i);
+
+		if (!dc)
+			continue;
+
+		mods_sd_settings[i].enable = 0;
+		mods_sd_settings[i].sd_brightness = NULL;
+		mods_sd_settings[i].bl_device_name = NULL;
+		mods_sd_settings[i].bl_device = NULL;
+
+		tegra_dc_saved_sd_settings[i] = dc->out->sd_settings;
+		dc->out->sd_settings = &mods_sd_settings[i];
+
+		if (dc->enabled)
+			nvsd_init(dc, dc->out->sd_settings);
+
+		if (!tegra_dc_saved_sd_settings[i])
+			ret = nvsd_create_sysfs(&dc->ndev->dev);
+	}
+	LOG_EXT();
+	return ret;
+#else
+	return 0;
+#endif
+}
+
+void mods_exit_tegradc(void)
+{
+#if defined(CONFIG_TEGRA_NVSD)
+	int i, nheads;
+
+	LOG_ENT();
+	nheads = tegra_dc_get_numof_dispheads();
+
+	BUG_ON(nheads != cachedHeadCount);
+
+	for (i = 0; i < nheads; i++) {
+		struct tegra_dc *dc = tegra_dc_get_dc(i);
+
+		if (!dc)
+			continue;
+		if (!tegra_dc_saved_sd_settings[i])
+			nvsd_remove_sysfs(&dc->ndev->dev);
+		dc->out->sd_settings = tegra_dc_saved_sd_settings[i];
+		if (dc->enabled)
+			nvsd_init(dc, dc->out->sd_settings);
+	}
+#endif
+}
diff --git a/drivers/misc/mods/mods_tegraprod.c b/drivers/misc/mods/mods_tegraprod.c
new file mode 100644
index 00000000..b1e84b49
--- /dev/null
+++ b/drivers/misc/mods/mods_tegraprod.c
@@ -0,0 +1,632 @@
+/*
+ * mods_tegraprod.c - This file is part of NVIDIA MODS kernel driver.
+ *
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with NVIDIA MODS kernel driver.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mods_internal.h"
+#include <linux/err.h>
+#include <linux/miscdevice.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/tegra_prod.h>
+
+#define MAX_REG_INFO_ENTRY	400
+#define MAX_IO_MAP_ENTRY	200
+
+static struct device *mods_tegra_prod_dev;
+
+/**
+ * mods_tegra_prod_init - Initialize tegra prod module.
+ * @misc_dev:       pointer to mods device
+ *
+ * Returns 0 on success, others for error.
+ */
+int mods_tegra_prod_init(const struct miscdevice *misc_dev)
+{
+	if (!misc_dev) {
+		mods_error_printk("mods device pointer is NULL\n");
+		return -EINVAL;
+	}
+
+	mods_tegra_prod_dev = misc_dev->this_device;
+	if (!mods_tegra_prod_dev) {
+		mods_error_printk("this_device in mods device is NULL\n");
+		return -EINVAL;
+	}
+
+	return OK;
+}
+
+/**
+ * esc_mods_tegra_prod_iterate_dt - Find device_node by device name.
+ * @MODS_TEGRA_PROD_ITERATOR: Input information, only the following
+ *				members are used.
+ *   +device_handle:	Last node pointer for current iteration
+ *   +name:		Current node name
+ *   +next_name:	Next node name
+ *   +index:		Index of the device nodes shared the same name
+ *			(NOTE: index starts from 0)
+ *   +is_leaf:		Is the node with current name a leaf node
+ *   +next_device_handle: Result node pointer for next iteration
+ * Returns 0 on success, others for error or no matching node found.
+ */
+int esc_mods_tegra_prod_iterate_dt(
+	struct file *fp,
+	struct MODS_TEGRA_PROD_ITERATOR *iterator
+)
+{
+	struct device_node *dev_node;
+	struct device_node *child_node = NULL;
+	struct resource res;
+	int ret_resource = -1;
+	int i;
+
+	dev_node = (struct device_node *)iterator->device_handle;
+
+	if (!iterator->name[0]) {
+		mods_error_printk(
+			"node name is missing for tegra prod value\n");
+		return -EINVAL;
+	}
+	if (!iterator->next_name[0] && !iterator->is_leaf) {
+		mods_error_printk("inner node with empty next_name\n");
+		return -EINVAL;
+	}
+
+	/* Need to search several times since some nodes may share same name */
+	for (i = 0; i <= iterator->index; ++i) {
+		/* Search from Left to Right in DT */
+		dev_node = of_find_node_by_name(dev_node, iterator->name);
+		if (!dev_node) {
+			mods_error_printk("node %s not found in device tree\n",
+					iterator->name);
+			return -EINVAL;
+		}
+
+		/*
+		 * Search from Top to Bottom in DT
+		 * Check: does this node need to be filtered out
+		 */
+		if (iterator->is_leaf) {
+			/* Leaf node : search for "prod-settings" node */
+			child_node = of_get_child_by_name(dev_node,
+							"prod-settings");
+			ret_resource = of_address_to_resource(
+							dev_node, 0, &res);
+		} else {
+			/* Inner node : search for next device node */
+			child_node = of_get_child_by_name(dev_node,
+							iterator->next_name);
+			ret_resource = -1;
+		}
+		if (!child_node && ret_resource < 0)
+			--i;	/* Not a valid device node */
+	}
+
+	/* Return next_device_handler to ioctl caller */
+	iterator->next_device_handle = (__u64)dev_node;
+	return OK;
+}
+
+/**
+ * mods_read_reg_info - Read register information (address and size)
+ * @dev_node:		 Device node pointer
+ * @reg_info:		 Register information array
+ * @count_reg_cells:	 (OUT) Pointer to count of cells in "reg"
+ * @count_addrsize_pair: (OUT) Pointer to count of each pair in "reg"
+ * @count_address_cells: (OUT) Pointer to count of "address" cell in "reg"
+ * @count_size_cells:	 (OUT) Pointer to count of "size" cell in "reg"
+ *
+ * Return Value :
+ *    0   - OK
+ * Others - ERROR
+ *
+ */
+static int mods_read_reg_info(
+	const struct device_node *dev_node,
+	__u32 *reg_info,
+	__u32 *count_reg_cells,
+	__u32 *count_addrsize_pair,
+	__u32 *count_address_cells,
+	__u32 *count_size_cells
+)
+{
+	struct device_node *parent_node;
+	int ret;
+
+	/* Get parent node to read the format of "reg" property */
+	parent_node = dev_node->parent;
+	ret = of_property_read_u32(parent_node, "#address-cells",
+				count_address_cells);
+	if (ret < 0) {
+		mods_error_printk("Read #address-cells failed\n");
+		return ret;
+
+	} else if (*count_address_cells == 0) {
+		mods_error_printk("#address-cells cannot be 0\n");
+		return -EINVAL;
+	}
+
+	ret = of_property_read_u32(parent_node, "#size-cells",
+				count_size_cells);
+	if (ret < 0) {
+		mods_error_printk("Read #size-cells failed\n");
+		return ret;
+
+	} else if (*count_size_cells == 0) {
+		mods_error_printk("#size-cells cannot be 0\n");
+		return -EINVAL;
+	}
+	*count_addrsize_pair = *count_address_cells + *count_size_cells;
+
+	/* Read count of cells in "reg" property */
+	ret = of_property_count_u32_elems(dev_node, "reg");
+	if (ret < 0) {
+		mods_error_printk(
+			"Unable to get count of cells in \"reg\" of node %s\n",
+			dev_node->name);
+		return ret;
+	}
+
+	*count_reg_cells = (__u32)ret;
+	if (*count_reg_cells == 0) {
+		mods_error_printk("No \"reg\" info is available\n");
+		return -EINVAL;
+
+	} else if (*count_reg_cells % *count_addrsize_pair != 0) {
+		/*
+		 * "reg" property may have more than 1 pairs of address
+		 * and size. The length of each pair is represented by
+		 * "count_addrsize_pair"; the total length of "reg"
+		 * property is represented by "count_reg_cells". If
+		 * "count_reg_cells" is not an integral multiple of
+		 * "count_addrsize_pair", the read "reg" information is
+		 * incomplete or incorrect.
+		 */
+		mods_error_printk(
+			"\"reg\" property has invalid length : %d\n",
+			*count_reg_cells);
+		return -EINVAL;
+	}
+
+	/* Read register information from "reg" property */
+	ret = of_property_read_u32_array(dev_node, "reg", reg_info,
+					(size_t)(*count_reg_cells));
+	if (ret < 0) {
+		mods_error_printk(
+			"Unable to read \"reg\" property of node %s\n",
+			dev_node->name);
+		return ret;
+	}
+
+	return OK;
+}
+
+/**
+ * mods_batch_iounmap - Unmap all virtual memory mapped by IO address.
+ * @io_base:		IO address array
+ * @count_io_base:	Count of IO addresses are mapped
+ *
+ */
+static void mods_batch_iounmap(
+	void __iomem **io_base,
+	__u32 count_io_base
+)
+{
+	int i;
+
+	if (!io_base) {
+		mods_error_printk("IO base address array is NULL\n");
+		return;
+	}
+
+	for (i = 0; i < count_io_base; ++i)
+		iounmap(io_base[i]);
+}
+
+/**
+ * mods_batch_iomap - Get all segments of IO address from a device node,
+ *                    and create a virtual memory mapping.
+ * @dev_node:		Device node pointer
+ * @io_base:		(OUT) IO address array
+ * @count_io_base:	(OUT) Pointer to the count of IO addresses are mapped
+ *
+ * Return Value :
+ *    0   - OK
+ * Others - ERROR (NOTE: partially mapped IO memory will be unmapped on error)
+ *
+ */
+static int mods_batch_iomap(
+	const struct device_node *dev_node,
+	void __iomem **io_base,
+	__u32 *count_io_base
+)
+{
+	__u32 reg_info[MAX_REG_INFO_ENTRY];
+	__u32 count_reg_cells = 0;
+	__u32 count_addrsize_pair, count_address_cells, count_size_cells;
+	__u64 io_addr_base, io_addr_length;
+	void __iomem *io_addr_mapped;
+	int ret;
+	int i;
+
+	/* Check arguments */
+	if (!dev_node) {
+		mods_error_printk("Controller device handle is NULL\n");
+		return -EINVAL;
+	}
+	if (!io_base) {
+		mods_error_printk("IO base address array is NULL\n");
+		return -EINVAL;
+	}
+	if (!count_io_base) {
+		mods_error_printk("Count of IO base address array is NULL\n");
+		return -EINVAL;
+	}
+
+	/* Get registers information */
+	ret = mods_read_reg_info(
+		dev_node,
+		reg_info,
+		&count_reg_cells,
+		&count_addrsize_pair,
+		&count_address_cells,
+		&count_size_cells
+	);
+	if (ret < 0)
+		return ret;
+
+	/* IO mapping - using 64-bit physical address */
+	*count_io_base = 0;
+	for (i = 0; i < count_reg_cells;
+		i += count_addrsize_pair, *count_io_base += 1) {
+
+		/* Compute IO physical address */
+		/* Lower 32-bit IO physical address in DTB */
+		io_addr_base = reg_info[i + count_address_cells - 1];
+		if (count_address_cells > 1) {
+			/* Higher 32-bit IO physical address in DTB */
+			io_addr_base += ((__u64)reg_info
+					[i + count_address_cells - 2]) << 32;
+		}
+
+		/* Compute IO address space length */
+		/* Lower 32-bit IO address space length in DTB */
+		io_addr_length = reg_info[i + count_addrsize_pair - 1];
+		if (count_size_cells > 1) {
+			/* Higher 32-bit IO address space length in DTB */
+			io_addr_length += ((__u64)reg_info
+					[i + count_addrsize_pair - 2]) << 32;
+		}
+
+		/* Map physical address to virtual address space */
+		io_addr_mapped = ioremap((resource_size_t)io_addr_base,
+					(resource_size_t)io_addr_length);
+		if (io_addr_mapped == NULL) {
+			mods_error_printk(
+			"Unable to map io address 0x%llx, length 0x%llx\n",
+			io_addr_base, io_addr_length);
+			/* Clean :
+			 * Unmap the IO memory that have already been mapped
+			 */
+			mods_batch_iounmap(io_base, *count_io_base);
+			return -ENXIO;
+		}
+		io_base[*count_io_base] = io_addr_mapped;
+	}
+
+	return OK;
+}
+
+
+/**
+ * mods_tegra_get_prod_list - Get tegra_prod list by valid device node.
+ * @dev_node:       Device node.
+ *
+ * Returns non-NULL on success, NULL on error.
+ */
+static struct tegra_prod *mods_tegra_get_prod_list(struct device_node *dev_node)
+{
+	struct tegra_prod *prod_list;
+
+	if (!mods_tegra_prod_dev) {
+		mods_error_printk("tegra prod is not initialized\n");
+		return NULL;
+	}
+
+	if (!dev_node) {
+		mods_error_printk("device node is NULL\n");
+		return NULL;
+	}
+
+	prod_list = devm_tegra_prod_get_from_node(mods_tegra_prod_dev,
+						dev_node);
+	if (IS_ERR(prod_list)) {
+		mods_error_printk("failed to get prod_list : %s\n",
+				dev_node->name);
+		return NULL;
+	}
+
+	return prod_list;
+}
+
+/**
+ * mods_tegra_get_prod_info - Get tegra_prod_list & mapped IO addresses
+ * @MODS_TEGRA_PROD_SET_TUPLE:  Input information, only the following
+ *				members are used.
+ *   +prod_node_handle:	Handle of device node contained prod values.
+ *   +ctrl_node_handle:	Handle of controller device node.
+ * @tegra_prod_list:	(OUT) Pointer to tegra_prod_list.
+ * @ctrl_base:		(OUT) Array of mapped IO address.
+ * @count_ctrl_base:	(OUT) Pointer to count of mapped IO address.
+ *
+ * Return Value :
+ *    0   - OK
+ * Others - ERROR
+ *
+ */
+static int mods_tegra_get_prod_info(
+	const struct MODS_TEGRA_PROD_SET_TUPLE *tuple,
+	struct tegra_prod **tegra_prod_list,
+	void __iomem **ctrl_base,
+	__u32 *count_ctrl_base
+)
+{
+	struct device_node *prod_node, *ctrl_node;
+
+	if (!tegra_prod_list || !ctrl_base || !count_ctrl_base) {
+		mods_error_printk("Detected NULL pointer for out value.");
+		return -EINVAL;
+	}
+
+	prod_node = (struct device_node *)tuple->prod_dev_handle;
+	if (!prod_node) {
+		mods_error_printk("Prod device handle is NULL\n");
+		return -EINVAL;
+	}
+
+	*tegra_prod_list = mods_tegra_get_prod_list(prod_node);
+	if (!(*tegra_prod_list)) {
+		mods_error_printk(
+		"Failed to get prod_list with prod handle 0x%llx\n",
+		tuple->prod_dev_handle);
+		return -EINVAL;
+	}
+
+	ctrl_node = (struct device_node *)tuple->ctrl_dev_handle;
+	if (!ctrl_node) {
+		mods_error_printk("Controller device handle is NULL\n");
+		return -EINVAL;
+	}
+
+	return mods_batch_iomap(ctrl_node, ctrl_base, count_ctrl_base);
+}
+
+/**
+ * esc_mods_tegra_prod_is_supported - Test the prod is supported by
+ *					given prod name.
+ * @MODS_TEGRA_PROD_IS_SUPPORTED:  Input information, only the following
+				   members are used.
+ *   +prod_node_handle:     Handle of device node contained prod values.
+ *   +prod_name:            Prod name.
+ *   +is_supported:         Result of supporting given prod configuration.
+ *
+ * Return Value :
+ *    0   - OK
+ * Others - ERROR
+ *
+ */
+int esc_mods_tegra_prod_is_supported(
+	struct file *fp,
+	struct MODS_TEGRA_PROD_IS_SUPPORTED *tuple
+)
+{
+	struct device_node *prod_node;
+	struct tegra_prod *tegra_prod;
+	bool is_supported;
+
+	prod_node = (struct device_node *)tuple->prod_dev_handle;
+	if (!prod_node) {
+		mods_error_printk("Prod device handle is NULL\n");
+		return -EINVAL;
+	}
+
+	tegra_prod = mods_tegra_get_prod_list(prod_node);
+	if (!tegra_prod) {
+		mods_error_printk(
+		"Failed to get prod_list with prod handle 0x%llx\n",
+		tuple->prod_dev_handle);
+		return -EINVAL;
+	}
+
+	is_supported = tegra_prod_by_name_supported(tegra_prod,
+						tuple->prod_name);
+	tuple->is_supported = is_supported ? 1 : 0;
+
+	return OK;
+}
+
+/**
+ * esc_mods_tegra_prod_set_prod_all - Read prod values from prod device node,
+ *                                    and set prod values to controller device
+ *				      node.
+ * @MODS_TEGRA_PROD_SET_TUPLE:  Input information, only the following
+ *				members are used.
+ *   +prod_node_handle:	Handle of device node contained prod values.
+ *   +ctrl_node_handle:	Handle of controller device node.
+ *
+ * Return Value :
+ *    0   - OK
+ * Others - ERROR
+ *
+ */
+int esc_mods_tegra_prod_set_prod_all(
+	struct file *fp,
+	struct MODS_TEGRA_PROD_SET_TUPLE *tuple
+)
+{
+	int ret;
+	struct tegra_prod *tegra_prod_list;
+	void __iomem *ctrl_base[MAX_IO_MAP_ENTRY];
+	__u32 count_ctrl_base;
+
+	ret = mods_tegra_get_prod_info(tuple, &tegra_prod_list,
+				ctrl_base, &count_ctrl_base);
+	if (ret < 0)
+		return ret;
+
+	ret = tegra_prod_set_list(ctrl_base, tegra_prod_list);
+	if (ret < 0)
+		mods_error_printk("Set prod failed\n");
+
+	mods_batch_iounmap(ctrl_base, count_ctrl_base);
+
+	return ret;
+}
+
+/**
+ * esc_mods_tegra_prod_set_prod_boot - Read prod values from prod device
+ *				       node, and set prod values to
+ *				       controller device node, which are
+ *				       required for boot initialization.
+ * @MODS_TEGRA_PROD_SET_TUPLE:  Input information, only the following
+ *				members are used.
+ *   +prod_node_handle:	Handle of device node contained prod values.
+ *   +ctrl_node_handle:	Handle of controller device node.
+ *
+ * Return Value :
+ *    0   - OK
+ * Others - ERROR
+ *
+ */
+int esc_mods_tegra_prod_set_prod_boot(
+	struct file *fp,
+	struct MODS_TEGRA_PROD_SET_TUPLE *tuple
+)
+{
+	int ret;
+	struct tegra_prod *tegra_prod_list;
+	void __iomem *ctrl_base[MAX_IO_MAP_ENTRY];
+	__u32 count_ctrl_base;
+
+	ret = mods_tegra_get_prod_info(tuple, &tegra_prod_list,
+				ctrl_base, &count_ctrl_base);
+	if (ret < 0)
+		return ret;
+
+	ret = tegra_prod_set_boot_init(ctrl_base, tegra_prod_list);
+	if (ret < 0)
+		mods_error_printk("Set boot init prod failed\n");
+
+	mods_batch_iounmap(ctrl_base, count_ctrl_base);
+
+	return ret;
+}
+
+/**
+ * esc_mods_tegra_prod_set_prod_by_name - Read prod values from prod
+ *					  device node, and set prod values
+ *					  to controller device node based
+ *					  on prod name.
+ * @MODS_TEGRA_PROD_SET_TUPLE:  Input information, only the following
+ *				members are used.
+ *   +prod_node_handle:	Handle of device node contained prod values.
+ *   +ctrl_node_handle:	Handle of controller device node.
+ *   +prod_name:	Prod name.
+ *
+ * Return Value :
+ *    0   - OK
+ * Others - ERROR
+ *
+ */
+int esc_mods_tegra_prod_set_prod_by_name(
+	struct file *fp,
+	struct MODS_TEGRA_PROD_SET_TUPLE *tuple
+)
+{
+	int ret;
+	struct tegra_prod *tegra_prod_list;
+	void __iomem *ctrl_base[MAX_IO_MAP_ENTRY];
+	__u32 count_ctrl_base;
+
+	ret = mods_tegra_get_prod_info(tuple, &tegra_prod_list,
+				ctrl_base, &count_ctrl_base);
+	if (ret < 0)
+		return ret;
+
+	ret = tegra_prod_set_by_name(ctrl_base, tuple->prod_name,
+				tegra_prod_list);
+	if (ret < 0) {
+		mods_error_printk("Set prod by name \"%s\" failed\n",
+				tuple->prod_name);
+	}
+
+	mods_batch_iounmap(ctrl_base, count_ctrl_base);
+
+	return ret;
+}
+
+/**
+ * esc_mods_tegra_prod_set_prod_exact - Read prod values from prod device
+ *					node, and set prod values to
+ *					controller device node based
+ *					on prod name, index, offset, and mask.
+ * @MODS_TEGRA_PROD_SET_TUPLE:	Input information, only the following
+				members are used.
+ *   +prod_node_handle:	Handle of device node contained prod values.
+ *   +ctrl_node_handle:	Handle of controller device node.
+ *   +prod_name:	Prod name.
+ *   +index:		Index of base address.
+ *   +offset:		Offset of the register.
+ *   +mask:		Mask field on given register.
+ *
+ * Return Value :
+ *    0   - OK
+ * Others - ERROR
+ *
+ */
+int esc_mods_tegra_prod_set_prod_exact(
+	struct file *fp,
+	struct MODS_TEGRA_PROD_SET_TUPLE *tuple
+)
+{
+	int ret;
+	struct tegra_prod *tegra_prod_list;
+	void __iomem *ctrl_base[MAX_IO_MAP_ENTRY];
+	__u32 count_ctrl_base;
+
+	ret = mods_tegra_get_prod_info(tuple, &tegra_prod_list,
+				ctrl_base, &count_ctrl_base);
+	if (ret < 0)
+		return ret;
+
+	ret = tegra_prod_set_by_name_partially(ctrl_base, tuple->prod_name,
+				tegra_prod_list, tuple->index, tuple->offset,
+				tuple->mask);
+	if (ret < 0) {
+		mods_error_printk("Set prod exact by name \"%s\" failed\n",
+				tuple->prod_name);
+		mods_error_printk("index [%x]; offset [%x]; mask [%x]\n",
+				tuple->index, tuple->offset, tuple->mask);
+	}
+
+	mods_batch_iounmap(ctrl_base, count_ctrl_base);
+
+	return ret;
+}
+