From 20dbe0996b4915162bf811e65127458c2b56a998 Mon Sep 17 00:00:00 2001 From: Revanth Kumar Uppala Date: Wed, 24 Apr 2024 16:48:23 +0530 Subject: [PATCH] r8168: Fix -20C 10mbps failure in Mods test Issue: Ethernet mplan stability tests at -20C for 10Mbps fails with rate 15% Basically the GPHY 10M power saving includes the below parameters, clock speed down, pll off and reference voltage off. During debugging it was found that enable/disable pll circuit frequently when in 10M low data traffic (such as idle mode) may have a corner case and plays a part in this issue repro. Fix: So plloff saving function should be disable (do not have to open it) for nvidia -20C mplan test case. Bug 3946623 Change-Id: Ifabe9e26e840537520d66acca106b37d3c285722 Signed-off-by: Revanth Kumar Uppala Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3123359 Reviewed-by: Jon Hunter GVS: buildbot_gerritrpt Reviewed-by: Brad Griffis --- drivers/net/ethernet/realtek/r8168/r8168_n.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8168/r8168_n.c b/drivers/net/ethernet/realtek/r8168/r8168_n.c index ad63f42c..35a65cae 100644 --- a/drivers/net/ethernet/realtek/r8168/r8168_n.c +++ b/drivers/net/ethernet/realtek/r8168/r8168_n.c @@ -25331,7 +25331,10 @@ rtl8168_hw_phy_config(struct net_device *dev) } rtl8168_mdio_write(tp, 0x1F, 0x0A44); - rtl8168_set_eth_phy_bit(tp, 0x11, BIT_11); + rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_11 | BIT_7)); + rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_11)); + rtl8168_mdio_write(tp, 0x1F, 0x0A43); + rtl8168_clear_eth_phy_bit(tp, 0x10, (BIT_0)); rtl8168_mdio_write(tp, 0x1F, 0x0000); @@ -25383,7 +25386,10 @@ rtl8168_hw_phy_config(struct net_device *dev) } rtl8168_mdio_write(tp, 0x1F, 0x0A44); - rtl8168_set_eth_phy_bit(tp, 0x11, BIT_11); + rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_11 | BIT_7)); + rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_11)); + rtl8168_mdio_write(tp, 0x1F, 0x0A43); + rtl8168_clear_eth_phy_bit(tp, 0x10, (BIT_0)); rtl8168_mdio_write(tp, 0x1F, 0x0000); if (tp->RequireAdcBiasPatch) { @@ -25588,7 +25594,10 @@ rtl8168_hw_phy_config(struct net_device *dev) } } else if (tp->mcfg == CFG_METHOD_35) { rtl8168_mdio_write(tp, 0x1F, 0x0A44); - rtl8168_set_eth_phy_bit(tp, 0x11, BIT_11); + rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_11 | BIT_7)); + rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_11)); + rtl8168_mdio_write(tp, 0x1F, 0x0A43); + rtl8168_clear_eth_phy_bit(tp, 0x10, (BIT_0)); rtl8168_mdio_write(tp, 0x1F, 0x0000);