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drm/tegra: Send ICC requests with peak_bw

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When BPMP BWMGR receives ICC avg_bw requests from different memory
clients, it will sum up all avg_bw values together and use it to
determine the final EMC frequency.

Transitioning to ICC peak_bw requests will cause BPMP to evaluate
the bandwidth requirements of each memory client individually,
selecting the maximum bandwidth request from among all the clients
to determine the final EMC frequency.

This modification prevents excessive memory bandwidth allocation
when multiple host1x clients collaborate for data processing.
Currently, host1x clients request the full theoretical 100% data
bandwidth, even though the system typically doesn't fully utilize
that amount during runtime.

To address the issue of insufficient memory bandwidth when multiple
host1x clients are used together, we can reduce the boost_up_threshold
value of cactmon DFS. This adjustment ensures that when actual memory
bandwidth utilization surpasses the specified boost-up bandwidth
threshold, EMC frequency will be further scaled by one step further
to alleviate the problem.

Bug 4328471

Signed-off-by: Johnny Liu <johnliu@nvidia.com>
Change-Id: I826a374666f38718652c5cae449c0aadeabfbdb5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2996561
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Johnny Liu
2023-10-13 02:38:06 +00:00
committed by mobile promotions
parent af936f3b1e
commit 21c6a3b3e8
4 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/tegra/nvdec.c
View File

@@ -108,7 +108,7 @@ static int nvdec_set_rate(struct nvdec *nvdec, unsigned long rate)
if (nvdec->icc_write) {
emc_kbps = dev_rate * NVDEC_AXI_RW_BANDWIDTH / 1024;
err = icc_set_bw(nvdec->icc_write, kbps_to_icc(emc_kbps), 0);
err = icc_set_bw(nvdec->icc_write, 0, kbps_to_icc(emc_kbps));
if (err)
dev_warn(nvdec->dev, "failed to set icc bw: %d\n", err);
}

2
drivers/gpu/drm/tegra/nvenc.c
View File

@@ -91,7 +91,7 @@ static int nvenc_set_rate(struct nvenc *nvenc, unsigned long rate)
if (nvenc->icc_write) {
emc_kbps = dev_rate * NVENC_AXI_RW_BANDWIDTH / 1024;
err = icc_set_bw(nvenc->icc_write, kbps_to_icc(emc_kbps), 0);
err = icc_set_bw(nvenc->icc_write, 0, kbps_to_icc(emc_kbps));
if (err)
dev_warn(nvenc->dev, "failed to set icc bw: %d\n", err);
}

2
drivers/gpu/drm/tegra/nvjpg.c
View File

@@ -88,7 +88,7 @@ static int nvjpg_set_rate(struct nvjpg *nvjpg, unsigned long rate)
if (nvjpg->icc_write) {
emc_kbps = dev_rate * NVJPG_AXI_RW_BANDWIDTH / 1024;
err = icc_set_bw(nvjpg->icc_write, kbps_to_icc(emc_kbps), 0);
err = icc_set_bw(nvjpg->icc_write, 0, kbps_to_icc(emc_kbps));
if (err)
dev_warn(nvjpg->dev, "failed to set icc bw: %d\n", err);
}

2
drivers/gpu/drm/tegra/vic.c
View File

@@ -129,7 +129,7 @@ static int vic_set_rate(struct vic *vic, unsigned long rate)
if (vic->icc_write) {
emc_kbps = dev_rate * VIC_AXI_RW_BANDWIDTH / 1024;
err = icc_set_bw(vic->icc_write, kbps_to_icc(emc_kbps), 0);
err = icc_set_bw(vic->icc_write, 0, kbps_to_icc(emc_kbps));
if (err)
dev_warn(vic->dev, "failed to set icc bw: %d\n", err);
}