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nvidia-oot: add IPA type info of IVC channel
Bug 4293372 Signed-off-by: Joshua Cha <joshuac@nvidia.com> Change-Id: I5c0cf142afdac9a6a1108a38513af6861272a8e9 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2995973 (cherry picked from commit ebedbb2492ea13211b53a48655e9312ba6b255dd) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3004066 Reviewed-by: Kurt Yi <kyi@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -1,5 +1,14 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* SPDX-License-Identifier: GPL-2.0-only */
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// Copyright (c) 2019-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
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* property and proprietary rights in and to this material, related
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* documentation and any modifications thereto. Any use, reproduction,
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* disclosure or distribution of this material and related documentation
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* without an express license agreement from NVIDIA CORPORATION or
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* its affiliates is strictly prohibited.
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*/
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/*
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/*
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* This is NvSciIpc kernel driver. At present its only use is to support
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* This is NvSciIpc kernel driver. At present its only use is to support
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@@ -508,11 +517,15 @@ static int nvsciipc_ioctl_set_db(struct nvsciipc *ctx, unsigned int cmd,
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entry->vuid = vuid64.value;
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entry->vuid = vuid64.value;
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/* fill peer vmid */
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/* fill peer vmid */
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if (entry->backend == NVSCIIPC_BACKEND_IVC)
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if (entry->backend == NVSCIIPC_BACKEND_IVC) {
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/* Sometimes it fails to find vmid due to bad configuration
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/* Sometimes it fails to find vmid due to bad configuration
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* in PCT but it is not error. Hence ignore result
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* in PCT but it is not error. Hence ignore result
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*/
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*/
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(void)ivc_cdev_get_peer_vmid(entry->id, &entry->peer_vmid);
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(void)ivc_cdev_get_peer_vmid(entry->id, &entry->peer_vmid);
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(void)ivc_cdev_get_noti_type(entry->id, &entry->noti_type);
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} else {
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entry->noti_type = IVC_INVALID_IPA;
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}
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}
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}
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}
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}
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#endif /* CONFIG_TEGRA_VIRTUALIZATION */
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#endif /* CONFIG_TEGRA_VIRTUALIZATION */
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@@ -654,14 +667,14 @@ static ssize_t nvsciipc_dbg_read(struct file *filp, char __user *buf,
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}
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}
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for (i = 0; i < ctx->num_eps; i++) {
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for (i = 0; i < ctx->num_eps; i++) {
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INFO("EP[%03d]: ep_name: %s, dev_name: %s, backend: %u, nframes: %u, "
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INFO("EP[%03d]: ep:%s,dev:%s,be:%u,nfrm:%u,fsz:%u,id:%u,noti:%d(TRAP:1,MSI:2)\n", i,
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"frame_size: %u, id: %u\n", i,
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ctx->db[i]->ep_name,
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ctx->db[i]->ep_name,
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ctx->db[i]->dev_name,
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ctx->db[i]->dev_name,
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ctx->db[i]->backend,
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ctx->db[i]->backend,
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ctx->db[i]->nframes,
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ctx->db[i]->nframes,
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ctx->db[i]->frame_size,
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ctx->db[i]->frame_size,
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ctx->db[i]->id,
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ctx->db[i]->id);
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ctx->db[i]->noti_type);
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}
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}
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return 0;
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return 0;
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@@ -1,6 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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/*
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* Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
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* property and proprietary rights in and to this material, related
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* documentation and any modifications thereto. Any use, reproduction,
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* disclosure or distribution of this material and related documentation
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* without an express license agreement from NVIDIA CORPORATION or
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* its affiliates is strictly prohibited.
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*/
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*/
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#include <nvidia/conftest.h>
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#include <nvidia/conftest.h>
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@@ -283,10 +290,13 @@ static long ivc_dev_ioctl(struct file *filp, unsigned int cmd,
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info.queue_offset = ivcd->qd->offset;
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info.queue_offset = ivcd->qd->offset;
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info.area_size = ivc_area_size;
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info.area_size = ivc_area_size;
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#ifdef SUPPORTS_TRAP_MSI_NOTIFICATION
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#ifdef SUPPORTS_TRAP_MSI_NOTIFICATION
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if (ivcd->qd->msi_ipa != 0)
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if (ivcd->qd->msi_ipa != 0) {
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info.noti_ipa = ivcd->qd->msi_ipa;
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info.noti_ipa = ivcd->qd->msi_ipa;
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else
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info.noti_type = IVC_MSI_IPA;
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} else {
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info.noti_ipa = ivcd->qd->trap_ipa;
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info.noti_ipa = ivcd->qd->trap_ipa;
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info.noti_type = IVC_TRAP_IPA;
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}
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info.noti_irq = ivcd->qd->raise_irq;
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info.noti_irq = ivcd->qd->raise_irq;
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#endif /* SUPPORTS_TRAP_MSI_NOTIFICATION */
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#endif /* SUPPORTS_TRAP_MSI_NOTIFICATION */
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@@ -624,6 +634,39 @@ exit:
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}
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}
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EXPORT_SYMBOL(ivc_cdev_get_peer_vmid);
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EXPORT_SYMBOL(ivc_cdev_get_peer_vmid);
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int ivc_cdev_get_noti_type(uint32_t qid, uint32_t *noti_type)
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{
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uint32_t i;
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int32_t ret = -ENOENT;
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if ((s_infop == NULL) || (s_guestid == INVALID_VMID)) {
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ERR("ivc info or VMID is NOT initialized yet");
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ret = -EFAULT;
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goto exit;
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}
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for (i = 0; i < s_infop->nr_queues; i++) {
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struct ivc_dev *ivc = &ivc_dev_array[i];
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if (ivc->qd->id == qid) {
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if (ivc->qd->msi_ipa != 0)
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*noti_type = IVC_MSI_IPA;
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else
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*noti_type = IVC_TRAP_IPA;
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ret = 0;
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DBG("found qid %d: noti_type=%d\n", qid, *noti_type);
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break;
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}
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}
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if (ret != 0)
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INFO("qid %d not found\n", qid);
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exit:
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return ret;
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}
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EXPORT_SYMBOL(ivc_cdev_get_noti_type);
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module_init(ivc_init);
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module_init(ivc_init);
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module_exit(ivc_exit);
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module_exit(ivc_exit);
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@@ -1,32 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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*
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* This header is BSD licensed so anyone can use the definitions to implement
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* NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
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* compatible drivers/servers.
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* property and proprietary rights in and to this material, related
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*
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* documentation and any modifications thereto. Any use, reproduction,
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* Redistribution and use in source and binary forms, with or without
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* disclosure or distribution of this material and related documentation
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* modification, are permitted provided that the following conditions
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* without an express license agreement from NVIDIA CORPORATION or
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* are met:
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* its affiliates is strictly prohibited.
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of NVIDIA CORPORATION nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#ifndef __NVSCIIPC_IOCTL_H__
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#ifndef __NVSCIIPC_IOCTL_H__
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@@ -57,6 +38,7 @@ struct nvsciipc_config_entry {
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uint32_t remote_port;
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uint32_t remote_port;
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uint32_t local_port;
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uint32_t local_port;
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uint32_t peer_vmid;
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uint32_t peer_vmid;
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uint32_t noti_type;
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};
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};
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struct nvsciipc_db {
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struct nvsciipc_db {
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@@ -1,6 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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/*
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
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* property and proprietary rights in and to this material, related
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* documentation and any modifications thereto. Any use, reproduction,
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* disclosure or distribution of this material and related documentation
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* without an express license agreement from NVIDIA CORPORATION or
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* its affiliates is strictly prohibited.
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*/
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*/
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#ifndef __UAPI_TEGRA_IVC_DEV_H
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#ifndef __UAPI_TEGRA_IVC_DEV_H
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@@ -8,6 +15,10 @@
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#include <linux/ioctl.h>
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#include <linux/ioctl.h>
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#define IVC_INVALID_IPA 0U
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#define IVC_TRAP_IPA 1U
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#define IVC_MSI_IPA 2U
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struct nvipc_ivc_info {
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struct nvipc_ivc_info {
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uint32_t nframes;
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uint32_t nframes;
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uint32_t frame_size;
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uint32_t frame_size;
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@@ -17,6 +28,7 @@ struct nvipc_ivc_info {
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bool rx_first;
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bool rx_first;
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uint64_t noti_ipa;
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uint64_t noti_ipa;
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uint16_t noti_irq;
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uint16_t noti_irq;
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uint16_t noti_type; /* IVC_TRAP_IPA, IVC_MSI_IPA */
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};
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};
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/* IOCTL magic number */
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/* IOCTL magic number */
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@@ -37,5 +49,6 @@ struct nvipc_ivc_info {
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#define NVIPC_IVC_IOCTL_NUMBER_MAX 3
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#define NVIPC_IVC_IOCTL_NUMBER_MAX 3
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int ivc_cdev_get_peer_vmid(uint32_t qid, uint32_t *peer_vmid);
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int ivc_cdev_get_peer_vmid(uint32_t qid, uint32_t *peer_vmid);
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int ivc_cdev_get_noti_type(uint32_t qid, uint32_t *noti_type);
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#endif
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#endif
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