tegra-virt-alt: Add minimal support for T264

- CIF register bitmask is updated in T264, it is mandatory
  to update it for T264 audio usecases.
- With this change all T234 AHUB usecases can be verified.

TAS-2330

Change-Id: I9b64fcb5725bfd4dd01ef29466f7255bdfd6a53f
Signed-off-by: Sheetal <sheetal@nvidia.com>

sound/soc/tegra-virt-alt/tegra210_virt_alt_admaif.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  */
 
 #include <nvidia/conftest.h>
@@ -44,6 +44,9 @@ static int tegra210_admaif_hw_params(struct snd_pcm_substream *substream,
 	struct tegra210_virt_audio_cif cif_conf;
 	struct nvaudio_ivc_msg	msg;
 	unsigned int value;
+	unsigned int audio_bits_shift;
+	unsigned int audio_ch_shift;
+	unsigned int client_ch_shift;
 	int err;
 
 	memset(&cif_conf, 0, sizeof(struct tegra210_virt_audio_cif));
@@ -73,14 +76,20 @@ static int tegra210_admaif_hw_params(struct snd_pcm_substream *substream,
 	}
 	cif_conf.direction = substream->stream;
 
+	audio_bits_shift = (admaif->num_ch == TEGRA264_MAX_CHANNELS) ?
+		TEGRA_32CH_ACIF_CTRL_AUDIO_BITS_SHIFT : TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT;
+
+	audio_ch_shift = (admaif->num_ch == TEGRA264_MAX_CHANNELS) ?
+		TEGRA_32CH_ACIF_CTRL_AUDIO_CH_SHIFT : TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT;
+
+	client_ch_shift = (admaif->num_ch == TEGRA264_MAX_CHANNELS) ?
+		TEGRA_32CH_ACIF_CTRL_CLIENT_CH_SHIFT : TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT;
+
 	value = (cif_conf.threshold <<
 			TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
-		((cif_conf.audio_channels - 1) <<
+		((cif_conf.audio_channels - 1) << audio_ch_shift) |
-			TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
+		((cif_conf.client_channels - 1) << client_ch_shift) |
-		((cif_conf.client_channels - 1) <<
+		(cif_conf.audio_bits << audio_bits_shift) |
-			TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
-		(cif_conf.audio_bits <<
-			TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
 		(cif_conf.client_bits <<
 			TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
 		(cif_conf.expand <<
@@ -882,6 +891,16 @@ int tegra210_virt_admaif_register_component(struct platform_device *pdev,
 			admaif->capture_dma_data[i].addr = TEGRA210_ADMAIF_BASE +
 					TEGRA210_ADMAIF_XBAR_RX_FIFO_READ +
 					(i * TEGRA210_ADMAIF_CHANNEL_REG_STRIDE);
+		} else if (of_device_is_compatible(pdev->dev.of_node,
+			"nvidia,tegra264-virt-pcm-oot")) {
+			admaif->playback_dma_data[i].addr = TEGRA264_ADMAIF_BASE +
+					TEGRA264_ADMAIF_XBAR_TX_FIFO_WRITE +
+					(i * TEGRA264_ADMAIF_CHANNEL_REG_STRIDE);
+			admaif->capture_dma_data[i].addr = TEGRA264_ADMAIF_BASE +
+					TEGRA264_ADMAIF_XBAR_RX_FIFO_READ +
+					(i * TEGRA264_ADMAIF_CHANNEL_REG_STRIDE);
+			/* TODO: Should get from soc_data during full Thor changes */
+			admaif->num_ch = TEGRA264_MAX_CHANNELS;
 		} else {
 			dev_err(&pdev->dev,
 				"Uncompatible device driver\n");

sound/soc/tegra-virt-alt/tegra210_virt_alt_admaif.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  */
 
 #ifndef __TEGRA210_VIRT_ALT_ADMAIF_H__
@@ -37,6 +37,16 @@
 #define TEGRA210_AUDIOCIF_CTRL_TRUNCATE_SHIFT		1
 #define TEGRA210_AUDIOCIF_CTRL_MONO_CONV_SHIFT		0
 
+#define TEGRA264_ADMAIF_BASE				0x09610000
+#define TEGRA264_ADMAIF_XBAR_RX_FIFO_READ		0x2c
+#define TEGRA264_ADMAIF_XBAR_TX_FIFO_WRITE		0x102c
+#define TEGRA264_ADMAIF_CHANNEL_REG_STRIDE		0x40
+#define TEGRA_32CH_ACIF_CTRL_AUDIO_BITS_SHIFT		11
+#define TEGRA_32CH_ACIF_CTRL_CLIENT_CH_SHIFT		14
+#define TEGRA_32CH_ACIF_CTRL_AUDIO_CH_SHIFT		19
+
+#define TEGRA264_MAX_CHANNELS				32
+
 /* ADMAIF ids */
 enum {
 	ADMAIF_ID_0 = 0,
@@ -89,6 +99,7 @@ struct tegra210_admaif {
 	struct tegra_alt_pcm_dma_params *capture_dma_data;
 	struct tegra_alt_pcm_dma_params *playback_dma_data;
 	struct tegra210_virt_admaif_client_data client_data;
+	unsigned int num_ch;
 };
 
 struct tegra_virt_admaif_soc_data {

sound/soc/tegra-virt-alt/tegra_asoc_xbar_virt_alt.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  */
 
 #include <linux/module.h>
@@ -1109,6 +1109,13 @@ int tegra_virt_xbar_register_codec(struct platform_device *pdev)
 				&tegra234_virt_xbar_codec,
 				tegra186_virt_xbar_dais,
 				ARRAY_SIZE(tegra186_virt_xbar_dais), "xbar");
+	} else if (of_device_is_compatible(pdev->dev.of_node,
+		"nvidia,tegra264-virt-pcm-oot")) {
+		/* TODO: Update it when add full Thor support */
+		ret = tegra_register_component(&pdev->dev,
+				&tegra234_virt_xbar_codec,
+				tegra186_virt_xbar_dais,
+				ARRAY_SIZE(tegra186_virt_xbar_dais), "xbar");
 	} else {
 		ret = tegra_register_component(&pdev->dev,
 				&tegra186_virt_xbar_codec,

sound/soc/tegra-virt-alt/tegra_virt_ref_alt.c

@@ -54,6 +54,9 @@ static const struct of_device_id tegra_virt_machine_of_match[] = {
 		.data = &soc_data_tegra186},
 	{ .compatible = "nvidia,tegra234-virt-pcm-oot",
 		.data = &soc_data_tegra186},
+	{ .compatible = "nvidia,tegra264-virt-pcm-oot",
+		/* TODO: Update soc_data for t264 while adding full Thor support */
+		.data = &soc_data_tegra186},
 	{},
 };