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dla: kmd: Update fuse register read for K5.15
+ Enabled the logic to read the DLA Fuse registers directly for K5.15 + Required for setting up the correct DLA instance on fused boards like TA983 Bug 4156086 Change-Id: I23addb28c54466979fd88a1b3c65960b10f946ca Signed-off-by: Akshata Bhat <akshatab@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2929422 Reviewed-by: Maxim Grigoriev (SW-GPU) <maximg@nvidia.com> Reviewed-by: Arvind M <am@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -19,6 +19,7 @@
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#include <linux/nvmem-consumer.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_runtime.h>
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#include <soc/tegra/fuse-helper.h>
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#include <soc/tegra/fuse-helper.h>
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#include <soc/tegra/fuse.h>
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#include <uapi/linux/nvhost_nvdla_ioctl.h>
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#include <uapi/linux/nvhost_nvdla_ioctl.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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@@ -978,6 +979,8 @@ static int nvdla_probe(struct platform_device *pdev)
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struct nvdla_device *nvdla_dev = NULL;
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struct nvdla_device *nvdla_dev = NULL;
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struct device *dev = &pdev->dev;
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struct device *dev = &pdev->dev;
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uint32_t soft_fuse_ret = 0U;
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uint32_t soft_fuse_ret = 0U;
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int fuse_register_ret = 0U;
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uint32_t register_value = 0U;
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struct tegra_soc_hwpm_ip_ops hwpm_ip_ops;
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struct tegra_soc_hwpm_ip_ops hwpm_ip_ops;
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#if !IS_ENABLED(CONFIG_TEGRA_GRHOST)
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#if !IS_ENABLED(CONFIG_TEGRA_GRHOST)
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@@ -1037,26 +1040,26 @@ static int nvdla_probe(struct platform_device *pdev)
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err = -ENODEV;
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err = -ENODEV;
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goto err_no_ip;
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goto err_no_ip;
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}
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}
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#if KERNEL_VERSION(5, 11, 0) >= LINUX_VERSION_CODE
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} else {
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} else {
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#if KERNEL_VERSION(5, 11, 0) >= LINUX_VERSION_CODE
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err = nvhost_nvdla_read_chip_option_register(pdev);
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fuse_register_ret = nvhost_nvdla_read_chip_option_register(pdev);
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#else
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if ((err & FUSE_OPT_DLA_0_DISABLED)
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err = tegra_fuse_readl(NVDLA_DISABLE_FUSE_REGISTER_OFFSET, ®ister_value);
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fuse_register_ret = (int)register_value;
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#endif
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if ((fuse_register_ret & FUSE_OPT_DLA_0_DISABLED)
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&& (pdata->class == NV_DLA0_CLASS_ID)) {
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&& (pdata->class == NV_DLA0_CLASS_ID)) {
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dev_err(dev, "NVDLA0 IP is disabled in Fuse\n");
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dev_err(dev, "NVDLA0 IP is disabled in Fuse\n");
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err = -ENODEV;
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err = -ENODEV;
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goto err_no_ip;
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goto err_no_ip;
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}
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}
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if ((err & FUSE_OPT_DLA_1_DISABLED)
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if ((fuse_register_ret & FUSE_OPT_DLA_1_DISABLED)
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&& (pdata->class == NV_DLA1_CLASS_ID)) {
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&& (pdata->class == NV_DLA1_CLASS_ID)) {
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dev_err(dev, "NVDLA1 IP is disabled in Fuse\n");
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dev_err(dev, "NVDLA1 IP is disabled in Fuse\n");
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err = -ENODEV;
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err = -ENODEV;
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goto err_no_ip;
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goto err_no_ip;
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}
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}
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#endif
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}
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}
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}
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}
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@@ -40,6 +40,13 @@
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#endif /* CONFIG_TEGRA_HSIERRRPTINJ */
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#endif /* CONFIG_TEGRA_HSIERRRPTINJ */
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/* DLA FUSE REGISTER
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* Corresponds to the offset of "opt-dla-disable" - part of the
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* struct tegra_fuse_cells of type nvmem_cell_info.
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*/
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#define NVDLA_DISABLE_FUSE_REGISTER_OFFSET 0x3f0
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/*
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/*
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* macro to encode firmware version
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* macro to encode firmware version
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*/
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*/
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