From 2664f7f2b7b7e1794c04c4f44371cab919dc440e Mon Sep 17 00:00:00 2001 From: Krish Agarwal Date: Thu, 15 Feb 2024 07:39:34 -0800 Subject: [PATCH] pva: drivers: prevent program of scr regs for gen3 Since power management is not supported on pre- silicon platforms on GEN3 avoid programming registers with lock bit enabled. Bug 4500579 Signed-off-by: Krish Agarwal Change-Id: Id4c2352d32a38e3e3408e54e38df3d5f723a4d20 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3077879 Reviewed-by: Sreehari Mohan Reviewed-by: Amruta Sai Anusha Bhamidipati Reviewed-by: Omar Nemri GVS: Gerrit_Virtual_Submit --- drivers/video/tegra/host/pva/pva.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/video/tegra/host/pva/pva.c b/drivers/video/tegra/host/pva/pva.c index 3e04a7d0..03b18c1f 100644 --- a/drivers/video/tegra/host/pva/pva.c +++ b/drivers/video/tegra/host/pva/pva.c @@ -382,16 +382,13 @@ static int pva_init_fw(struct platform_device *pdev) cfg_priv_ar1_usegreg_r(pva->version), PVA_EXTRACT64((useg_addr), 39, 32, u32)); - if (pdata->version != PVA_HW_GEN1) { - host1x_writel(pdev, evp_scr_r(), PVA_EVP_SCR_VAL | PVA_LOCK_SCR); - host1x_writel(pdev, cfg_scr_priv_0_r(), PVA_PRIV_SCR_VAL | PVA_LOCK_SCR); - host1x_writel(pdev, cfg_scr_ccq_ctrl_r(), PVA_CCQ_SCR_VAL | PVA_LOCK_SCR); - } - /* WAR: Bypass configuring status strl reg due to failure in gen 3 sim test */ if (pdata->version == PVA_HW_GEN2) { host1x_writel(pdev, cfg_scr_status_ctrl_r(), PVA_STATUS_CTL_SCR_VAL | PVA_LOCK_SCR); + host1x_writel(pdev, evp_scr_r(), PVA_EVP_SCR_VAL | PVA_LOCK_SCR); + host1x_writel(pdev, cfg_scr_priv_0_r(), PVA_PRIV_SCR_VAL | PVA_LOCK_SCR); + host1x_writel(pdev, cfg_scr_ccq_ctrl_r(), PVA_CCQ_SCR_VAL | PVA_LOCK_SCR); } }