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drm/tegra: nvhost support for t264

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- VIC RISC-V EB boot support
- Programming sequence modification needed for Thor
- Reloc block linear addressing not needed for t264

Bug 4132685

Signed-off-by: Santosh BS <santoshb@nvidia.com>
Change-Id: I8ad47cce31cfd06020e33d3457a0d674a11e4d49
This commit is contained in:
Santosh BS
2023-08-08 15:17:56 +00:00
committed by Jon Hunter
parent 340bd4418f
commit 26b1cb4a82
8 changed files with 416 additions and 59 deletions
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6
drivers/gpu/drm/tegra/vic.h
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@@ -18,17 +18,11 @@
#define CG_IDLE_CG_EN (1 << 6)
#define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16)
#define NV_PVIC_TFBIF_ACTMON_ACTIVE_MASK 0x0000204c
#define NV_PVIC_TFBIF_ACTMON_ACTIVE_BORPS 0x00002050
#define NV_PVIC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x00002054
#define VIC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0)
#define VIC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1)
#define VIC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2)
#define VIC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7)
#define VIC_TFBIF_TRANSCFG 0x00002044
/* Firmware offsets */
#define VIC_UCODE_FCE_HEADER_OFFSET (6*4)