nvethernet: T264 VDMA feature and initial bring up

Bug 4043836

Ported from the change -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2896006

Change-Id: I844112cc71e387f6ae04c2cc7f64b71abb4283fd
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3149289
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Rakesh Goyal
2023-04-28 11:58:49 +00:00
committed by mobile promotions
parent e7777958d3
commit 2a104ca84d
3 changed files with 271 additions and 77 deletions

View File

@@ -186,6 +186,7 @@
/**
* @brief Max pending SKB count
*/
//TBD: does need change for T264?
#define ETHER_MAX_PENDING_SKB_CNT (64 * OSI_MGBE_MAX_NUM_CHANS)
/**
@@ -348,7 +349,7 @@ struct ether_rx_napi {
*/
struct ether_vm_irq_data {
/** List of DMA Tx/Rx channel mask */
unsigned int chan_mask;
unsigned int chan_mask[3];
/** OSD private data */
struct ether_priv_data *pdata;
};
@@ -529,7 +530,7 @@ struct ether_priv_data {
/** MAC loopback mode */
unsigned int mac_loopback_mode;
/** Array of MTL queue TX priority */
unsigned int txq_prio[OSI_MGBE_MAX_NUM_CHANS];
unsigned int txq_prio[OSI_MGBE_MAX_NUM_PDMA_CHANS];
/** Spin lock for Tx/Rx interrupt enable registers */
raw_spinlock_t rlock;
/** max address register count, 2*mac_addr64_sel */