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nvethernet: T264 VDMA feature and initial bring up
Bug 4043836 Ported from the change - https://git-master.nvidia.com/r/c/nvethernet-docs/+/2896006 Change-Id: I844112cc71e387f6ae04c2cc7f64b71abb4283fd Signed-off-by: Mahesh Patil <maheshp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3149289 Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Ashutosh Jha <ajha@nvidia.com> Reviewed-by: Michael Hsu <mhsu@nvidia.com> Reviewed-by: Bhadram Varka <vbhadram@nvidia.com> Tested-by: Bhadram Varka <vbhadram@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
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@@ -186,6 +186,7 @@
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/**
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* @brief Max pending SKB count
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*/
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//TBD: does need change for T264?
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#define ETHER_MAX_PENDING_SKB_CNT (64 * OSI_MGBE_MAX_NUM_CHANS)
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/**
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@@ -348,7 +349,7 @@ struct ether_rx_napi {
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*/
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struct ether_vm_irq_data {
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/** List of DMA Tx/Rx channel mask */
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unsigned int chan_mask;
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unsigned int chan_mask[3];
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/** OSD private data */
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struct ether_priv_data *pdata;
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};
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@@ -529,7 +530,7 @@ struct ether_priv_data {
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/** MAC loopback mode */
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unsigned int mac_loopback_mode;
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/** Array of MTL queue TX priority */
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unsigned int txq_prio[OSI_MGBE_MAX_NUM_CHANS];
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unsigned int txq_prio[OSI_MGBE_MAX_NUM_PDMA_CHANS];
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/** Spin lock for Tx/Rx interrupt enable registers */
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raw_spinlock_t rlock;
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/** max address register count, 2*mac_addr64_sel */
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