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misc: tegra_cec: enable input filtering

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Bug 1605426

Change-Id: I7fdfd3eee37f91f016fcbfe573d761f551560dde
Signed-off-by: Toby Butzon <tbutzon@nvidia.com>
Reviewed-on: http://git-master/r/682207
(cherry picked from commit fb8396c2f5cc02e72dae45d9421d17565b607921)
Reviewed-on: http://git-master/r/708747
(cherry picked from commit 1c18321a0e97b6fd2568b418ea353f6716b5a2e4)
This commit is contained in:
Toby Butzon
2015-02-07 16:01:37 -08:00
committed by Prafull Suryawanshi
parent 43ca60174f
commit 2c5db18fa0
1 changed files with 1 additions and 1 deletions
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2
drivers/misc/tegra-cec/tegra_cec.c
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@@ -308,7 +308,7 @@ static void tegra_cec_init(struct tegra_cec *cec)
TEGRA_CEC_HWCTRL_TX_RX_MODE, TEGRA_CEC_HWCTRL_TX_RX_MODE,
cec->cec_base + TEGRA_CEC_HW_CONTROL); cec->cec_base + TEGRA_CEC_HW_CONTROL);
writel(0x00, cec->cec_base + TEGRA_CEC_INPUT_FILTER); writel((1U << 31) | 0x20, cec->cec_base + TEGRA_CEC_INPUT_FILTER);
writel((0x7a << TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MAX_LO_TIME_MASK) | writel((0x7a << TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MAX_LO_TIME_MASK) |
(0x6d << TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MIN_LO_TIME_MASK) | (0x6d << TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MIN_LO_TIME_MASK) |