nv-tegra-mirror/linux-nv-oot
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nv-oot.git synced 2025-12-22 09:11:26 +03:00
Code Issues Packages Projects Releases Wiki Activity

nvscic2c-pcie: add support for error handling

Browse Source 
Enable AER reporting for ednpoint.

Provide error handler for AER reception and
update error code to be read by user space process.
Change PCIe link to down.

Implement error reporting for runtime eDMA xfer errors.

Bug 4088959
Jira NVIPC-334

Change-Id: I74871e5226eab1b708c72aa71216cd160c6ebf68
Signed-off-by: dbadgaiyan <dbadgaiyan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2915753
(cherry picked from commit 7b24941fb486ada70229c42ae1deec12f75028c2)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2921480
Reviewed-by: Arihant Jejani <ajejani@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
dbadgaiyan
2023-06-05 13:30:40 +00:00
committed by mobile promotions
parent f19d5372b4
commit 3067ceeb00
8 changed files with 313 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
include/uapi/misc/nvscic2c-pcie-ioctl.h
View File

@@ -15,12 +15,24 @@
#define MAX_NAME_SZ (32)
/* Represents PCIe runtime errors reported to user space. */
#define NVSCIC2C_PCIE_NO_ERROR (0x00U)
#define NVSCIC2C_PCIE_EDMA_XFER_ERROR (0x01U)
#define NVSCIC2C_PCIE_AER_UNCORRECTABLE_FATAL (0x02U)
#define NVSCIC2C_PCIE_AER_UNCORRECTABLE_NONFATAL (0x04U)
/* Link status between the two peers - encapsulates PCIe link also.*/
enum nvscic2c_pcie_link {
NVSCIC2C_PCIE_LINK_DOWN = 0,
NVSCIC2C_PCIE_LINK_UP,
};
/* Represents layout of link status memory. */
struct nvscic2c_pcie_link_mem {
enum nvscic2c_pcie_link link_status;
__u32 aer_err;
};
/**
* stream extensions - object type.
*/
@@ -70,6 +82,7 @@ struct nvscic2c_pcie_endpoint_info {
struct nvscic2c_pcie_endpoint_mem_info peer;
struct nvscic2c_pcie_endpoint_mem_info self;
struct nvscic2c_pcie_endpoint_mem_info link;
struct nvscic2c_pcie_endpoint_mem_info edma_err;
};
/**