From 30a6d63eb25dfc1b191b8202232cc0a77c4594ec Mon Sep 17 00:00:00 2001 From: Rakesh Goyal Date: Tue, 14 Dec 2021 16:34:31 +0530 Subject: [PATCH] nvethernet: read pps output freq control Issue: Default 1 pulse (of width clk_ptp_ref_i) every second. Fix: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. low period of 537 ms and a high period of 463 ms. Bug 3462227 Change-Id: I5ec433af9e64e7709ba8e3d01261fe8a29d83198 Signed-off-by: Rakesh Goyal Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2641897 Reviewed-by: svc_kernel_abi Reviewed-by: Nagarjuna Kristam Reviewed-by: Narayan Reddy Reviewed-by: Bitan Biswas Reviewed-by: Ashutosh Jha Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/net/ethernet/nvidia/nvethernet/ether_linux.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c index b33b3434..ff31c38e 100644 --- a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c +++ b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c @@ -5921,6 +5921,16 @@ static int ether_parse_dt(struct ether_priv_data *pdata) if (ret_val < 0 || osi_core->m2m_role > OSI_PTP_M2M_SECONDARY) { osi_core->m2m_role = OSI_PTP_M2M_INACTIVE; } + + /* Set PPS output control, 0 - default. + * 1 - Binary rollover is 2 Hz, and the digital rollover is 1 Hz. + */ + ret_val = of_property_read_u32(np, "nvidia,pps_op_ctrl", + &osi_core->pps_frq); + if (ret_val < 0 || osi_core->pps_frq > OSI_ENABLE) { + osi_core->pps_frq = OSI_DISABLE; + } + exit: return ret; }