tegra_bl_debug: Read USC_TIMER base from DT

The physical address of Tegra Microsecond Timer USEC_CNTR_USECCVR_0
is currently hard-coded with the address from T234.

The address of this register changes with newer chips. Hence, read
this address from device tree.

Get rid of hard-coded values of address and size.

Change-Id: I416166f6f01cdb6009d4c53717e19f61cebe92e3
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3213600
Reviewed-by: Bhavesh Parekh <bparekh@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svc-bootloader-acv <svc-bootloader-acv@nvidia.com>

Documentation/devicetree/bindings/platform/tegra/tegra_bootloader_debug.yaml

@@ -26,6 +26,7 @@ examples:
   - |
     profiler_device {
         compatible = "nvidia,tegra_bl_debug";
+        usec_timer_reg_base = <0x0C240000>; /* USEC_CNTR_USECCVR_0 */
         status = "okay";
     };
 ...