csi5: add lane polarity config

parse the lane polarity config from the DTB and
program the nvcsi brick config accordingly.

bug 3865161

Change-Id: I70f746a40033bafa7d9286790b9c01ae5986a9f8
Signed-off-by: Anubhav Rai <arai@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2855412
(cherry picked from commit bee21e4c839b8c55ac6314fd55f2e36edd547c97)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2953780
Reviewed-by: Ankur Pawar <ankurp@nvidia.com>
Reviewed-by: Praveen AC <pac@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Semi Malinen <smalinen@nvidia.com>
Tested-by: Ankur Pawar <ankurp@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>

drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c

@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2016-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
@@ -207,6 +207,7 @@ static int csi5_stream_set_config(struct tegra_csi_channel *chan, u32 stream_id,
 	const struct sensor_mode_properties *mode = NULL;
 
 	unsigned int cil_settletime = 0;
+	unsigned int lane_polarity = 0;
 	int vi_port = 0;
 
 	struct CAPTURE_CONTROL_MSG msg;
@@ -216,7 +217,7 @@ static int csi5_stream_set_config(struct tegra_csi_channel *chan, u32 stream_id,
 	dev_dbg(csi->dev, "%s: stream_id=%u, csi_port=%u\n",
 		__func__, stream_id, csi_port);
 
-	/* Attempt to find the cil_settingtime from the device tree */
+	/* Attempt to find the brick config from the device tree */
 	if (s_data) {
 		int idx = s_data->mode_prop_idx;
 
@@ -224,13 +225,15 @@ static int csi5_stream_set_config(struct tegra_csi_channel *chan, u32 stream_id,
 		if (idx < s_data->sensor_props.num_modes) {
 			mode = &s_data->sensor_props.sensor_modes[idx];
 			cil_settletime = mode->signal_properties.cil_settletime;
+			lane_polarity = mode->signal_properties.lane_polarity;
 		} else {
 			dev_dbg(csi->dev, "mode not listed in DT, use default");
 			cil_settletime = 0;
+			lane_polarity = 0;
 		}
 	} else if (chan->of_node) {
 		int err = 0;
-		const char *str;
+		const char *str = NULL;
 
 		dev_dbg(csi->dev,
 			"cil_settletime is pulled from device of_node");
@@ -244,6 +247,18 @@ static int csi5_stream_set_config(struct tegra_csi_channel *chan, u32 stream_id,
 				cil_settletime = 0;
 			}
 		}
+		/* Reset string pointer for the next property */
+		str = NULL;
+		err = of_property_read_string(chan->of_node, "lane_polarity",
+			&str);
+		if (!err) {
+			err = kstrtou32(str, 10, &lane_polarity);
+			if (err) {
+				dev_dbg(csi->dev,
+					"no lane_polarity in of_node");
+				lane_polarity = 0;
+			}
+		}
 	}
 
 	/* Brick config */
@@ -251,6 +266,13 @@ static int csi5_stream_set_config(struct tegra_csi_channel *chan, u32 stream_id,
 	brick_config.phy_mode = (!is_cphy) ?
 		NVCSI_PHY_TYPE_DPHY : NVCSI_PHY_TYPE_CPHY;
 
+	/* Lane polarity */
+	if (!is_cphy) {
+		unsigned int index = 0;
+		for (index = 0; index < NVCSI_BRICK_NUM_LANES; index++)
+			brick_config.lane_polarity[index] = (lane_polarity >> index) & (0x1);
+	}
+
 	/* CIL config */
 	memset(&cil_config, 0, sizeof(cil_config));
 	cil_config.num_lanes = csi_lanes;

drivers/media/platform/tegra/camera/sensor_common.c

@@ -1,8 +1,8 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * sensor_common.c - utilities for tegra sensor drivers
  *
- * Copyright (c) 2017-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  */
 
 #include <media/sensor_common.h>
@@ -145,6 +145,16 @@ static int sensor_common_parse_signal_props(
 	else
 		signal->cil_settletime = value;
 
+	err = read_property_u32(node, "lane_polarity", &value);
+	/*
+	 * absence of this value is not an error and default behaviour is
+	 * no polarity swap on any CSI lane
+	 */
+	if (err)
+		signal->lane_polarity = 0;
+	else
+		signal->lane_polarity = value;
+
 	/* initialize default if this prop not available */
 	err = of_property_read_string(node, "discontinuous_clk", &temp_str);
 	if (!err)

include/media/tegra-v4l2-camera.h

@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * TEGRA_V4L2_CAMERA.h - utilities for tegra camera driver
+ * tegra-v4l2-camera.h - utilities for tegra camera driver
  *
- * Copyright (c) 2017-2022, NVIDIA Corporation.  All rights reserved.
+ * Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  */
 
 #ifndef __TEGRA_V4L2_CAMERA__
@@ -95,6 +95,7 @@ struct sensor_signal_properties {
 	__u32 mclk_freq;
 	union __u64val pixel_clock;
 	__u32 cil_settletime;
+	__u32 lane_polarity;
 	__u32 discontinuous_clk;
 	__u32 dpcm_enable;
 	__u32 tegra_sinterface;