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media: add ov5693 sensor driver
Add ov5693 camera sensor driver code, mode tables and makefile changes. Bug 3583587 Change-Id: Ib692c0a68cb893583c41da0d58bda0be80dd74e3 Signed-off-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2864554 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Semi Malinen <smalinen@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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include/uapi/media/nvc.h
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215
include/uapi/media/nvc.h
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@@ -0,0 +1,215 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#ifndef __UAPI_NVC_H__
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#define __UAPI_NVC_H__
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#define NVC_INT2FLOAT_DIVISOR_1K 1000
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#define NVC_INT2FLOAT_DIVISOR_1M 1000000
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#define NVC_INT2FLOAT_DIVISOR 1000
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struct nvc_param_32 {
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__u32 param;
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__u32 sizeofvalue;
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__u32 variant;
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__u32 p_value;
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} __packed;
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struct nvc_param {
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__u32 param;
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__u32 sizeofvalue;
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__u32 variant;
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unsigned long p_value;
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} __packed;
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enum nvc_params {
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NVC_PARAM_EXPOSURE = 0,
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NVC_PARAM_GAIN,
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NVC_PARAM_FRAMERATE,
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NVC_PARAM_MAX_FRAMERATE,
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NVC_PARAM_INPUT_CLOCK,
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NVC_PARAM_LOCUS,
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NVC_PARAM_FLASH_CAPS,
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NVC_PARAM_FLASH_LEVEL,
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NVC_PARAM_FLASH_PIN_STATE,
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NVC_PARAM_TORCH_CAPS,
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NVC_PARAM_TORCH_LEVEL,
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NVC_PARAM_FOCAL_LEN,
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NVC_PARAM_MAX_APERTURE,
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NVC_PARAM_FNUMBER,
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NVC_PARAM_EXPOSURE_LIMITS,
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NVC_PARAM_GAIN_LIMITS,
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NVC_PARAM_FRAMERATE_LIMITS,
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NVC_PARAM_FRAME_RATES,
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NVC_PARAM_CLOCK_LIMITS,
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NVC_PARAM_EXP_LATCH_TIME,
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NVC_PARAM_REGION_USED,
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NVC_PARAM_CALIBRATION_DATA,
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NVC_PARAM_CALIBRATION_OVERRIDES,
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NVC_PARAM_SELF_TEST,
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NVC_PARAM_STS,
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NVC_PARAM_TESTMODE,
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NVC_PARAM_EXPECTED_VALUES,
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NVC_PARAM_RESET,
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NVC_PARAM_OPTIMIZE_RES,
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NVC_PARAM_DETECT_COLOR_TEMP,
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NVC_PARAM_LINES_PER_SEC,
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NVC_PARAM_CAPS,
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NVC_PARAM_CUSTOM_BLOCK_INFO,
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NVC_PARAM_STEREO_CAP,
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NVC_PARAM_FOCUS_STEREO,
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NVC_PARAM_STEREO,
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NVC_PARAM_INHERENT_GAIN,
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NVC_PARAM_VIEW_ANGLE_H,
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NVC_PARAM_VIEW_ANGLE_V,
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NVC_PARAM_ISP_SETTING,
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NVC_PARAM_OPERATION_MODE,
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NVC_PARAM_SUPPORT_ISP,
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NVC_PARAM_AWB_LOCK,
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NVC_PARAM_AE_LOCK,
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NVC_PARAM_RES_CHANGE_WAIT_TIME,
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NVC_PARAM_FACTORY_CALIBRATION_DATA,
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NVC_PARAM_DEV_ID,
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NVC_PARAM_GROUP_HOLD,
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NVC_PARAM_SET_SENSOR_FLASH_MODE,
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NVC_PARAM_TORCH_QUERY,
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NVC_PARAM_FLASH_EXT_CAPS,
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NVC_PARAM_TORCH_EXT_CAPS,
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NVC_PARAM_BEGIN_VENDOR_EXTENSIONS = 0x10000000,
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NVC_PARAM_CALIBRATION_STATUS,
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NVC_PARAM_TEST_PATTERN,
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NVC_PARAM_MODULE_INFO,
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NVC_PARAM_FLASH_MAX_POWER,
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NVC_PARAM_DIRECTION,
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NVC_PARAM_SENSOR_TYPE,
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NVC_PARAM_DLI_CHECK,
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NVC_PARAM_PARALLEL_DLI_CHECK,
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NVC_PARAM_BRACKET_CAPS,
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NVC_PARAM_NUM,
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NVC_PARAM_I2C,
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NVC_PARAM_FEATURES,
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NVC_PARAM_FORCE32 = 0x7FFFFFFF
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};
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/* sync off */
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#define NVC_SYNC_OFF 0
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/* use only this device (the one receiving the call) */
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#define NVC_SYNC_MASTER 1
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/* use only the synced device (the "other" device) */
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#define NVC_SYNC_SLAVE 2
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/* use both synced devices at the same time */
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#define NVC_SYNC_STEREO 3
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#define NVC_RESET_HARD 0
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#define NVC_RESET_SOFT 1
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struct nvc_param_isp {
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int attr;
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void *p_data;
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__u32 data_size;
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} __packed;
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struct nvc_isp_focus_param {
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__s32 min_pos;
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__s32 max_pos;
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__s32 hyperfocal;
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__s32 macro;
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__s32 powersave;
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} __packed;
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struct nvc_isp_focus_pos {
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__u32 is_auto;
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__s32 value;
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} __packed;
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struct nvc_isp_focus_region {
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__u32 num_region;
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__s32 value;
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} __packed;
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enum nvc_params_isp {
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NVC_PARAM_ISP_FOCUS_CAF = 16389,
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NVC_PARAM_ISP_FOCUS_CAF_PAUSE,
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NVC_PARAM_ISP_FOCUS_CAF_STS,
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NVC_PARAM_ISP_FOCUS_POS = 16407,
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NVC_PARAM_ISP_FOCUS_RANGE,
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NVC_PARAM_ISP_FOCUS_AF_RGN = 16413,
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NVC_PARAM_ISP_FOCUS_AF_RGN_MASK,
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NVC_PARAM_ISP_FOCUS_AF_RGN_STS,
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NVC_PARAM_ISP_FOCUS_CTRL = 16424,
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NVC_PARAM_ISP_FOCUS_TRGR,
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NVC_PARAM_ISP_FOCUS_STS,
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};
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#define NVC_PARAM_ISP_FOCUS_STS_BUSY 0
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#define NVC_PARAM_ISP_FOCUS_STS_LOCKD 1
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#define NVC_PARAM_ISP_FOCUS_STS_FAILD 2
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#define NVC_PARAM_ISP_FOCUS_STS_ERR 3
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#define NVC_PARAM_ISP_FOCUS_CTRL_ON 0
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#define NVC_PARAM_ISP_FOCUS_CTRL_OFF 1
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#define NVC_PARAM_ISP_FOCUS_CTRL_AUTO 2
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#define NVC_PARAM_ISP_FOCUS_CTRL_ALOCK 3
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#define NVC_PARAM_ISP_FOCUS_CAF_CONVRG 1
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#define NVC_PARAM_ISP_FOCUS_CAF_SEARCH 2
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#define NVC_PARAM_ISP_FOCUS_POS_INF 0
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#define NVC_IOCTL_PWR_WR _IOW('o', 102, int)
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#define NVC_IOCTL_PWR_RD _IOW('o', 103, int)
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#define NVC_IOCTL_PARAM_WR _IOW('o', 104, struct nvc_param)
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#define NVC_IOCTL32_PARAM_WR _IOW('o', 104, struct nvc_param_32)
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#define NVC_IOCTL_PARAM_RD _IOWR('o', 105, struct nvc_param)
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#define NVC_IOCTL32_PARAM_RD _IOWR('o', 105, struct nvc_param_32)
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#define NVC_IOCTL_PARAM_ISP_RD _IOWR('o', 200, struct nvc_param_isp)
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#define NVC_IOCTL_PARAM_ISP_WR _IOWR('o', 201, struct nvc_param_isp)
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#define NVC_IOCTL_FUSE_ID _IOWR('o', 202, struct nvc_fuseid)
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#define NVC_IOCTL_SET_EEPROM_DATA _IOWR('o', 254, __u8 *)
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#define NVC_IOCTL_GET_EEPROM_DATA _IOWR('o', 255, __u8 *)
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/* Expected higher level power calls are:
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* 1 = OFF
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* 2 = STANDBY
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* 3 = ON
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* These will be multiplied by 2 before given to the driver's PM code that
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* uses the _PWR_ defines. This allows us to insert defines to give more power
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* granularity and still remain linear with regards to the power usage and
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* full power state transition latency for easy implementation of PM
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* algorithms.
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* The PM actions:
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* _PWR_ERR = Non-valid state.
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* _PWR_OFF_FORCE = _PWR_OFF is forced regardless of standby mechanisms.
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* _PWR_OFF = Device, regulators, clocks, etc is turned off. The longest
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* transition time to _PWR_ON is from this state.
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* _PWR_STDBY_OFF = Device is useless but powered. No communication possible.
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* Device does not retain programming. Main purpose is for
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* faster return to _PWR_ON without regulator delays.
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* _PWR_STDBY = Device is in standby. Device retains programming.
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* _PWR_COMM = Device is powered enough to communicate with the device.
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* _PWR_ON = Device is at full power with active output.
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*
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* The kernel drivers treat these calls as Guaranteed Level Of Service.
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*/
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#define NVC_PWR_ERR 0
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#define NVC_PWR_OFF_FORCE 1
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#define NVC_PWR_OFF 2
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#define NVC_PWR_STDBY_OFF 3
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#define NVC_PWR_STDBY 4
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#define NVC_PWR_COMM 5
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#define NVC_PWR_ON 6
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struct nvc_fuseid {
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__u32 size;
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__u8 data[16];
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};
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#endif /* __UAPI_NVC_H__ */
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245
include/uapi/media/nvc_image.h
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245
include/uapi/media/nvc_image.h
Normal file
@@ -0,0 +1,245 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#ifndef __UAPI_NVC_IMAGE_H__
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#define __UAPI_NVC_IMAGE_H__
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#define NVC_IMAGER_API_CAPS_VER 2
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#define NVC_IMAGER_API_STATIC_VER 1
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#define NVC_IMAGER_API_DYNAMIC_VER 1
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#define NVC_IMAGER_API_BAYER_VER 1
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#define NVC_IMAGER_TEST_NONE 0
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#define NVC_IMAGER_TEST_COLORBARS 1
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#define NVC_IMAGER_TEST_CHECKERBOARD 2
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#define NVC_IMAGER_TEST_WALKING1S 3
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#define NVC_IMAGER_CROPMODE_NONE 1
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#define NVC_IMAGER_CROPMODE_PARTIAL 2
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#define NVC_IMAGER_TYPE_HUH 0
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#define NVC_IMAGER_TYPE_RAW 1
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#define NVC_IMAGER_TYPE_SOC 2
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/**
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* Defines camera imager types.
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* Mirrors "NvOdmImagerRegion" in "imager/include/nvodm_imager.h".
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* These must remain in sync.
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*/
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#define NVC_IMAGER_SENSOR_INTERFACE_PARALLEL_8 1
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#define NVC_IMAGER_SENSOR_INTERFACE_PARALLEL_10 2
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#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_A 3
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#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_B 4
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#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_C 5
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#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_AB 6
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#define NVC_IMAGER_SENSOR_INTERFACE_CCIR 7
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#define NVC_IMAGER_SENSOR_INTERFACE_HOST 8
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#define NVC_IMAGER_SENSOR_INTERFACE_HOST_CSI_A 9
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#define NVC_IMAGER_SENSOR_INTERFACE_HOST_CSI_B 10
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#define NVC_IMAGER_SENSOR_INTERFACE_NUM 11
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#define NVC_IMAGER_IDENTIFIER_MAX 32
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#define NVC_IMAGER_FORMAT_MAX 4
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#define NVC_IMAGER_CLOCK_PROFILE_MAX 2
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#define NVC_IMAGER_CAPABILITIES_VERSION2 ((0x3434 << 16) | 2)
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#define NVC_IMAGER_INT2FLOAT_DIVISOR 1000
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#define NVC_FOCUS_INTERNAL (0x665F4E5643414D69ULL)
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#define NVC_FOCUS_GUID(n) (0x665F4E5643414D30ULL | ((n) & 0xF))
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#define NVC_TORCH_GUID(n) (0x6C5F4E5643414D30ULL | ((n) & 0xF))
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struct nvc_imager_static_nvc {
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__u32 api_version;
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__u32 sensor_type;
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__u32 bits_per_pixel;
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__u32 sensor_id;
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__u32 sensor_id_minor;
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__u32 focal_len;
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__u32 max_aperture;
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__u32 fnumber;
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__u32 view_angle_h;
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__u32 view_angle_v;
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__u32 stereo_cap;
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__u32 res_chg_wait_time;
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__u8 support_isp;
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__u8 align1;
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__u8 align2;
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__u8 align3;
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__u8 fuse_id[16];
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__u32 place_holder1;
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__u32 place_holder2;
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__u32 place_holder3;
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__u32 place_holder4;
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} __packed;
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struct nvc_imager_dynamic_nvc {
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__u32 api_version;
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__s32 region_start_x;
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__s32 region_start_y;
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__u32 x_scale;
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__u32 y_scale;
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__u32 bracket_caps;
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__u32 flush_count;
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__u32 init_intra_frame_skip;
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__u32 ss_intra_frame_skip;
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__u32 ss_frame_number;
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__u32 coarse_time;
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__u32 max_coarse_diff;
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__u32 min_exposure_course;
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__u32 max_exposure_course;
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__u32 diff_integration_time;
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__u32 line_length;
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__u32 frame_length;
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__u32 min_frame_length;
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__u32 max_frame_length;
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__u32 min_gain;
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__u32 max_gain;
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__u32 inherent_gain;
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__u32 inherent_gain_bin_en;
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__u8 support_bin_control;
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__u8 support_fast_mode;
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__u8 align2;
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__u8 align3;
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__u32 pll_mult;
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__u32 pll_div;
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__u32 mode_sw_wait_frames;
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__u32 place_holder1;
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__u32 place_holder2;
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__u32 place_holder3;
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} __packed;
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struct nvc_imager_bayer {
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__u32 api_version;
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__s32 res_x;
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__s32 res_y;
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__u32 frame_length;
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__u32 coarse_time;
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__u32 gain;
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__u8 bin_en;
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__u8 align1;
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__u8 align2;
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__u8 align3;
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__u32 place_holder1;
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__u32 place_holder2;
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__u32 place_holder3;
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__u32 place_holder4;
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} __packed;
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struct nvc_imager_mode {
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__s32 res_x;
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__s32 res_y;
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__s32 active_start_x;
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__s32 active_stary_y;
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__u32 peak_frame_rate;
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__u32 pixel_aspect_ratio;
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__u32 pll_multiplier;
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__u32 crop_mode;
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__u32 rect_left;
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__u32 rect_top;
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__u32 rect_right;
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__u32 rect_bottom;
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__u32 point_x;
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__u32 point_y;
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__u32 type;
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} __packed;
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struct nvc_imager_dnvc {
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__s32 res_x;
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__s32 res_y;
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struct nvc_imager_mode *p_mode;
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struct nvc_imager_dynamic_nvc *p_dnvc;
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} __packed;
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struct nvc_imager_mode_list {
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struct nvc_imager_mode *p_modes;
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__u32 *p_num_mode;
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} __packed;
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struct nvc_clock_profile {
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__u32 external_clock_khz;
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__u32 clock_multiplier;
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} __packed;
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struct nvc_imager_cap {
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char identifier[NVC_IMAGER_IDENTIFIER_MAX];
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__u32 sensor_nvc_interface;
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__u32 pixel_types[NVC_IMAGER_FORMAT_MAX];
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__u32 orientation;
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__u32 direction;
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__u32 initial_clock_rate_khz;
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struct nvc_clock_profile clock_profiles[NVC_IMAGER_CLOCK_PROFILE_MAX];
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__u32 h_sync_edge;
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__u32 v_sync_edge;
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__u32 mclk_on_vgp0;
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__u8 csi_port;
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__u8 data_lanes;
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__u8 virtual_channel_id;
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__u8 discontinuous_clk_mode;
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__u8 cil_threshold_settle;
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__u8 align1;
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__u8 align2;
|
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__u8 align3;
|
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__s32 min_blank_time_width;
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__s32 min_blank_time_height;
|
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__u32 preferred_mode_index;
|
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__u64 focuser_guid;
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__u64 torch_guid;
|
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__u32 cap_version;
|
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__u8 flash_control_enabled;
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__u8 adjustable_flash_timing;
|
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__u8 is_hdr;
|
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__u8 align5;
|
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} __packed;
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struct nvc_imager_ae {
|
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__u32 frame_length;
|
||||
__u8 frame_length_enable;
|
||||
__u32 coarse_time;
|
||||
__u8 coarse_time_enable;
|
||||
__u32 gain;
|
||||
__u8 gain_enable;
|
||||
} __packed;
|
||||
|
||||
union nvc_imager_flash_control {
|
||||
__u16 mode;
|
||||
struct {
|
||||
__u16 enable:1; /* enable the on-sensor flash control */
|
||||
__u16 edge_trig_en:1; /* two types of flash controls:
|
||||
* 0 - LED_FLASH_EN - supports continued
|
||||
* flash level only, doesn't
|
||||
* support start edge/repeat/dly.
|
||||
* 1 - FLASH_EN - supports control pulse
|
||||
* control pulse attributes are
|
||||
* defined below.
|
||||
*/
|
||||
__u16 start_edge:1; /* flash control pulse rise position:
|
||||
* 0 - at the start of the next frame.
|
||||
* 1 - at the effective pixel end
|
||||
* position of the next frame.
|
||||
*/
|
||||
__u16 repeat:1; /* flash control pulse repeat:
|
||||
* 0 - only triggers one frame.
|
||||
* 1 - trigger repeats every frame until
|
||||
* Flash_EN = 0.
|
||||
*/
|
||||
__u16 delay_frm:2; /* flash control pulse can be delayed
|
||||
* in frame units: (0 - 3) - frame
|
||||
* numbers the pulse is delayed.
|
||||
*/
|
||||
} settings;
|
||||
};
|
||||
|
||||
#define NVC_IOCTL_CAPS_RD _IOWR('o', 106, struct nvc_imager_cap)
|
||||
#define NVC_IOCTL_MODE_WR _IOW('o', 107, struct nvc_imager_bayer)
|
||||
#define NVC_IOCTL_MODE_RD _IOWR('o', 108, struct nvc_imager_mode_list)
|
||||
#define NVC_IOCTL_STATIC_RD _IOWR('o', 109, struct nvc_imager_static_nvc)
|
||||
#define NVC_IOCTL_DYNAMIC_RD _IOWR('o', 110, struct nvc_imager_dnvc)
|
||||
|
||||
#endif /* __UAPI_NVC_IMAGE_H__ */
|
||||
104
include/uapi/media/ov5693.h
Normal file
104
include/uapi/media/ov5693.h
Normal file
@@ -0,0 +1,104 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __UAPI_OV5693_H__
|
||||
#define __UAPI_OV5693_H__
|
||||
|
||||
#include <media/nvc.h>
|
||||
#include "nvc_image.h"
|
||||
|
||||
#define OV5693_IOCTL_SET_MODE _IOW('o', 1, struct ov5693_mode)
|
||||
#define OV5693_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32)
|
||||
#define OV5693_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32)
|
||||
#define OV5693_IOCTL_SET_GAIN _IOW('o', 4, __u16)
|
||||
#define OV5693_IOCTL_GET_STATUS _IOR('o', 5, __u8)
|
||||
#define OV5693_IOCTL_SET_BINNING _IOW('o', 6, __u8)
|
||||
#define OV5693_IOCTL_TEST_PATTERN _IOW('o', 7, \
|
||||
enum ov5693_test_pattern)
|
||||
#define OV5693_IOCTL_SET_GROUP_HOLD _IOW('o', 8, struct ov5693_ae)
|
||||
/*
|
||||
* IOCTL to set the operating mode of camera.
|
||||
* This can be either stereo , leftOnly or rightOnly
|
||||
*/
|
||||
#define OV5693_IOCTL_SET_CAMERA_MODE _IOW('o', 10, __u32)
|
||||
#define OV5693_IOCTL_SYNC_SENSORS _IOW('o', 11, __u32)
|
||||
#define OV5693_IOCTL_GET_FUSEID _IOR('o', 12, struct nvc_fuseid)
|
||||
#define OV5693_IOCTL_SET_HDR_COARSE_TIME _IOW('o', 13, struct ov5693_hdr)
|
||||
#define OV5693_IOCTL_READ_OTP_BANK _IOWR('o', 14, \
|
||||
struct ov5693_otp_bank)
|
||||
#define OV5693_IOCTL_SET_CAL_DATA _IOW('o', 15, \
|
||||
struct ov5693_cal_data)
|
||||
#define OV5693_IOCTL_GET_EEPROM_DATA _IOR('o', 20, __u8 *)
|
||||
#define OV5693_IOCTL_SET_EEPROM_DATA _IOW('o', 21, __u8 *)
|
||||
#define OV5693_IOCTL_GET_CAPS _IOR('o', 22, struct nvc_imager_cap)
|
||||
#define OV5693_IOCTL_SET_POWER _IOW('o', 23, __u32)
|
||||
|
||||
#define OV5693_FUSE_ID_OTP_START_ADDR 0x3D00
|
||||
#define OV5693_FUSE_ID_OTP_BANK 0
|
||||
#define OV5693_FUSE_ID_SIZE 8
|
||||
#define OV5693_FUSE_ID_STR_SIZE (OV5693_FUSE_ID_SIZE * 2)
|
||||
|
||||
#define OV5693_FRAME_LENGTH_ADDR_MSB 0x380E
|
||||
#define OV5693_FRAME_LENGTH_ADDR_LSB 0x380F
|
||||
#define OV5693_COARSE_TIME_ADDR_1 0x3500
|
||||
#define OV5693_COARSE_TIME_ADDR_2 0x3501
|
||||
#define OV5693_COARSE_TIME_ADDR_3 0x3502
|
||||
#define OV5693_COARSE_TIME_SHORT_ADDR_1 0x3506
|
||||
#define OV5693_COARSE_TIME_SHORT_ADDR_2 0x3507
|
||||
#define OV5693_COARSE_TIME_SHORT_ADDR_3 0x3508
|
||||
#define OV5693_GAIN_ADDR_MSB 0x350A
|
||||
#define OV5693_GAIN_ADDR_LSB 0x350B
|
||||
#define OV5693_GROUP_HOLD_ADDR 0x3208
|
||||
#define OV5693_TIMING_REG20 0x3820
|
||||
#define VERTICAL_FLIP ((0x1 << 1) | (0x1 << 6))
|
||||
#define OV5693_TIMING_REG21 0x3821
|
||||
#define HORIZONTAL_MIRROR_MASK (0x3 << 1)
|
||||
|
||||
struct ov5693_mode {
|
||||
int res_x;
|
||||
int res_y;
|
||||
int fps;
|
||||
__u32 frame_length;
|
||||
__u32 coarse_time;
|
||||
__u32 coarse_time_short;
|
||||
__u16 gain;
|
||||
__u8 hdr_en;
|
||||
};
|
||||
|
||||
struct ov5693_ae {
|
||||
__u32 frame_length;
|
||||
__u8 frame_length_enable;
|
||||
__u32 coarse_time;
|
||||
__u32 coarse_time_short;
|
||||
__u8 coarse_time_enable;
|
||||
__s32 gain;
|
||||
__u8 gain_enable;
|
||||
};
|
||||
|
||||
struct ov5693_fuseid {
|
||||
__u32 size;
|
||||
__u8 id[16];
|
||||
};
|
||||
|
||||
struct ov5693_hdr {
|
||||
__u32 coarse_time_long;
|
||||
__u32 coarse_time_short;
|
||||
};
|
||||
|
||||
struct ov5693_otp_bank {
|
||||
__u32 id;
|
||||
__u8 buf[16];
|
||||
};
|
||||
|
||||
struct ov5693_cal_data {
|
||||
int loaded;
|
||||
int rg_ratio;
|
||||
int bg_ratio;
|
||||
int rg_ratio_typical;
|
||||
int bg_ratio_typical;
|
||||
__u8 lenc[62];
|
||||
};
|
||||
|
||||
#endif /* __UAPI_OV5693_H__ */
|
||||
Reference in New Issue
Block a user