mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 17:25:35 +03:00
media: add ov5693 sensor driver
Add ov5693 camera sensor driver code, mode tables and makefile changes. Bug 3583587 Change-Id: Ib692c0a68cb893583c41da0d58bda0be80dd74e3 Signed-off-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2864554 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Semi Malinen <smalinen@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Ankur Pawar
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@@ -5,3 +5,4 @@ subdir-ccflags-y += -Werror
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obj-m += nv_imx185.o
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obj-m += nv_imx185.o
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obj-m += nv_imx274.o
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obj-m += nv_imx274.o
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obj-m += nv_ov5693.o
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1276
drivers/media/i2c/nv_ov5693.c
Normal file
1276
drivers/media/i2c/nv_ov5693.c
Normal file
File diff suppressed because it is too large
Load Diff
2390
drivers/media/i2c/ov5693_mode_tbls.h
Normal file
2390
drivers/media/i2c/ov5693_mode_tbls.h
Normal file
File diff suppressed because it is too large
Load Diff
91
include/media/nvc.h
Normal file
91
include/media/nvc.h
Normal file
@@ -0,0 +1,91 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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*/
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#ifndef __NVC_H__
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#define __NVC_H__
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#include <linux/regulator/consumer.h>
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#include <uapi/media/nvc.h>
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#define MAKE_CONSTUSER_PTR(p) ((const void __user *)((unsigned long)(p)))
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#define MAKE_USER_PTR(p) ((void __user *)((unsigned long)(p)))
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/* The NVC_CFG_ defines are for the .cfg entry in the
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* platform data structure.
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*/
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/* Device not registered if not found */
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#define NVC_CFG_NODEV (1 << 0)
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/* Don't return errors */
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#define NVC_CFG_NOERR (1 << 1)
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/* Always go to _PWR_STDBY instead of _PWR_OFF */
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#define NVC_CFG_OFF2STDBY (1 << 2)
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/* Init device at sys boot */
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#define NVC_CFG_BOOT_INIT (1 << 3)
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/* Sync mode uses an I2C MUX to send at same time */
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#define NVC_CFG_SYNC_I2C_MUX (1 << 4)
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struct nvc_regulator_init {
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unsigned int vreg_num;
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const char *vreg_name;
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};
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struct nvc_regulator {
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bool vreg_flag;
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struct regulator *vreg;
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const char *vreg_name;
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};
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/* The GPIO mechanism uses the _gpio_type in the device's header file as a key
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* to define all the possible GPIO's the device will need. The key is used to
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* combine the GPIO's defined in the platform board file using the
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* nvc_gpio_pdata structure with the nvc_gpio structure in the nvc kernel
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* driver.
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*/
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struct nvc_gpio_pdata {
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/* use a _gpio_type enum from the device's header file */
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unsigned int gpio_type;
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/* the GPIO system number */
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unsigned int gpio;
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/* init_en is typically set to true for all GPIO's used by the driver.
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* However, some GPIO's are used by multiple drivers (CSI MUX, reset,
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* etc.). In this case, this is set true for only one of the drivers
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* that uses the GPIO and false for the others. If the platform board
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* file initializes the GPIO, then this is false for all of the drivers
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* using the GPIO.
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*/
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bool init_en;
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/* this defines the assert level for the general purpose GPIO's
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* (_GPIO_TYPE_GPx, etc.). The _GPIO_TYPE_GPx can be used for a GPIO
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* that the driver doesn't know about but is needed in order for the
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* device to work (CSI select, regulator, etc.). The driver will
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* blindly assert the GPIO when the device is operational and deassert
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* when the device is turned off.
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*/
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bool active_high;
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};
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struct nvc_gpio_init {
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/* key to match in nvc_gpio_pdata */
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unsigned int gpio_type;
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/* same as in gpio.h */
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unsigned long flags;
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/* same as in gpio.h */
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const char *label;
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/* used instead of nvc_gpio_pdata.active_high if use_flags true */
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bool active_high;
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/* false if nvc_gpio_pdata.active_high used else flags is used */
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bool use_flags;
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};
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struct nvc_gpio {
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unsigned int gpio; /* system GPIO number */
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bool own; /* gets set if driver initializes */
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bool active_high; /* used for GP GPIOs */
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bool valid; /* set if struct data is valid */
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bool flag; /* scratch flag for driver implementation */
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};
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#endif /* __NVC_H__ */
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59
include/media/ov5693.h
Normal file
59
include/media/ov5693.h
Normal file
@@ -0,0 +1,59 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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*/
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#ifndef __OV5693_H__
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#define __OV5693_H__
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#include <media/nvc.h>
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#include <uapi/media/nvc_image.h>
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#include <uapi/media/ov5693.h>
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#define OV5693_INVALID_COARSE_TIME -1
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#define OV5693_EEPROM_ADDRESS 0x54
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#define OV5693_EEPROM_SIZE 1024
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#define OV5693_EEPROM_STR_SIZE (OV5693_EEPROM_SIZE * 2)
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#define OV5693_EEPROM_BLOCK_SIZE (1 << 8)
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#define OV5693_EEPROM_NUM_BLOCKS \
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(OV5693_EEPROM_SIZE / OV5693_EEPROM_BLOCK_SIZE)
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#define OV5693_OTP_LOAD_CTRL_ADDR 0x3D81
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#define OV5693_OTP_BANK_SELECT_ADDR 0x3D84
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#define OV5693_OTP_BANK_START_ADDR 0x3D00
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#define OV5693_OTP_BANK_END_ADDR 0x3D0F
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#define OV5693_OTP_NUM_BANKS (32)
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#define OV5693_OTP_BANK_SIZE \
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(OV5693_OTP_BANK_END_ADDR - OV5693_OTP_BANK_START_ADDR + 1)
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#define OV5693_OTP_SIZE \
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(OV5693_OTP_BANK_SIZE * OV5693_OTP_NUM_BANKS)
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#define OV5693_OTP_STR_SIZE (OV5693_OTP_SIZE * 2)
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/* See notes in the nvc.h file on the GPIO usage */
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enum ov5693_gpio_type {
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OV5693_GPIO_TYPE_PWRDN = 0,
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OV5693_GPIO_TYPE_RESET,
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};
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struct ov5693_eeprom_data {
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struct i2c_client *i2c_client;
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struct i2c_adapter *adap;
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struct i2c_board_info brd;
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struct regmap *regmap;
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};
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struct ov5693_power_rail {
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struct regulator *dvdd;
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struct regulator *avdd;
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struct regulator *dovdd;
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};
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struct ov5693_regulators {
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const char *avdd;
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const char *dvdd;
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const char *dovdd;
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};
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#endif /* __OV5693_H__ */
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37
include/trace/events/ov5693.h
Normal file
37
include/trace/events/ov5693.h
Normal file
@@ -0,0 +1,37 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* ov5693.h
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*
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*/
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#undef TRACE_SYSTEM
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#define TRACE_SYSTEM ov5693
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#if !defined(_TRACE_OV5693_H) || defined(TRACE_HEADER_MULTI_READ)
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#define _TRACE_OV5693_H
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#include <linux/tracepoint.h>
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TRACE_EVENT(ov5693_s_stream,
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TP_PROTO(const char *name, int enable, int mode),
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TP_ARGS(name, enable, mode),
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TP_STRUCT__entry(
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__string(name, name)
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__field(int, enable)
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__field(int, mode)
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),
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TP_fast_assign(
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__assign_str(name, name);
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__entry->enable = enable;
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__entry->mode = mode;
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),
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TP_printk("%s: on %d mode %d", __get_str(name),
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__entry->enable, __entry->mode)
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);
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#endif
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/* This part must be outside protection */
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#include <trace/define_trace.h>
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215
include/uapi/media/nvc.h
Normal file
215
include/uapi/media/nvc.h
Normal file
@@ -0,0 +1,215 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#ifndef __UAPI_NVC_H__
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#define __UAPI_NVC_H__
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#define NVC_INT2FLOAT_DIVISOR_1K 1000
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#define NVC_INT2FLOAT_DIVISOR_1M 1000000
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#define NVC_INT2FLOAT_DIVISOR 1000
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struct nvc_param_32 {
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__u32 param;
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__u32 sizeofvalue;
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__u32 variant;
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__u32 p_value;
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} __packed;
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struct nvc_param {
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__u32 param;
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__u32 sizeofvalue;
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__u32 variant;
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unsigned long p_value;
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} __packed;
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enum nvc_params {
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NVC_PARAM_EXPOSURE = 0,
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NVC_PARAM_GAIN,
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NVC_PARAM_FRAMERATE,
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NVC_PARAM_MAX_FRAMERATE,
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NVC_PARAM_INPUT_CLOCK,
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NVC_PARAM_LOCUS,
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NVC_PARAM_FLASH_CAPS,
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NVC_PARAM_FLASH_LEVEL,
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NVC_PARAM_FLASH_PIN_STATE,
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NVC_PARAM_TORCH_CAPS,
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NVC_PARAM_TORCH_LEVEL,
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NVC_PARAM_FOCAL_LEN,
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NVC_PARAM_MAX_APERTURE,
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NVC_PARAM_FNUMBER,
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NVC_PARAM_EXPOSURE_LIMITS,
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NVC_PARAM_GAIN_LIMITS,
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NVC_PARAM_FRAMERATE_LIMITS,
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NVC_PARAM_FRAME_RATES,
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NVC_PARAM_CLOCK_LIMITS,
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NVC_PARAM_EXP_LATCH_TIME,
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NVC_PARAM_REGION_USED,
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NVC_PARAM_CALIBRATION_DATA,
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NVC_PARAM_CALIBRATION_OVERRIDES,
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NVC_PARAM_SELF_TEST,
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NVC_PARAM_STS,
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NVC_PARAM_TESTMODE,
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NVC_PARAM_EXPECTED_VALUES,
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NVC_PARAM_RESET,
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NVC_PARAM_OPTIMIZE_RES,
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NVC_PARAM_DETECT_COLOR_TEMP,
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NVC_PARAM_LINES_PER_SEC,
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NVC_PARAM_CAPS,
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NVC_PARAM_CUSTOM_BLOCK_INFO,
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NVC_PARAM_STEREO_CAP,
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NVC_PARAM_FOCUS_STEREO,
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NVC_PARAM_STEREO,
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NVC_PARAM_INHERENT_GAIN,
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NVC_PARAM_VIEW_ANGLE_H,
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NVC_PARAM_VIEW_ANGLE_V,
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NVC_PARAM_ISP_SETTING,
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NVC_PARAM_OPERATION_MODE,
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NVC_PARAM_SUPPORT_ISP,
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NVC_PARAM_AWB_LOCK,
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NVC_PARAM_AE_LOCK,
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NVC_PARAM_RES_CHANGE_WAIT_TIME,
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NVC_PARAM_FACTORY_CALIBRATION_DATA,
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NVC_PARAM_DEV_ID,
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NVC_PARAM_GROUP_HOLD,
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NVC_PARAM_SET_SENSOR_FLASH_MODE,
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NVC_PARAM_TORCH_QUERY,
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NVC_PARAM_FLASH_EXT_CAPS,
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NVC_PARAM_TORCH_EXT_CAPS,
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NVC_PARAM_BEGIN_VENDOR_EXTENSIONS = 0x10000000,
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NVC_PARAM_CALIBRATION_STATUS,
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NVC_PARAM_TEST_PATTERN,
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NVC_PARAM_MODULE_INFO,
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NVC_PARAM_FLASH_MAX_POWER,
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NVC_PARAM_DIRECTION,
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NVC_PARAM_SENSOR_TYPE,
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NVC_PARAM_DLI_CHECK,
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NVC_PARAM_PARALLEL_DLI_CHECK,
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NVC_PARAM_BRACKET_CAPS,
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NVC_PARAM_NUM,
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NVC_PARAM_I2C,
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NVC_PARAM_FEATURES,
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NVC_PARAM_FORCE32 = 0x7FFFFFFF
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};
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/* sync off */
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#define NVC_SYNC_OFF 0
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/* use only this device (the one receiving the call) */
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#define NVC_SYNC_MASTER 1
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/* use only the synced device (the "other" device) */
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#define NVC_SYNC_SLAVE 2
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/* use both synced devices at the same time */
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#define NVC_SYNC_STEREO 3
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#define NVC_RESET_HARD 0
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#define NVC_RESET_SOFT 1
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struct nvc_param_isp {
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int attr;
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void *p_data;
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__u32 data_size;
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} __packed;
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struct nvc_isp_focus_param {
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__s32 min_pos;
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__s32 max_pos;
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__s32 hyperfocal;
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__s32 macro;
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__s32 powersave;
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} __packed;
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struct nvc_isp_focus_pos {
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__u32 is_auto;
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__s32 value;
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} __packed;
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struct nvc_isp_focus_region {
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__u32 num_region;
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__s32 value;
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} __packed;
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enum nvc_params_isp {
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NVC_PARAM_ISP_FOCUS_CAF = 16389,
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NVC_PARAM_ISP_FOCUS_CAF_PAUSE,
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NVC_PARAM_ISP_FOCUS_CAF_STS,
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NVC_PARAM_ISP_FOCUS_POS = 16407,
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NVC_PARAM_ISP_FOCUS_RANGE,
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NVC_PARAM_ISP_FOCUS_AF_RGN = 16413,
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NVC_PARAM_ISP_FOCUS_AF_RGN_MASK,
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NVC_PARAM_ISP_FOCUS_AF_RGN_STS,
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NVC_PARAM_ISP_FOCUS_CTRL = 16424,
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NVC_PARAM_ISP_FOCUS_TRGR,
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NVC_PARAM_ISP_FOCUS_STS,
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};
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#define NVC_PARAM_ISP_FOCUS_STS_BUSY 0
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#define NVC_PARAM_ISP_FOCUS_STS_LOCKD 1
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||||||
|
#define NVC_PARAM_ISP_FOCUS_STS_FAILD 2
|
||||||
|
#define NVC_PARAM_ISP_FOCUS_STS_ERR 3
|
||||||
|
|
||||||
|
#define NVC_PARAM_ISP_FOCUS_CTRL_ON 0
|
||||||
|
#define NVC_PARAM_ISP_FOCUS_CTRL_OFF 1
|
||||||
|
#define NVC_PARAM_ISP_FOCUS_CTRL_AUTO 2
|
||||||
|
#define NVC_PARAM_ISP_FOCUS_CTRL_ALOCK 3
|
||||||
|
|
||||||
|
#define NVC_PARAM_ISP_FOCUS_CAF_CONVRG 1
|
||||||
|
#define NVC_PARAM_ISP_FOCUS_CAF_SEARCH 2
|
||||||
|
|
||||||
|
#define NVC_PARAM_ISP_FOCUS_POS_INF 0
|
||||||
|
|
||||||
|
|
||||||
|
#define NVC_IOCTL_PWR_WR _IOW('o', 102, int)
|
||||||
|
#define NVC_IOCTL_PWR_RD _IOW('o', 103, int)
|
||||||
|
#define NVC_IOCTL_PARAM_WR _IOW('o', 104, struct nvc_param)
|
||||||
|
#define NVC_IOCTL32_PARAM_WR _IOW('o', 104, struct nvc_param_32)
|
||||||
|
#define NVC_IOCTL_PARAM_RD _IOWR('o', 105, struct nvc_param)
|
||||||
|
#define NVC_IOCTL32_PARAM_RD _IOWR('o', 105, struct nvc_param_32)
|
||||||
|
#define NVC_IOCTL_PARAM_ISP_RD _IOWR('o', 200, struct nvc_param_isp)
|
||||||
|
#define NVC_IOCTL_PARAM_ISP_WR _IOWR('o', 201, struct nvc_param_isp)
|
||||||
|
#define NVC_IOCTL_FUSE_ID _IOWR('o', 202, struct nvc_fuseid)
|
||||||
|
#define NVC_IOCTL_SET_EEPROM_DATA _IOWR('o', 254, __u8 *)
|
||||||
|
#define NVC_IOCTL_GET_EEPROM_DATA _IOWR('o', 255, __u8 *)
|
||||||
|
|
||||||
|
/* Expected higher level power calls are:
|
||||||
|
* 1 = OFF
|
||||||
|
* 2 = STANDBY
|
||||||
|
* 3 = ON
|
||||||
|
* These will be multiplied by 2 before given to the driver's PM code that
|
||||||
|
* uses the _PWR_ defines. This allows us to insert defines to give more power
|
||||||
|
* granularity and still remain linear with regards to the power usage and
|
||||||
|
* full power state transition latency for easy implementation of PM
|
||||||
|
* algorithms.
|
||||||
|
* The PM actions:
|
||||||
|
* _PWR_ERR = Non-valid state.
|
||||||
|
* _PWR_OFF_FORCE = _PWR_OFF is forced regardless of standby mechanisms.
|
||||||
|
* _PWR_OFF = Device, regulators, clocks, etc is turned off. The longest
|
||||||
|
* transition time to _PWR_ON is from this state.
|
||||||
|
* _PWR_STDBY_OFF = Device is useless but powered. No communication possible.
|
||||||
|
* Device does not retain programming. Main purpose is for
|
||||||
|
* faster return to _PWR_ON without regulator delays.
|
||||||
|
* _PWR_STDBY = Device is in standby. Device retains programming.
|
||||||
|
* _PWR_COMM = Device is powered enough to communicate with the device.
|
||||||
|
* _PWR_ON = Device is at full power with active output.
|
||||||
|
*
|
||||||
|
* The kernel drivers treat these calls as Guaranteed Level Of Service.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define NVC_PWR_ERR 0
|
||||||
|
#define NVC_PWR_OFF_FORCE 1
|
||||||
|
#define NVC_PWR_OFF 2
|
||||||
|
#define NVC_PWR_STDBY_OFF 3
|
||||||
|
#define NVC_PWR_STDBY 4
|
||||||
|
#define NVC_PWR_COMM 5
|
||||||
|
#define NVC_PWR_ON 6
|
||||||
|
|
||||||
|
struct nvc_fuseid {
|
||||||
|
__u32 size;
|
||||||
|
__u8 data[16];
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* __UAPI_NVC_H__ */
|
||||||
|
|
||||||
245
include/uapi/media/nvc_image.h
Normal file
245
include/uapi/media/nvc_image.h
Normal file
@@ -0,0 +1,245 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __UAPI_NVC_IMAGE_H__
|
||||||
|
#define __UAPI_NVC_IMAGE_H__
|
||||||
|
|
||||||
|
#include <linux/ioctl.h>
|
||||||
|
#include <linux/types.h>
|
||||||
|
|
||||||
|
#define NVC_IMAGER_API_CAPS_VER 2
|
||||||
|
#define NVC_IMAGER_API_STATIC_VER 1
|
||||||
|
#define NVC_IMAGER_API_DYNAMIC_VER 1
|
||||||
|
#define NVC_IMAGER_API_BAYER_VER 1
|
||||||
|
|
||||||
|
#define NVC_IMAGER_TEST_NONE 0
|
||||||
|
#define NVC_IMAGER_TEST_COLORBARS 1
|
||||||
|
#define NVC_IMAGER_TEST_CHECKERBOARD 2
|
||||||
|
#define NVC_IMAGER_TEST_WALKING1S 3
|
||||||
|
|
||||||
|
#define NVC_IMAGER_CROPMODE_NONE 1
|
||||||
|
#define NVC_IMAGER_CROPMODE_PARTIAL 2
|
||||||
|
|
||||||
|
#define NVC_IMAGER_TYPE_HUH 0
|
||||||
|
#define NVC_IMAGER_TYPE_RAW 1
|
||||||
|
#define NVC_IMAGER_TYPE_SOC 2
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Defines camera imager types.
|
||||||
|
* Mirrors "NvOdmImagerRegion" in "imager/include/nvodm_imager.h".
|
||||||
|
* These must remain in sync.
|
||||||
|
*/
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_PARALLEL_8 1
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_PARALLEL_10 2
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_A 3
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_B 4
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_C 5
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_AB 6
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_CCIR 7
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_HOST 8
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_HOST_CSI_A 9
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_HOST_CSI_B 10
|
||||||
|
#define NVC_IMAGER_SENSOR_INTERFACE_NUM 11
|
||||||
|
|
||||||
|
#define NVC_IMAGER_IDENTIFIER_MAX 32
|
||||||
|
#define NVC_IMAGER_FORMAT_MAX 4
|
||||||
|
#define NVC_IMAGER_CLOCK_PROFILE_MAX 2
|
||||||
|
#define NVC_IMAGER_CAPABILITIES_VERSION2 ((0x3434 << 16) | 2)
|
||||||
|
|
||||||
|
#define NVC_IMAGER_INT2FLOAT_DIVISOR 1000
|
||||||
|
|
||||||
|
#define NVC_FOCUS_INTERNAL (0x665F4E5643414D69ULL)
|
||||||
|
#define NVC_FOCUS_GUID(n) (0x665F4E5643414D30ULL | ((n) & 0xF))
|
||||||
|
#define NVC_TORCH_GUID(n) (0x6C5F4E5643414D30ULL | ((n) & 0xF))
|
||||||
|
|
||||||
|
|
||||||
|
struct nvc_imager_static_nvc {
|
||||||
|
__u32 api_version;
|
||||||
|
__u32 sensor_type;
|
||||||
|
__u32 bits_per_pixel;
|
||||||
|
__u32 sensor_id;
|
||||||
|
__u32 sensor_id_minor;
|
||||||
|
__u32 focal_len;
|
||||||
|
__u32 max_aperture;
|
||||||
|
__u32 fnumber;
|
||||||
|
__u32 view_angle_h;
|
||||||
|
__u32 view_angle_v;
|
||||||
|
__u32 stereo_cap;
|
||||||
|
__u32 res_chg_wait_time;
|
||||||
|
__u8 support_isp;
|
||||||
|
__u8 align1;
|
||||||
|
__u8 align2;
|
||||||
|
__u8 align3;
|
||||||
|
__u8 fuse_id[16];
|
||||||
|
__u32 place_holder1;
|
||||||
|
__u32 place_holder2;
|
||||||
|
__u32 place_holder3;
|
||||||
|
__u32 place_holder4;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
struct nvc_imager_dynamic_nvc {
|
||||||
|
__u32 api_version;
|
||||||
|
__s32 region_start_x;
|
||||||
|
__s32 region_start_y;
|
||||||
|
__u32 x_scale;
|
||||||
|
__u32 y_scale;
|
||||||
|
__u32 bracket_caps;
|
||||||
|
__u32 flush_count;
|
||||||
|
__u32 init_intra_frame_skip;
|
||||||
|
__u32 ss_intra_frame_skip;
|
||||||
|
__u32 ss_frame_number;
|
||||||
|
__u32 coarse_time;
|
||||||
|
__u32 max_coarse_diff;
|
||||||
|
__u32 min_exposure_course;
|
||||||
|
__u32 max_exposure_course;
|
||||||
|
__u32 diff_integration_time;
|
||||||
|
__u32 line_length;
|
||||||
|
__u32 frame_length;
|
||||||
|
__u32 min_frame_length;
|
||||||
|
__u32 max_frame_length;
|
||||||
|
__u32 min_gain;
|
||||||
|
__u32 max_gain;
|
||||||
|
__u32 inherent_gain;
|
||||||
|
__u32 inherent_gain_bin_en;
|
||||||
|
__u8 support_bin_control;
|
||||||
|
__u8 support_fast_mode;
|
||||||
|
__u8 align2;
|
||||||
|
__u8 align3;
|
||||||
|
__u32 pll_mult;
|
||||||
|
__u32 pll_div;
|
||||||
|
__u32 mode_sw_wait_frames;
|
||||||
|
__u32 place_holder1;
|
||||||
|
__u32 place_holder2;
|
||||||
|
__u32 place_holder3;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
struct nvc_imager_bayer {
|
||||||
|
__u32 api_version;
|
||||||
|
__s32 res_x;
|
||||||
|
__s32 res_y;
|
||||||
|
__u32 frame_length;
|
||||||
|
__u32 coarse_time;
|
||||||
|
__u32 gain;
|
||||||
|
__u8 bin_en;
|
||||||
|
__u8 align1;
|
||||||
|
__u8 align2;
|
||||||
|
__u8 align3;
|
||||||
|
__u32 place_holder1;
|
||||||
|
__u32 place_holder2;
|
||||||
|
__u32 place_holder3;
|
||||||
|
__u32 place_holder4;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
struct nvc_imager_mode {
|
||||||
|
__s32 res_x;
|
||||||
|
__s32 res_y;
|
||||||
|
__s32 active_start_x;
|
||||||
|
__s32 active_stary_y;
|
||||||
|
__u32 peak_frame_rate;
|
||||||
|
__u32 pixel_aspect_ratio;
|
||||||
|
__u32 pll_multiplier;
|
||||||
|
__u32 crop_mode;
|
||||||
|
__u32 rect_left;
|
||||||
|
__u32 rect_top;
|
||||||
|
__u32 rect_right;
|
||||||
|
__u32 rect_bottom;
|
||||||
|
__u32 point_x;
|
||||||
|
__u32 point_y;
|
||||||
|
__u32 type;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
struct nvc_imager_dnvc {
|
||||||
|
__s32 res_x;
|
||||||
|
__s32 res_y;
|
||||||
|
struct nvc_imager_mode *p_mode;
|
||||||
|
struct nvc_imager_dynamic_nvc *p_dnvc;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
struct nvc_imager_mode_list {
|
||||||
|
struct nvc_imager_mode *p_modes;
|
||||||
|
__u32 *p_num_mode;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
struct nvc_clock_profile {
|
||||||
|
__u32 external_clock_khz;
|
||||||
|
__u32 clock_multiplier;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
struct nvc_imager_cap {
|
||||||
|
char identifier[NVC_IMAGER_IDENTIFIER_MAX];
|
||||||
|
__u32 sensor_nvc_interface;
|
||||||
|
__u32 pixel_types[NVC_IMAGER_FORMAT_MAX];
|
||||||
|
__u32 orientation;
|
||||||
|
__u32 direction;
|
||||||
|
__u32 initial_clock_rate_khz;
|
||||||
|
struct nvc_clock_profile clock_profiles[NVC_IMAGER_CLOCK_PROFILE_MAX];
|
||||||
|
__u32 h_sync_edge;
|
||||||
|
__u32 v_sync_edge;
|
||||||
|
__u32 mclk_on_vgp0;
|
||||||
|
__u8 csi_port;
|
||||||
|
__u8 data_lanes;
|
||||||
|
__u8 virtual_channel_id;
|
||||||
|
__u8 discontinuous_clk_mode;
|
||||||
|
__u8 cil_threshold_settle;
|
||||||
|
__u8 align1;
|
||||||
|
__u8 align2;
|
||||||
|
__u8 align3;
|
||||||
|
__s32 min_blank_time_width;
|
||||||
|
__s32 min_blank_time_height;
|
||||||
|
__u32 preferred_mode_index;
|
||||||
|
__u64 focuser_guid;
|
||||||
|
__u64 torch_guid;
|
||||||
|
__u32 cap_version;
|
||||||
|
__u8 flash_control_enabled;
|
||||||
|
__u8 adjustable_flash_timing;
|
||||||
|
__u8 is_hdr;
|
||||||
|
__u8 align5;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
struct nvc_imager_ae {
|
||||||
|
__u32 frame_length;
|
||||||
|
__u8 frame_length_enable;
|
||||||
|
__u32 coarse_time;
|
||||||
|
__u8 coarse_time_enable;
|
||||||
|
__u32 gain;
|
||||||
|
__u8 gain_enable;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
union nvc_imager_flash_control {
|
||||||
|
__u16 mode;
|
||||||
|
struct {
|
||||||
|
__u16 enable:1; /* enable the on-sensor flash control */
|
||||||
|
__u16 edge_trig_en:1; /* two types of flash controls:
|
||||||
|
* 0 - LED_FLASH_EN - supports continued
|
||||||
|
* flash level only, doesn't
|
||||||
|
* support start edge/repeat/dly.
|
||||||
|
* 1 - FLASH_EN - supports control pulse
|
||||||
|
* control pulse attributes are
|
||||||
|
* defined below.
|
||||||
|
*/
|
||||||
|
__u16 start_edge:1; /* flash control pulse rise position:
|
||||||
|
* 0 - at the start of the next frame.
|
||||||
|
* 1 - at the effective pixel end
|
||||||
|
* position of the next frame.
|
||||||
|
*/
|
||||||
|
__u16 repeat:1; /* flash control pulse repeat:
|
||||||
|
* 0 - only triggers one frame.
|
||||||
|
* 1 - trigger repeats every frame until
|
||||||
|
* Flash_EN = 0.
|
||||||
|
*/
|
||||||
|
__u16 delay_frm:2; /* flash control pulse can be delayed
|
||||||
|
* in frame units: (0 - 3) - frame
|
||||||
|
* numbers the pulse is delayed.
|
||||||
|
*/
|
||||||
|
} settings;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define NVC_IOCTL_CAPS_RD _IOWR('o', 106, struct nvc_imager_cap)
|
||||||
|
#define NVC_IOCTL_MODE_WR _IOW('o', 107, struct nvc_imager_bayer)
|
||||||
|
#define NVC_IOCTL_MODE_RD _IOWR('o', 108, struct nvc_imager_mode_list)
|
||||||
|
#define NVC_IOCTL_STATIC_RD _IOWR('o', 109, struct nvc_imager_static_nvc)
|
||||||
|
#define NVC_IOCTL_DYNAMIC_RD _IOWR('o', 110, struct nvc_imager_dnvc)
|
||||||
|
|
||||||
|
#endif /* __UAPI_NVC_IMAGE_H__ */
|
||||||
104
include/uapi/media/ov5693.h
Normal file
104
include/uapi/media/ov5693.h
Normal file
@@ -0,0 +1,104 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __UAPI_OV5693_H__
|
||||||
|
#define __UAPI_OV5693_H__
|
||||||
|
|
||||||
|
#include <media/nvc.h>
|
||||||
|
#include "nvc_image.h"
|
||||||
|
|
||||||
|
#define OV5693_IOCTL_SET_MODE _IOW('o', 1, struct ov5693_mode)
|
||||||
|
#define OV5693_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32)
|
||||||
|
#define OV5693_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32)
|
||||||
|
#define OV5693_IOCTL_SET_GAIN _IOW('o', 4, __u16)
|
||||||
|
#define OV5693_IOCTL_GET_STATUS _IOR('o', 5, __u8)
|
||||||
|
#define OV5693_IOCTL_SET_BINNING _IOW('o', 6, __u8)
|
||||||
|
#define OV5693_IOCTL_TEST_PATTERN _IOW('o', 7, \
|
||||||
|
enum ov5693_test_pattern)
|
||||||
|
#define OV5693_IOCTL_SET_GROUP_HOLD _IOW('o', 8, struct ov5693_ae)
|
||||||
|
/*
|
||||||
|
* IOCTL to set the operating mode of camera.
|
||||||
|
* This can be either stereo , leftOnly or rightOnly
|
||||||
|
*/
|
||||||
|
#define OV5693_IOCTL_SET_CAMERA_MODE _IOW('o', 10, __u32)
|
||||||
|
#define OV5693_IOCTL_SYNC_SENSORS _IOW('o', 11, __u32)
|
||||||
|
#define OV5693_IOCTL_GET_FUSEID _IOR('o', 12, struct nvc_fuseid)
|
||||||
|
#define OV5693_IOCTL_SET_HDR_COARSE_TIME _IOW('o', 13, struct ov5693_hdr)
|
||||||
|
#define OV5693_IOCTL_READ_OTP_BANK _IOWR('o', 14, \
|
||||||
|
struct ov5693_otp_bank)
|
||||||
|
#define OV5693_IOCTL_SET_CAL_DATA _IOW('o', 15, \
|
||||||
|
struct ov5693_cal_data)
|
||||||
|
#define OV5693_IOCTL_GET_EEPROM_DATA _IOR('o', 20, __u8 *)
|
||||||
|
#define OV5693_IOCTL_SET_EEPROM_DATA _IOW('o', 21, __u8 *)
|
||||||
|
#define OV5693_IOCTL_GET_CAPS _IOR('o', 22, struct nvc_imager_cap)
|
||||||
|
#define OV5693_IOCTL_SET_POWER _IOW('o', 23, __u32)
|
||||||
|
|
||||||
|
#define OV5693_FUSE_ID_OTP_START_ADDR 0x3D00
|
||||||
|
#define OV5693_FUSE_ID_OTP_BANK 0
|
||||||
|
#define OV5693_FUSE_ID_SIZE 8
|
||||||
|
#define OV5693_FUSE_ID_STR_SIZE (OV5693_FUSE_ID_SIZE * 2)
|
||||||
|
|
||||||
|
#define OV5693_FRAME_LENGTH_ADDR_MSB 0x380E
|
||||||
|
#define OV5693_FRAME_LENGTH_ADDR_LSB 0x380F
|
||||||
|
#define OV5693_COARSE_TIME_ADDR_1 0x3500
|
||||||
|
#define OV5693_COARSE_TIME_ADDR_2 0x3501
|
||||||
|
#define OV5693_COARSE_TIME_ADDR_3 0x3502
|
||||||
|
#define OV5693_COARSE_TIME_SHORT_ADDR_1 0x3506
|
||||||
|
#define OV5693_COARSE_TIME_SHORT_ADDR_2 0x3507
|
||||||
|
#define OV5693_COARSE_TIME_SHORT_ADDR_3 0x3508
|
||||||
|
#define OV5693_GAIN_ADDR_MSB 0x350A
|
||||||
|
#define OV5693_GAIN_ADDR_LSB 0x350B
|
||||||
|
#define OV5693_GROUP_HOLD_ADDR 0x3208
|
||||||
|
#define OV5693_TIMING_REG20 0x3820
|
||||||
|
#define VERTICAL_FLIP ((0x1 << 1) | (0x1 << 6))
|
||||||
|
#define OV5693_TIMING_REG21 0x3821
|
||||||
|
#define HORIZONTAL_MIRROR_MASK (0x3 << 1)
|
||||||
|
|
||||||
|
struct ov5693_mode {
|
||||||
|
int res_x;
|
||||||
|
int res_y;
|
||||||
|
int fps;
|
||||||
|
__u32 frame_length;
|
||||||
|
__u32 coarse_time;
|
||||||
|
__u32 coarse_time_short;
|
||||||
|
__u16 gain;
|
||||||
|
__u8 hdr_en;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ov5693_ae {
|
||||||
|
__u32 frame_length;
|
||||||
|
__u8 frame_length_enable;
|
||||||
|
__u32 coarse_time;
|
||||||
|
__u32 coarse_time_short;
|
||||||
|
__u8 coarse_time_enable;
|
||||||
|
__s32 gain;
|
||||||
|
__u8 gain_enable;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ov5693_fuseid {
|
||||||
|
__u32 size;
|
||||||
|
__u8 id[16];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ov5693_hdr {
|
||||||
|
__u32 coarse_time_long;
|
||||||
|
__u32 coarse_time_short;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ov5693_otp_bank {
|
||||||
|
__u32 id;
|
||||||
|
__u8 buf[16];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ov5693_cal_data {
|
||||||
|
int loaded;
|
||||||
|
int rg_ratio;
|
||||||
|
int bg_ratio;
|
||||||
|
int rg_ratio_typical;
|
||||||
|
int bg_ratio_typical;
|
||||||
|
__u8 lenc[62];
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* __UAPI_OV5693_H__ */
|
||||||
Reference in New Issue
Block a user