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PCD: Add Ethernet schema
Change-Id: I2430eca4258a625dba6f7f9ac868edf615ef3f5e Signed-off-by: Mark Mendez <mmendez@nvidia.com> Change-Id: I2430eca4258a625dba6f7f9ac868edf615ef3f5e Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3315791 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
This commit is contained in:
Mark Mendez
@@ -0,0 +1,663 @@
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# SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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# SPDX-License-Identifier: LicenseRef-NvidiaProprietary
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#
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# NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
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# property and proprietary rights in and to this material, related
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# documentation and any modifications thereto. Any use, reproduction,
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# disclosure or distribution of this material and related documentation
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# without an express license agreement from NVIDIA CORPORATION or
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# its affiliates is strictly prohibited.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ethernet@a808a10000/nvidia,tegra264-mgbe.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Ethernet Driver
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maintainers:
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- Narayan Reddy
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description: |
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the compatability = nvidia,tegra264-mgbe is mentioned in the following drivers
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- <TOP>/kernel/nvidia-oot/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c
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The following nodes use this compatibility
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- /bus@0/ethernet@a808a10000
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- /bus@0/ethernet@a808b10000
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- /bus@0/ethernet@a808d10000
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- /bus@0/ethernet@a808e10000
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select:
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properties:
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||||||
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compatible:
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||||||
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minItems: 1
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||||||
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maxItems: 1
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items:
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enum:
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- nvidia,tegra264-mgbe
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required:
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- compatible
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properties:
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||||||
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||||||
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reg:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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description: |
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Registers are given by a tuple of two values:
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- register address:
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- register block size.
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items:
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minItems: 4
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maxItems: 4
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||||||
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items:
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0xa8
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||||||
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maximum: 0xa8
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x8a10000
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||||||
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maximum: 0x8ed0000
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x0
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||||||
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maximum: 0x0
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x2000
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maximum: 0x10000
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reg-names:
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$ref: "/schemas/types.yaml#/definitions/string-array"
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items:
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enum:
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- mac
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- dma_base
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- macsec-base
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interrupts:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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description: |
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Interrupts are give by a tuple of 3 values:
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- interrupt specifier (GIC_SPI = 0, GIC_PPI = 1)
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definitions in dt-bindings/interrupt-controller/arm-gic.h
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- interrupt number
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- trigger type (rising edge, falling edge, both, etc)
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definitions in dt-bindings/interrupt-controller/irq.h
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items:
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items:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x0
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maximum: 0x0
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x366
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||||||
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maximum: 0x385
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x4
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maximum: 0x4
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interrupt-names:
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$ref: "/schemas/types.yaml#/definitions/string-array"
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items:
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enum:
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- common
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- vm0
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- vm1
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- vm2
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- vm3
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- vm4
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- macsec-ns-irq
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- macsec-s-irq
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resets:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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description: |
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Resets are given by a tuple of 2 values:
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- Phandle to the device
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- Reset ID
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items:
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||||||
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minItems: 2
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||||||
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maxItems: 2
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||||||
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items:
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x3e
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maximum: 0x49
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reset-names:
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$ref: "/schemas/types.yaml#/definitions/string-array"
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items:
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enum:
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- mac
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- pcs
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- macsec_ns_rst
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clocks:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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description: |
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Clocks are given by a tuple of 2 values:
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- Phandle to the device
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||||||
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- Clock ID
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||||||
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items:
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||||||
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minItems: 2
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||||||
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maxItems: 2
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||||||
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items:
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0xd5
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maximum: 0x1d2
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clock-names:
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$ref: "/schemas/types.yaml#/definitions/string-array"
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items:
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enum:
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- mac
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- tx
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- mgbe
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- macsec
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- tx-pcs
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- ptp-ref
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- rx-input
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||||||
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- rx-pcs-input
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||||||
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- tx-m
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||||||
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- rx-input-m
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||||||
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- rx-pcs-m
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||||||
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- utmi_pll1_clk
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||||||
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- pll_bpmpcam
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- tx_ser
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||||||
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- rx_ser
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nvidia,num-dma-chans:
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||||||
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x8
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maximum: 0x8
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||||||
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nvidia,dma-chans:
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||||||
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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||||||
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items:
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||||||
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minItems: 8
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||||||
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maxItems: 8
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||||||
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items:
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x0
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||||||
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maximum: 0x0
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x1
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||||||
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maximum: 0x1
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x2
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||||||
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maximum: 0x2
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x3
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||||||
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maximum: 0x3
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x4
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||||||
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maximum: 0x4
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x5
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||||||
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maximum: 0x5
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x6
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||||||
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maximum: 0x6
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x7
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||||||
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maximum: 0x7
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||||||
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||||||
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nvidia,num-mtl-queues:
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||||||
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$ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x8
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maximum: 0x8
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||||||
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||||||
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nvidia,mtl-queues:
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||||||
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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||||||
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items:
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||||||
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minItems: 10
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||||||
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maxItems: 10
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||||||
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items:
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x0
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||||||
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maximum: 0x0
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x1
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||||||
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maximum: 0x1
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x2
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||||||
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maximum: 0x2
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x3
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maximum: 0x3
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x4
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maximum: 0x4
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x5
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||||||
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maximum: 0x5
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x6
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||||||
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maximum: 0x6
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x7
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||||||
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maximum: 0x7
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x8
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||||||
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maximum: 0x8
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x9
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||||||
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maximum: 0x9
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||||||
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||||||
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nvidia,tc-mapping:
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||||||
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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||||||
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items:
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||||||
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minItems: 10
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||||||
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maxItems: 10
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||||||
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items:
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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||||||
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minimum: 0x0
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||||||
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maximum: 0x0
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
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minimum: 0x1
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||||||
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maximum: 0x1
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||||||
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- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
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minimum: 0x2
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||||||
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maximum: 0x2
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||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
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minimum: 0x3
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||||||
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maximum: 0x3
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
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minimum: 0x4
|
||||||
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maximum: 0x4
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x5
|
||||||
|
maximum: 0x5
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x6
|
||||||
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maximum: 0x6
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x7
|
||||||
|
maximum: 0x7
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
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minimum: 0x1
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||||||
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maximum: 0x1
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||||||
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||||||
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nvidia,residual-queue:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
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minimum: 0x1
|
||||||
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maximum: 0x1
|
||||||
|
|
||||||
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nvidia,rxq_enable_ctrl:
|
||||||
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
|
||||||
|
items:
|
||||||
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minItems: 10
|
||||||
|
maxItems: 10
|
||||||
|
items:
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
|
||||||
|
nvidia,vm-irq-config:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
|
||||||
|
nvidia,vm-vdma-config:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
|
||||||
|
nvidia,tx-queue-prio:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
|
||||||
|
items:
|
||||||
|
minItems: 10
|
||||||
|
maxItems: 10
|
||||||
|
items:
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x1
|
||||||
|
maximum: 0x1
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x3
|
||||||
|
maximum: 0x3
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x4
|
||||||
|
maximum: 0x4
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x5
|
||||||
|
maximum: 0x5
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x6
|
||||||
|
maximum: 0x6
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x7
|
||||||
|
maximum: 0x7
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
|
||||||
|
nvidia,rx-queue-prio:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
|
||||||
|
items:
|
||||||
|
minItems: 10
|
||||||
|
maxItems: 10
|
||||||
|
items:
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x1
|
||||||
|
maximum: 0x1
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2
|
||||||
|
maximum: 0x2
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x4
|
||||||
|
maximum: 0x4
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x8
|
||||||
|
maximum: 0x8
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x10
|
||||||
|
maximum: 0x10
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x20
|
||||||
|
maximum: 0x20
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x40
|
||||||
|
maximum: 0x40
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x80
|
||||||
|
maximum: 0x80
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
|
||||||
|
nvidia,dcs-enable:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x1
|
||||||
|
maximum: 0x1
|
||||||
|
|
||||||
|
nvidia,macsec-enable:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x1
|
||||||
|
maximum: 0x1
|
||||||
|
|
||||||
|
nvidia,mgbe-riit-config:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
|
||||||
|
nvidia,rx_riwt:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x200
|
||||||
|
maximum: 0x200
|
||||||
|
|
||||||
|
nvidia,rx_frames:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x40
|
||||||
|
maximum: 0x40
|
||||||
|
|
||||||
|
nvidia,tx_usecs:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x100
|
||||||
|
maximum: 0x100
|
||||||
|
|
||||||
|
nvidia,tx_frames:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x10
|
||||||
|
maximum: 0x10
|
||||||
|
|
||||||
|
nvidia,phy-iface-mode:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
|
||||||
|
nvidia,promisc_mode:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x1
|
||||||
|
maximum: 0x1
|
||||||
|
|
||||||
|
nvidia,slot_num_check:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
|
||||||
|
items:
|
||||||
|
minItems: 8
|
||||||
|
maxItems: 8
|
||||||
|
items:
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
|
||||||
|
nvidia,slot_intvl_vals:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
|
||||||
|
items:
|
||||||
|
minItems: 8
|
||||||
|
maxItems: 8
|
||||||
|
items:
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x0
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x7d
|
||||||
|
maximum: 0x7d
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x7d
|
||||||
|
maximum: 0x7d
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x7d
|
||||||
|
maximum: 0x7d
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x7d
|
||||||
|
maximum: 0x7d
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x7d
|
||||||
|
maximum: 0x7d
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x7d
|
||||||
|
maximum: 0x7d
|
||||||
|
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x7d
|
||||||
|
maximum: 0x7d
|
||||||
|
|
||||||
|
nvidia,ptp_ref_clock_speed:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x12a05f20
|
||||||
|
maximum: 0x12a05f20
|
||||||
|
|
||||||
|
nvidia,instance_id:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x0
|
||||||
|
maximum: 0x3
|
||||||
|
|
||||||
|
nvidia,ptp-rx-queue:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x3
|
||||||
|
maximum: 0x3
|
||||||
|
|
||||||
|
nvidia,dma_rx_ring_sz:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x1000
|
||||||
|
maximum: 0x1000
|
||||||
|
|
||||||
|
nvidia,dma_tx_ring_sz:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x1000
|
||||||
|
maximum: 0x1000
|
||||||
|
|
||||||
|
dma-coherent:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/flag"
|
||||||
|
|
||||||
|
nvidia,mac-addr-idx:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x1
|
||||||
|
maximum: 0x4
|
||||||
|
|
||||||
|
nvidia,uphy-gbe-mode:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x1
|
||||||
|
maximum: 0x1
|
||||||
|
|
||||||
|
nvidia,max-platform-mtu:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x2328
|
||||||
|
maximum: 0x2328
|
||||||
|
|
||||||
|
nvidia,if-name:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/string-array"
|
||||||
|
items:
|
||||||
|
enum:
|
||||||
|
- mgbe0_0
|
||||||
|
- mgbe1_0
|
||||||
|
- mgbe2_0
|
||||||
|
- mgbe3_0
|
||||||
|
|
||||||
|
|
||||||
|
ivc:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x10
|
||||||
|
maximum: 0x1af
|
||||||
|
|
||||||
|
nvidia,ptp_m2m_role:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x1
|
||||||
|
maximum: 0x2
|
||||||
|
|
||||||
|
nvidia,pps_op_ctrl:
|
||||||
|
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||||
|
minimum: 0x8
|
||||||
|
maximum: 0x8
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- interrupts
|
||||||
|
- interrupt-names
|
||||||
|
- resets
|
||||||
|
- reset-names
|
||||||
|
- clocks
|
||||||
|
- clock-names
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
ethernet@a808a10000 {
|
||||||
|
compatible = "nvidia,tegra264-mgbe";
|
||||||
|
status = "disabled";
|
||||||
|
reg = <0xa8 0x8a10000 0x00 0x10000>,
|
||||||
|
<0xa8 0x8aa0000 0x00 0x10000>,
|
||||||
|
<0xa8 0x8ad0000 0x00 0x10000>,
|
||||||
|
<0xa8 0x8a00000 0x00 0x10000>;
|
||||||
|
reg-names = "mac, xpcs, macsec-base, hypervisor";
|
||||||
|
interrupts = <0 870 4>,
|
||||||
|
<0 873 4>,
|
||||||
|
<0 874 4>,
|
||||||
|
<0 875 4>,
|
||||||
|
<0 876 4>,
|
||||||
|
<0 877 4>,
|
||||||
|
<0 872 4>,
|
||||||
|
<0 871 4>;
|
||||||
|
interrupt-names = "common, vm0, vm1, vm2, vm3, vm4",
|
||||||
|
"macsec-ns-irq, macsec-s-irq";
|
||||||
|
resets = <&bpmp TEGRA264_RESET_MGBE0_MAC>,
|
||||||
|
<&bpmp TEGRA264_RESET_MGBE0_PCS>,
|
||||||
|
<&bpmp TEGRA264_RESET_MGBE0_MACSEC>;
|
||||||
|
reset-names = "mac, pcs, macsec_ns_rst";
|
||||||
|
clocks = <&bpmp TEGRA264_CLK_MGBE0_MAC>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_TX>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_APP>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_MACSEC>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_TX_PCS>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBES_PTP_REF>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_RX_IN>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_RX_PCS_IN>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_TX_M>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_RX_M>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_RX_PCS_M>,
|
||||||
|
<&bpmp TEGRA264_CLK_UTMI_PLL1_CLKOUT480>,
|
||||||
|
<&bpmp TEGRA264_CLK_PLLBPMPCAM>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_TX_SER>,
|
||||||
|
<&bpmp TEGRA264_CLK_MGBE0_RX_SER>;
|
||||||
|
clock-names = "mac, tx, mgbe, macsec, tx-pcs, ptp-ref",
|
||||||
|
"rx-input, rx-pcs-input, tx-m, rx-input-m",
|
||||||
|
"rx-pcs-m, utmi_pll1_clk, pll_bpmpcam, tx_ser, rx_ser";
|
||||||
|
nvidia,num-dma-chans = <8>;
|
||||||
|
nvidia,dma-chans = <0 1 2 3 4 5 6 7>;
|
||||||
|
iommus = <&smmu0_mmu TEGRA_SID_MGBE0_VF0>;
|
||||||
|
nvidia,num-mtl-queues = <10>;
|
||||||
|
nvidia,mtl-queues = <0 1 2 3 4 5 6 7 8 9>;
|
||||||
|
nvidia,tc-mapping = <0 1 2 3 4 5 6 7 0 1>;
|
||||||
|
nvidia,residual-queue = <1>;
|
||||||
|
nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2 2 2>;
|
||||||
|
nvidia,vm-irq-config = <&mgbe_vm_irq_config>;
|
||||||
|
nvidia,vm-vdma-config = <&mgbe_vm_vdma_config>;
|
||||||
|
nvidia,tx-queue-prio = <0 1 2 3 4 5 6 7 0 0>;
|
||||||
|
nvidia,rx-queue-prio = <0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80 0x0 0x0>;
|
||||||
|
nvidia,dcs-enable = <0x1>;
|
||||||
|
nvidia,macsec-enable = <0x1>;
|
||||||
|
nvidia,mgbe-riit-config = <&mgbe_riit_config>;
|
||||||
|
nvidia,rx_riwt = <512>;
|
||||||
|
nvidia,rx_frames = <64>;
|
||||||
|
nvidia,tx_usecs = <256>;
|
||||||
|
nvidia,tx_frames = <16>;
|
||||||
|
nvidia,phy-iface-mode = <2>;
|
||||||
|
nvidia,promisc_mode = <1>;
|
||||||
|
nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||||
|
nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
|
||||||
|
nvidia,ptp_ref_clock_speed = <312500000>;
|
||||||
|
nvidia,instance_id = <0>;
|
||||||
|
nvidia,ptp-rx-queue = <3>;
|
||||||
|
nvidia,dma_rx_ring_sz = <4096>;
|
||||||
|
nvidia,dma_tx_ring_sz = <4096>;
|
||||||
|
dma-coherent;
|
||||||
|
};
|
||||||
Reference in New Issue
Block a user