From 38578736f2d407c8c360e93b2709ccb4c0c48b2e Mon Sep 17 00:00:00 2001 From: Robert Huang Date: Tue, 20 May 2025 07:03:17 +0000 Subject: [PATCH] tegra-cec: Fix cec_irq flooding issue The RX_REGISTER_FULL interrupt is not cleared when rx_fifo_data is 0. Add readw for RX_REGISTER when rx_fifo_data is 0 so that the interrupt can be cleared. Bug 5266075 Change-Id: I10ab107efadc22a6ec79255e22bf080384b4ff5c Signed-off-by: Robert Huang Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3367190 GVS: buildbot_gerritrpt Reviewed-by: svcacv Reviewed-by: Prafull Suryawanshi Reviewed-by: Bitan Biswas --- drivers/misc/tegra-cec/tegra_cec.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/misc/tegra-cec/tegra_cec.c b/drivers/misc/tegra-cec/tegra_cec.c index 675df587..d61c841d 100644 --- a/drivers/misc/tegra-cec/tegra_cec.c +++ b/drivers/misc/tegra-cec/tegra_cec.c @@ -343,6 +343,11 @@ static irqreturn_t tegra_cec_irq_handler(int irq, void *data) readw(cec->cec_base + TEGRA_CEC_RX_REGISTER); } + if (cec->rx_fifo_data == 0) { + dev_info(dev, "rx_fifo_data is empty.\n"); + readw(cec->cec_base + TEGRA_CEC_RX_REGISTER); + } + tegra_cec_writel(TEGRA_CEC_INT_STAT_RX_REGISTER_FULL, cec->cec_base + TEGRA_CEC_INT_STAT);