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git://nv-tegra.nvidia.com/linux-nv-oot.git
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ASoC: tegra: merge 'tegra' and 'tegra-alt' directories
Tegra210 and later audio drivers have been using 'tegra-alt' directory from the beginning. As per the upstream roadmap, we plan to use the same 'tegra' directory and place all the drivers under it. This patch thus moves all the drivers to 'tegra' and renames the files accordingly. The '_alt' suffix is removed from header and source files. For some files still the '_alt' suffix is retained because 'tegra' already has the corresponding files. Manual merge of following files is needed and will be done in separate commits. * tegra_asoc_utils_alt.c and tegra_asoc_utils.c * tegra_asoc_utils_alt.h and tegra_asoc_utils.h * tegra_pcm_alt.c and tegra_pcm.c * tegra_pcm_alt.h and tegra_pcm.h * Corresponding Makefile and Kconfig files. * Source files related to ADSP audio, FPGA, bandwidth manager are not considered at the moment and will be tracked separately. Bug 2845498 Change-Id: I51dae3971c72b58d921dc19f0553a83422fd3f9e Signed-off-by: Sameer Pujar <spujar@nvidia.com>
This commit is contained in:
Sameer Pujar
524
sound/soc/tegra/tegra186_dspk.c
Normal file
524
sound/soc/tegra/tegra186_dspk.c
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@@ -0,0 +1,524 @@
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/*
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* tegra186_dspk_alt.c - Tegra186 DSPK driver
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*
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* Copyright (c) 2015-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/of_device.h>
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#include <soc/tegra/chip-id.h>
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#include <linux/pinctrl/pinconf-tegra.h>
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#include "tegra210_xbar_alt.h"
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#include "tegra186_dspk_alt.h"
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#include "ahub_unit_fpga_clock.h"
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#define DRV_NAME "tegra186-dspk"
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static const struct reg_default tegra186_dspk_reg_defaults[] = {
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{ TEGRA186_DSPK_AXBAR_RX_INT_MASK, 0x00000007},
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{ TEGRA186_DSPK_AXBAR_RX_CIF_CTRL, 0x00007700},
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{ TEGRA186_DSPK_CG, 0x00000001},
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{ TEGRA186_DSPK_CORE_CTRL, 0x00000310},
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{ TEGRA186_DSPK_CODEC_CTRL, 0x03000000},
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{ TEGRA186_DSPK_SDM_COEF_A_2, 0x000013bb},
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{ TEGRA186_DSPK_SDM_COEF_A_3, 0x00001cbf},
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{ TEGRA186_DSPK_SDM_COEF_A_4, 0x000029d7},
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{ TEGRA186_DSPK_SDM_COEF_A_5, 0x00003782},
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{ TEGRA186_DSPK_SDM_COEF_C_1, 0x000000a6},
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{ TEGRA186_DSPK_SDM_COEF_C_2, 0x00001959},
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{ TEGRA186_DSPK_SDM_COEF_C_3, 0x00002b9f},
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{ TEGRA186_DSPK_SDM_COEF_C_4, 0x00004218},
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{ TEGRA186_DSPK_SDM_COEF_G_1, 0x00000074},
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{ TEGRA186_DSPK_SDM_COEF_G_2, 0x0000007d},
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};
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static int tegra186_dspk_get_control(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_codec_get_drvdata(codec);
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if (strstr(kcontrol->id.name, "Rx fifo threshold"))
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ucontrol->value.integer.value[0] = dspk->rx_fifo_th;
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else if (strstr(kcontrol->id.name, "OSR Value"))
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ucontrol->value.integer.value[0] = dspk->osr_val;
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return 0;
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}
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static int tegra186_dspk_put_control(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_codec_get_drvdata(codec);
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int val = ucontrol->value.integer.value[0];
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if (strstr(kcontrol->id.name, "Rx fifo threshold")) {
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if (val >= 0 && val < TEGRA186_DSPK_RX_FIFO_DEPTH)
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dspk->rx_fifo_th = val;
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else
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return -EINVAL;
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} else if (strstr(kcontrol->id.name, "OSR Value"))
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dspk->osr_val = val;
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return 0;
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}
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static int tegra186_dspk_runtime_suspend(struct device *dev)
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{
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struct tegra186_dspk *dspk = dev_get_drvdata(dev);
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regcache_cache_only(dspk->regmap, true);
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regcache_mark_dirty(dspk->regmap);
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if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()))
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clk_disable_unprepare(dspk->clk_dspk);
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return 0;
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}
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static int tegra186_dspk_runtime_resume(struct device *dev)
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{
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struct tegra186_dspk *dspk = dev_get_drvdata(dev);
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int ret;
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if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
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ret = clk_prepare_enable(dspk->clk_dspk);
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if (ret) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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return ret;
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}
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}
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regcache_cache_only(dspk->regmap, false);
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regcache_sync(dspk->regmap);
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return 0;
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}
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static int tegra186_dspk_set_audio_cif(struct tegra186_dspk *dspk,
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struct snd_pcm_hw_params *params,
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unsigned int reg, struct snd_soc_dai *dai)
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{
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int channels, max_th;
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struct tegra210_xbar_cif_conf cif_conf;
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struct device *dev = dai->dev;
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channels = params_channels(params);
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memset(&cif_conf, 0, sizeof(struct tegra210_xbar_cif_conf));
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cif_conf.audio_channels = channels;
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cif_conf.client_channels = channels;
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cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_24;
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/* RX FIFO threshold interms of frames */
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max_th = (TEGRA186_DSPK_RX_FIFO_DEPTH / channels) - 1;
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max_th = (max_th < 0) ? 0 : max_th;
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if (dspk->rx_fifo_th > max_th) { /* error handling */
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cif_conf.threshold = max_th;
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dspk->rx_fifo_th = max_th;
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} else
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cif_conf.threshold = dspk->rx_fifo_th;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_16;
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cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_32;
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break;
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default:
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dev_err(dev, "Wrong format!\n");
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return -EINVAL;
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}
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tegra210_xbar_set_cif(dspk->regmap, TEGRA186_DSPK_AXBAR_RX_CIF_CTRL,
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&cif_conf);
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return 0;
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}
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static int tegra186_dspk_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->dev;
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struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
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int ret;
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if (dspk->prod_name != NULL) {
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ret = tegra_pinctrl_config_prod(dev, dspk->prod_name);
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if (ret < 0)
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dev_warn(dev, "Failed to set %s setting\n",
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dspk->prod_name);
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}
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return 0;
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}
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static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->dev;
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struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
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int channels, srate, ret, dspk_clk;
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int osr = dspk->osr_val;
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int interface_clk_ratio = 4; /* dspk interface clock should be fsout*4 */
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channels = params_channels(params);
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srate = params_rate(params);
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dspk_clk = (1 << (5+osr)) * srate * interface_clk_ratio;
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if ((tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
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program_dspk_clk(dspk_clk);
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} else {
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ret = clk_set_rate(dspk->clk_dspk, dspk_clk);
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if (ret) {
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dev_err(dev, "Can't set dspk clock rate: %d\n", ret);
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return ret;
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}
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}
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regmap_update_bits(dspk->regmap,
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TEGRA186_DSPK_CORE_CTRL,
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TEGRA186_DSPK_OSR_MASK,
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osr << TEGRA186_DSPK_OSR_SHIFT);
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regmap_update_bits(dspk->regmap,
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TEGRA186_DSPK_CORE_CTRL,
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TEGRA186_DSPK_CHANNEL_SELECT_MASK,
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((1 << channels) - 1) <<
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TEGRA186_DSPK_CHANNEL_SELECT_SHIFT);
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/* program cif control register */
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ret = tegra186_dspk_set_audio_cif(dspk, params,
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TEGRA186_DSPK_AXBAR_RX_CIF_CTRL,
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dai);
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if (ret)
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dev_err(dev, "Can't set dspk RX CIF: %d\n", ret);
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return ret;
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}
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static struct snd_soc_dai_ops tegra186_dspk_dai_ops = {
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.hw_params = tegra186_dspk_hw_params,
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.startup = tegra186_dspk_startup,
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};
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static struct snd_soc_dai_driver tegra186_dspk_dais[] = {
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{
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.name = "CIF",
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.playback = {
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.stream_name = "CIF Receive",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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},
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{
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.name = "DAP",
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.capture = {
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.stream_name = "DAP Transmit",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.ops = &tegra186_dspk_dai_ops,
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.symmetric_rates = 1,
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},
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/* The second DAI is used when the output of the DSPK is connected
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* to two mono codecs. When the output of the DSPK is connected to
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* a single stereo codec, then only the first DAI should be used.
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*/
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{
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.name = "CIF2",
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.playback = {
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.stream_name = "CIF2 Receive",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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},
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{
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.name = "DAP2",
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.capture = {
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.stream_name = "DAP2 Transmit",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.symmetric_rates = 1,
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},
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{
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.name = "DUMMY_SINK",
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.playback = {
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.stream_name = "Dummy Playback",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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},
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};
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static const struct snd_soc_dapm_widget tegra186_dspk_widgets[] = {
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SND_SOC_DAPM_AIF_OUT("DAP TX", NULL, 0, TEGRA186_DSPK_ENABLE, 0, 0),
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SND_SOC_DAPM_AIF_OUT("DAP2 TX", NULL, 0, 0, 0, 0),
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SND_SOC_DAPM_SPK("Dummy Output", NULL),
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};
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static const struct snd_soc_dapm_route tegra186_dspk_routes[] = {
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{ "DAP TX", NULL, "CIF Receive" },
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{ "DAP Transmit", NULL, "DAP TX" },
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{ "DAP2 TX", NULL, "CIF2 Receive" },
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{ "DAP2 Transmit", NULL, "DAP2 TX" },
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{ "Dummy Output", NULL, "Dummy Playback" },
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};
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static const char * const tegra186_dspk_osr_text[] = {
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"OSR_32", "OSR_64", "OSR_128", "OSR_256",
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};
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static const struct soc_enum tegra186_dspk_osr_enum =
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SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
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ARRAY_SIZE(tegra186_dspk_osr_text),
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tegra186_dspk_osr_text);
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#define NV_SOC_SINGLE_RANGE_EXT(xname, xmin, xmax, xget, xput) \
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{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
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.info = snd_soc_info_xr_sx, .get = xget, .put = xput, \
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.private_value = (unsigned long)&(struct soc_mixer_control) \
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{.invert = 0, .min = xmin, .max = xmax, \
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.platform_max = xmax} \
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}
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static const struct snd_kcontrol_new tegrat186_dspk_controls[] = {
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NV_SOC_SINGLE_RANGE_EXT("Rx fifo threshold", 0,
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TEGRA186_DSPK_RX_FIFO_DEPTH - 1, tegra186_dspk_get_control,
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tegra186_dspk_put_control),
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SOC_ENUM_EXT("OSR Value", tegra186_dspk_osr_enum,
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tegra186_dspk_get_control, tegra186_dspk_put_control),
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};
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static struct snd_soc_codec_driver tegra186_dspk_codec = {
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.idle_bias_off = 1,
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.component_driver = {
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.dapm_widgets = tegra186_dspk_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra186_dspk_widgets),
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.dapm_routes = tegra186_dspk_routes,
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.num_dapm_routes = ARRAY_SIZE(tegra186_dspk_routes),
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.controls = tegrat186_dspk_controls,
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.num_controls = ARRAY_SIZE(tegrat186_dspk_controls),
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},
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};
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/* Regmap callback functions */
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static bool tegra186_dspk_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA186_DSPK_AXBAR_RX_INT_MASK:
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case TEGRA186_DSPK_AXBAR_RX_INT_SET:
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case TEGRA186_DSPK_AXBAR_RX_INT_CLEAR:
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case TEGRA186_DSPK_AXBAR_RX_CIF_CTRL:
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case TEGRA186_DSPK_AXBAR_RX_CYA:
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case TEGRA186_DSPK_ENABLE:
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case TEGRA186_DSPK_SOFT_RESET:
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case TEGRA186_DSPK_CG:
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return true;
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default:
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if (((reg % 4) == 0) && (reg >= TEGRA186_DSPK_CORE_CTRL) &&
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(reg <= TEGRA186_DSPK_SDM_COEF_G_2))
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return true;
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else
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return false;
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};
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}
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static bool tegra186_dspk_rd_reg(struct device *dev, unsigned int reg)
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{
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if (tegra186_dspk_wr_reg(dev, reg))
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return true;
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switch (reg) {
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case TEGRA186_DSPK_AXBAR_RX_STATUS:
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case TEGRA186_DSPK_AXBAR_RX_INT_STATUS:
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case TEGRA186_DSPK_AXBAR_RX_CIF_FIFO_STATUS:
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case TEGRA186_DSPK_STATUS:
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case TEGRA186_DSPK_INT_STATUS:
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return true;
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default:
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if (((reg % 4) == 0) && (reg >= TEGRA186_DSPK_DEBUG_STATUS) &&
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(reg <= TEGRA186_DSPK_DEBUG_STAGE4_CNTR))
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return true;
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else
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return false;
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};
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}
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static bool tegra186_dspk_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA186_DSPK_AXBAR_RX_STATUS:
|
||||
case TEGRA186_DSPK_AXBAR_RX_INT_STATUS:
|
||||
case TEGRA186_DSPK_AXBAR_RX_CIF_FIFO_STATUS:
|
||||
case TEGRA186_DSPK_STATUS:
|
||||
case TEGRA186_DSPK_INT_STATUS:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
};
|
||||
}
|
||||
|
||||
static const struct regmap_config tegra186_dspk_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = TEGRA186_DSPK_DEBUG_STAGE4_CNTR,
|
||||
.writeable_reg = tegra186_dspk_wr_reg,
|
||||
.readable_reg = tegra186_dspk_rd_reg,
|
||||
.volatile_reg = tegra186_dspk_volatile_reg,
|
||||
.precious_reg = NULL,
|
||||
.reg_defaults = tegra186_dspk_reg_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(tegra186_dspk_reg_defaults),
|
||||
.cache_type = REGCACHE_FLAT,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra186_dspk_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra186-dspk" },
|
||||
{},
|
||||
};
|
||||
|
||||
static int tegra186_dspk_platform_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra186_dspk *dspk;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct resource *mem;
|
||||
void __iomem *regs;
|
||||
int ret = 0;
|
||||
const struct of_device_id *match;
|
||||
|
||||
match = of_match_device(tegra186_dspk_of_match, &pdev->dev);
|
||||
if (!match) {
|
||||
dev_err(&pdev->dev, "Error: No device match found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
dspk = devm_kzalloc(&pdev->dev, sizeof(*dspk), GFP_KERNEL);
|
||||
if (!dspk)
|
||||
return -ENOMEM;
|
||||
|
||||
dspk->prod_name = NULL;
|
||||
dspk->rx_fifo_th = 0;
|
||||
dspk->osr_val = TEGRA186_DSPK_OSR_64;
|
||||
dev_set_drvdata(&pdev->dev, dspk);
|
||||
|
||||
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
|
||||
dspk->clk_dspk = devm_clk_get(&pdev->dev, "dspk");
|
||||
if (IS_ERR(dspk->clk_dspk)) {
|
||||
dev_err(&pdev->dev, "Can't retrieve dspk clock\n");
|
||||
return PTR_ERR(dspk->clk_dspk);
|
||||
}
|
||||
}
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
regs = devm_ioremap_resource(&pdev->dev, mem);
|
||||
if (IS_ERR(regs))
|
||||
return PTR_ERR(regs);
|
||||
dspk->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
||||
&tegra186_dspk_regmap_config);
|
||||
if (IS_ERR(dspk->regmap)) {
|
||||
dev_err(&pdev->dev, "regmap init failed\n");
|
||||
return PTR_ERR(dspk->regmap);
|
||||
}
|
||||
regcache_cache_only(dspk->regmap, true);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
ret = snd_soc_register_codec(&pdev->dev, &tegra186_dspk_codec,
|
||||
tegra186_dspk_dais,
|
||||
ARRAY_SIZE(tegra186_dspk_dais));
|
||||
if (ret != 0) {
|
||||
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (of_property_read_string(np, "prod-name", &dspk->prod_name) == 0) {
|
||||
ret = tegra_pinctrl_config_prod(&pdev->dev, dspk->prod_name);
|
||||
if (ret < 0)
|
||||
dev_warn(&pdev->dev, "Failed to set %s setting\n",
|
||||
dspk->prod_name);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_dspk_platform_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra186_dspk *dspk;
|
||||
|
||||
dspk = dev_get_drvdata(&pdev->dev);
|
||||
snd_soc_unregister_codec(&pdev->dev);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||
tegra186_dspk_runtime_suspend(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops tegra186_dspk_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(tegra186_dspk_runtime_suspend,
|
||||
tegra186_dspk_runtime_resume, NULL)
|
||||
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver tegra186_dspk_driver = {
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra186_dspk_of_match,
|
||||
.pm = &tegra186_dspk_pm_ops,
|
||||
},
|
||||
.probe = tegra186_dspk_platform_probe,
|
||||
.remove = tegra186_dspk_platform_remove,
|
||||
};
|
||||
module_platform_driver(tegra186_dspk_driver);
|
||||
|
||||
|
||||
MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>");
|
||||
MODULE_DESCRIPTION("Tegra186 DSPK ASoC driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
MODULE_DEVICE_TABLE(of, tegra186_dspk_of_match);
|
||||
Reference in New Issue
Block a user