diff --git a/sound/soc/tegra-alt/include/tegra210_xbar_alt.h b/sound/soc/tegra-alt/include/tegra210_xbar_alt.h index 22bfa4f8..e87d9c1b 100644 --- a/sound/soc/tegra-alt/include/tegra210_xbar_alt.h +++ b/sound/soc/tegra-alt/include/tegra210_xbar_alt.h @@ -1,7 +1,7 @@ /* * tegra210_xbar_alt.h - TEGRA210 XBAR registers * - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -31,123 +31,48 @@ /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */ #define TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 24 -#define TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0x3f -#define TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) - /* Channel count minus 1 */ #define TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 20 -#define TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 0xf -#define TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) - /* Channel count minus 1 */ #define TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 -#define TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 0xf -#define TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) -#define TEGRA210_AUDIOCIF_BITS_RVDS 0 #define TEGRA210_AUDIOCIF_BITS_8 1 -#define TEGRA210_AUDIOCIF_BITS_12 2 #define TEGRA210_AUDIOCIF_BITS_16 3 -#define TEGRA210_AUDIOCIF_BITS_20 4 #define TEGRA210_AUDIOCIF_BITS_24 5 -#define TEGRA210_AUDIOCIF_BITS_28 6 #define TEGRA210_AUDIOCIF_BITS_32 7 #define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12 -#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA210_AUDIOCIF_BITS_8 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA210_AUDIOCIF_BITS_12 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA210_AUDIOCIF_BITS_16 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA210_AUDIOCIF_BITS_20 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA210_AUDIOCIF_BITS_24 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA210_AUDIOCIF_BITS_28 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA210_AUDIOCIF_BITS_32 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) - #define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8 -#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA210_AUDIOCIF_BITS_8 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA210_AUDIOCIF_BITS_12 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA210_AUDIOCIF_BITS_16 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA210_AUDIOCIF_BITS_20 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA210_AUDIOCIF_BITS_24 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA210_AUDIOCIF_BITS_28 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA210_AUDIOCIF_BITS_32 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) - -#define TEGRA210_AUDIOCIF_EXPAND_ZERO 0 -#define TEGRA210_AUDIOCIF_EXPAND_ONE 1 -#define TEGRA210_AUDIOCIF_EXPAND_LFSR 2 - #define TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT 6 -#define TEGRA210_AUDIOCIF_CTRL_EXPAND_MASK (3 << TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_EXPAND_ZERO (TEGRA210_AUDIOCIF_EXPAND_ZERO << TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_EXPAND_ONE (TEGRA210_AUDIOCIF_EXPAND_ONE << TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_EXPAND_LFSR (TEGRA210_AUDIOCIF_EXPAND_LFSR << TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT) - -#define TEGRA210_AUDIOCIF_STEREO_CONV_CH0 0 -#define TEGRA210_AUDIOCIF_STEREO_CONV_CH1 1 -#define TEGRA210_AUDIOCIF_STEREO_CONV_AVG 2 - #define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4 -#define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_MASK (3 << TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_CH0 (TEGRA210_AUDIOCIF_STEREO_CONV_CH0 << TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_CH1 (TEGRA210_AUDIOCIF_STEREO_CONV_CH1 << TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_AVG (TEGRA210_AUDIOCIF_STEREO_CONV_AVG << TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) - #define TEGRA210_AUDIOCIF_CTRL_REPLICATE_SHIFT 3 - -#define TEGRA210_AUDIOCIF_TRUNCATE_ROUND 0 -#define TEGRA210_AUDIOCIF_TRUNCATE_CHOP 1 - #define TEGRA210_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1 -#define TEGRA210_AUDIOCIF_CTRL_TRUNCATE_MASK (1 << TEGRA210_AUDIOCIF_CTRL_TRUNCATE_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_TRUNCATE_ROUND (TEGRA210_AUDIOCIF_TRUNCATE_ROUND << TEGRA210_AUDIOCIF_CTRL_TRUNCATE_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_TRUNCATE_CHOP (TEGRA210_AUDIOCIF_TRUNCATE_CHOP << TEGRA210_AUDIOCIF_CTRL_TRUNCATE_SHIFT) - -#define TEGRA210_AUDIOCIF_MONO_CONV_ZERO 0 -#define TEGRA210_AUDIOCIF_MONO_CONV_COPY 1 - #define TEGRA210_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0 -#define TEGRA210_AUDIOCIF_CTRL_MONO_CONV_MASK (1 << TEGRA210_AUDIOCIF_CTRL_MONO_CONV_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_MONO_CONV_ZERO (TEGRA210_AUDIOCIF_MONO_CONV_ZERO << TEGRA210_AUDIOCIF_CTRL_MONO_CONV_SHIFT) -#define TEGRA210_AUDIOCIF_CTRL_MONO_CONV_COPY (TEGRA210_AUDIOCIF_MONO_CONV_COPY << TEGRA210_AUDIOCIF_CTRL_MONO_CONV_SHIFT) /* Fields in *AHUBRAMCTL_CTRL; used by different AHUB modules */ -#define TEGRA210_AHUBRAMCTL_CTRL_READ_BUSY_SHIFT 31 -#define TEGRA210_AHUBRAMCTL_CTRL_READ_BUSY_MASK (1 << TEGRA210_AHUBRAMCTL_CTRL_READ_BUSY_SHIFT) -#define TEGRA210_AHUBRAMCTL_CTRL_READ_BUSY (1 << TEGRA210_AHUBRAMCTL_CTRL_READ_BUSY_SHIFT) - -#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_READ_COUNT_SHIFT 16 -#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_READ_COUNT_MASK (0xff << TEGRA210_AHUBRAMCTL_CTRL_SEQ_READ_COUNT_SHIFT) - -#define TEGRA210_AHUBRAMCTL_CTRL_RW_SHIFT 14 -#define TEGRA210_AHUBRAMCTL_CTRL_RW_MASK (1 << TEGRA210_AHUBRAMCTL_CTRL_RW_SHIFT) -#define TEGRA210_AHUBRAMCTL_CTRL_RW_READ (0 << TEGRA210_AHUBRAMCTL_CTRL_RW_SHIFT) -#define TEGRA210_AHUBRAMCTL_CTRL_RW_WRITE (1 << TEGRA210_AHUBRAMCTL_CTRL_RW_SHIFT) - -#define TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN_SHIFT 13 -#define TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN_MASK (1 << TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN_SHIFT) -#define TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN (1 << TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN_SHIFT) - -#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN_SHIFT 12 -#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN_MASK (1 << TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN_SHIFT) -#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN_SHIFT) - -#define TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_SHIFT 0 -#define TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK (0x1ff << TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_SHIFT) +#define TEGRA210_AHUBRAMCTL_CTRL_RW_READ 0 +#define TEGRA210_AHUBRAMCTL_CTRL_RW_WRITE (1 << 14) +#define TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN (1 << 13) +#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN (1 << 12) +#define TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK 0x1ff #define TEGRA210_NUM_DAIS 67 -#define TEGRA210_NUM_MUX_WIDGETS 50 -#define TEGRA210_NUM_MUX_INPUT 54 /* size of TEGRA210_ROUTES */ -#define TEGRA186_NUM_DAIS 108 -#define TEGRA186_NUM_MUX_WIDGETS 79 -#define TEGRA186_NUM_MUX_INPUT 82 /* size of TEGRA_ROUTES + TEGRA186_ROUTES */ +#define TEGRA210_NUM_MUX_WIDGETS 50 -#define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX +\ +/* size of TEGRA210_ROUTES */ +#define TEGRA210_NUM_MUX_INPUT 54 + +#define TEGRA186_NUM_DAIS 108 +#define TEGRA186_NUM_MUX_WIDGETS 79 + +/* size of TEGRA_ROUTES + TEGRA186_ROUTES */ +#define TEGRA186_NUM_MUX_INPUT 82 + +#define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \ (TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1))) -#define TEGRA186_XBAR_PART3_RX 0x600 +#define TEGRA186_XBAR_PART3_RX 0x600 #define TEGRA186_XBAR_AUDIO_RX_COUNT 115 -#define TEGRA186_AUDIOCIF_CTRL_FIFO_SIZE_DOWNSHIFT_SHIFT 2 #define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX +\ (TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1))) @@ -156,18 +81,18 @@ #define TEGRA210_XBAR_REG_MASK_1 0x3f30031f #define TEGRA210_XBAR_REG_MASK_2 0xff1cf313 #define TEGRA210_XBAR_REG_MASK_3 0x0 -#define TEGRA210_XBAR_UPDATE_MAX_REG 3 +#define TEGRA210_XBAR_UPDATE_MAX_REG 3 #define TEGRA186_XBAR_REG_MASK_0 0xF3FFFFF #define TEGRA186_XBAR_REG_MASK_1 0x3F310F1F #define TEGRA186_XBAR_REG_MASK_2 0xFF3CF311 #define TEGRA186_XBAR_REG_MASK_3 0x3F0F00FF -#define TEGRA186_XBAR_UPDATE_MAX_REG 4 +#define TEGRA186_XBAR_UPDATE_MAX_REG 4 #define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG) /* T210 Modules Base address */ -#define T210_ADMAIF_BASE_ADDR 0x702d0000 +#define T210_ADMAIF_BASE_ADDR 0x702d0000 #define T210_I2S1_BASE_ADDR 0x702d1000 #define T210_I2S2_BASE_ADDR 0x702d1100 #define T210_I2S3_BASE_ADDR 0x702d1200 @@ -191,15 +116,15 @@ #define T210_MVC2_BASE_ADDR 0x702da200 #define T210_IQC1_BASE_ADDR 0x702de000 #define T210_IQC2_BASE_ADDR 0x702de200 -#define T210_DMIC1_BASE_ADDR 0x702d4000 -#define T210_DMIC2_BASE_ADDR 0x702d4100 -#define T210_DMIC3_BASE_ADDR 0x702d4200 +#define T210_DMIC1_BASE_ADDR 0x702d4000 +#define T210_DMIC2_BASE_ADDR 0x702d4100 +#define T210_DMIC3_BASE_ADDR 0x702d4200 #define T210_OPE1_BASE_ADDR 0x702d8000 #define T210_OPE2_BASE_ADDR 0x702d8400 -#define T210_AMIXER1_BASE_ADDR 0x702dbb00 +#define T210_AMIXER1_BASE_ADDR 0x702dbb00 /* T186 Modules Base address */ -#define T186_ADMAIF_BASE_ADDR 0x0290F000 +#define T186_ADMAIF_BASE_ADDR 0x0290F000 #define T186_I2S1_BASE_ADDR 0x02901000 #define T186_I2S2_BASE_ADDR 0x02901100 #define T186_I2S3_BASE_ADDR 0x02901200 @@ -228,16 +153,16 @@ #define T186_MVC2_BASE_ADDR 0x0290A200 #define T186_IQC1_BASE_ADDR 0x0290E000 #define T186_IQC2_BASE_ADDR 0x0290E200 -#define T186_DMIC1_BASE_ADDR 0x02904000 -#define T186_DMIC2_BASE_ADDR 0x02904100 -#define T186_DMIC3_BASE_ADDR 0x02904200 -#define T186_DMIC4_BASE_ADDR 0x02904300 +#define T186_DMIC1_BASE_ADDR 0x02904000 +#define T186_DMIC2_BASE_ADDR 0x02904100 +#define T186_DMIC3_BASE_ADDR 0x02904200 +#define T186_DMIC4_BASE_ADDR 0x02904300 #define T186_OPE1_BASE_ADDR 0x02908000 -#define T186_AMIXER1_BASE_ADDR 0x0290BB00 -#define T186_ASRC1_BASE_ADDR 0x02910000 -#define T186_ARAD1_BASE_ADDR 0x0290E400 -#define T186_DSPK1_BASE_ADDR 0x02905000 -#define T186_DSPK2_BASE_ADDR 0x02905100 +#define T186_AMIXER1_BASE_ADDR 0x0290BB00 +#define T186_ASRC1_BASE_ADDR 0x02910000 +#define T186_ARAD1_BASE_ADDR 0x0290E400 +#define T186_DSPK1_BASE_ADDR 0x02905000 +#define T186_DSPK2_BASE_ADDR 0x02905100 struct tegra210_xbar_cif_conf { diff --git a/sound/soc/tegra-alt/utils/tegra210_xbar_utils_alt.c b/sound/soc/tegra-alt/utils/tegra210_xbar_utils_alt.c index 24383dc6..1a2178ec 100644 --- a/sound/soc/tegra-alt/utils/tegra210_xbar_utils_alt.c +++ b/sound/soc/tegra-alt/utils/tegra210_xbar_utils_alt.c @@ -87,8 +87,7 @@ void tegra210_xbar_write_ahubram(struct regmap *regmap, unsigned int reg_ctrl, unsigned int val = 0; int i = 0; - val = (ram_offset << TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_SHIFT) & - TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK; + val = ram_offset & TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK; val |= TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN; val |= TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN; val |= TEGRA210_AHUBRAMCTL_CTRL_RW_WRITE; @@ -108,8 +107,7 @@ void tegra210_xbar_read_ahubram(struct regmap *regmap, unsigned int reg_ctrl, unsigned int val = 0; int i = 0; - val = (ram_offset << TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_SHIFT) & - TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK; + val = ram_offset & TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK; val |= TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN; val |= TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN; val |= TEGRA210_AHUBRAMCTL_CTRL_RW_READ;