diff --git a/drivers/video/tegra/host/nvdla/axi/Makefile b/drivers/video/tegra/host/nvdla/axi/Makefile
index 3284a84a..b396f8b9 100644
--- a/drivers/video/tegra/host/nvdla/axi/Makefile
+++ b/drivers/video/tegra/host/nvdla/axi/Makefile
@@ -26,6 +26,7 @@ ccflags-y += -DNVDLA_HAVE_CONFIG_HW_PERFMON=0
 ccflags-y += -DNVDLA_HAVE_CONFIG_AXI=1
 ccflags-y += -DNVDLA_HAVE_CONFIG_SYNCPTFD=0
 ccflags-y += -DNVDLA_HAVE_CONFIG_HSIERRINJ=0
+ccflags-y += -DNVDLA_HAVE_CONFIG_FIREWALL=0
 ccflags-y += -DBUG_4942853=1
 ccflags-y += -DBUG_4960393=1
 ccflags-y += -DBUG_4972382=1
diff --git a/drivers/video/tegra/host/nvdla/nvdla_t25x.h b/drivers/video/tegra/host/nvdla/nvdla_t25x.h
index dfa01ee2..c784d08d 100644
--- a/drivers/video/tegra/host/nvdla/nvdla_t25x.h
+++ b/drivers/video/tegra/host/nvdla/nvdla_t25x.h
@@ -43,7 +43,11 @@ static struct nvhost_device_data t25x_nvdla0_info = {
 	.engine_can_cg		= false,
 	.can_powergate		= true,
 	.icc_id			= TEGRA_ICC_DLA_0,
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	.transcfg_addr		= 0x2244,
+#else
 	.transcfg_addr		= 0x0444,
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 	.transcfg_val		= 0x201,
 	.firmware_not_in_subdir = true,
 };
@@ -78,7 +82,11 @@ static struct nvhost_device_data t25x_nvdla1_info = {
 	.engine_can_cg		= false,
 	.can_powergate		= true,
 	.icc_id			= TEGRA_ICC_DLA_1,
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	.transcfg_addr		= 0x2244,
+#else
 	.transcfg_addr		= 0x0444,
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 	.transcfg_val		= 0x201,
 	.firmware_not_in_subdir = true,
 };
diff --git a/drivers/video/tegra/host/nvdla/nvdla_t264_sim.h b/drivers/video/tegra/host/nvdla/nvdla_t264_sim.h
index a68b9b46..302308d8 100644
--- a/drivers/video/tegra/host/nvdla/nvdla_t264_sim.h
+++ b/drivers/video/tegra/host/nvdla/nvdla_t264_sim.h
@@ -39,7 +39,11 @@ static struct nvhost_device_data t264_sim_nvdla0_info = {
 	.engine_can_cg		= false,
 	.can_powergate		= true,
 	.icc_id			= TEGRA_ICC_DLA_0,
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	.transcfg_addr		= 0x2244,
+#else
 	.transcfg_addr		= 0x0444,
+#endif  /* NVDLA_HAVE_CONFIG_FIREWALL */
 	.transcfg_val		= 0x201,
 	.firmware_not_in_subdir = true,
 };
diff --git a/drivers/video/tegra/host/nvdla/port/fw/nvdla_fw_riscv.c b/drivers/video/tegra/host/nvdla/port/fw/nvdla_fw_riscv.c
index e285573f..a24e708c 100644
--- a/drivers/video/tegra/host/nvdla/port/fw/nvdla_fw_riscv.c
+++ b/drivers/video/tegra/host/nvdla/port/fw/nvdla_fw_riscv.c
@@ -372,9 +372,6 @@ static int32_t s_riscv_finalize_poweron(struct platform_device *pdev)
 		nvdla_dbg_err(pdev, "firmware load err: %d\n", err);
 		goto fail;
 	}
-	/* Falcon will use ctxdma 2 to access ucode imem/dmem */
-	nvdla_device_register_write(pdev, pdata->transcfg_addr,
-		pdata->transcfg_val);
 
 #if defined(BUG_4960393) && (BUG_4960393 == 1)
 	if ((pdata->class == NV_DLA0_SIM_CLASS_ID) ||
@@ -392,6 +389,10 @@ static int32_t s_riscv_finalize_poweron(struct platform_device *pdev)
 #endif /* BUG_4960393 */
 
 	if (!skip_boot) {
+		/* Falcon will use ctxdma 2 to access ucode imem/dmem */
+		nvdla_device_register_write(pdev, pdata->transcfg_addr,
+			pdata->transcfg_val);
+
 		err = s_riscv_boot(riscv);
 		if (err < 0) {
 			nvdla_dbg_err(pdev, "boot err: %d\n", err);
diff --git a/drivers/video/tegra/host/nvdla/port/fw/nvdla_fw_riscv_reg.h b/drivers/video/tegra/host/nvdla/port/fw/nvdla_fw_riscv_reg.h
index f3ce6e4c..7a5a5e1b 100644
--- a/drivers/video/tegra/host/nvdla/port/fw/nvdla_fw_riscv_reg.h
+++ b/drivers/video/tegra/host/nvdla/port/fw/nvdla_fw_riscv_reg.h
@@ -41,13 +41,21 @@
 static inline uint32_t riscv_mthdwdat_r(void)
 {
 	/* NV_PNVDLA_FALCON_MTHDWDAT */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x0000206cU;
+#else
 	return 0x0000006cU;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_mthdid_r(void)
 {
 	/* NV_PNVDLA_FALCON_MTHDID */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002068U;
+#else
 	return 0x00000068U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_mthdid_wpend_v(uint32_t r)
@@ -65,25 +73,41 @@ static inline uint32_t riscv_mthdid_wpend_done_v(void)
 static inline uint32_t riscv_mailbox0_r(void)
 {
 	/* NV_PNVDLA_FALCON_MAILBOX0 */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002040U;
+#else
 	return 0x00000040U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_mailbox1_r(void)
 {
 	/* NV_PNVDLA_FALCON_MAILBOX1 */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002044U;
+#else
 	return 0x00000044U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_irqstat_r(void)
 {
 	/* NV_PNVDLA_FALCON_IRQSTAT */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002008U;
+#else
 	return 0x00000008U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_irqmclr_r(void)
 {
 	/* NV_PNVDLA_RISCV_IRQMCLR */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002324U;
+#else
 	return 0x00000d24U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_irqmclr_swgen0_set_f(void)
@@ -101,7 +125,11 @@ static inline uint32_t riscv_irqmclr_swgen1_set_f(void)
 static inline uint32_t riscv_irqsclr_r(void)
 {
 	/* NV_PNVDLA_FALCON_IRQSCLR */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002004U;
+#else
 	return 0x00000004U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_irqsclr_swgen0_set_f(void)
@@ -119,7 +147,11 @@ static inline uint32_t riscv_irqsclr_swgen1_set_f(void)
 static inline uint32_t riscv_dmatrfcmd_r(void)
 {
 	/* NV_PNVDLA_FALCON_DMATRFCMD */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002118U;
+#else
 	return 0x00000118U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_dmatrfcmd_idle_v(uint32_t r)
@@ -161,24 +193,40 @@ static inline uint32_t riscv_transcfg_falc_swid_v(void)
 static inline uint32_t riscv_dmatrfbase_r(void)
 {
 	/* NV_PNVDLA_FALCON_DMATRFBASE */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002110U;
+#else
 	return 0x00000110U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_dmatrfmoffs_r(void)
 {
 	/* NV_PNVDLA_FALCON_DMATRFMOFFS */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002114U;
+#else
 	return 0x00000114U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 static inline uint32_t riscv_dmatrffboffs_r(void)
 {
 	/* NV_PNVDLA_FALCON_DMATRFFBOFFS */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x0000211cU;
+#else
 	return 0x0000011cU;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_dmactl_r(void)
 {
 	/* NV_PNVDLA_FALCON_DMACTL */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x0000210cU;
+#else
 	return 0x0000010cU;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_dmactl_dmem_scrubbing_m(void)
@@ -196,7 +244,11 @@ static inline uint32_t riscv_dmactl_imem_scrubbing_m(void)
 static inline uint32_t riscv_itfen_r(void)
 {
 	/* NV_PNVDLA_FALCON_ITFEN */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002048U;
+#else
 	return 0x00000048U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_itfen_ctxen_enable_f(void)
@@ -214,7 +266,11 @@ static inline uint32_t riscv_itfen_mthden_enable_f(void)
 static inline uint32_t riscv_cpuctl_r(void)
 {
 	/* NV_PNVDLA_RISCV_CPUCTL */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002288U;
+#else
 	return 0x00000b88U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_cpuctl_startcpu_true_f(void)
@@ -226,7 +282,11 @@ static inline uint32_t riscv_cpuctl_startcpu_true_f(void)
 static inline uint32_t riscv_irqtype_r(void)
 {
 	/* NV_PNVDLA_RISCV_IRQTYPE */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002330U;
+#else
 	return 0x00000d30U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_irqtype_swgen0_host_nonstall_f(void)
@@ -244,19 +304,31 @@ static inline uint32_t riscv_irqtype_swgen1_host_nonstall_f(void)
 static inline uint32_t riscv_boot_vector_lo_r(void)
 {
 	/* NV_PNVDLA_RISCV_BOOT_VECTOR_LO */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002280U;
+#else
 	return 0x00000b80U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_boot_vector_hi_r(void)
 {
 	/* NV_PNVDLA_RISCV_BOOT_VECTOR_HI */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002284U;
+#else
 	return 0x00000b84U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_bcr_ctrl_r(void)
 {
 	/* NV_PNVDLA_RISCV_BCR_CTRL */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002388U;
+#else
 	return 0x00000e68U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_bcr_ctrl_core_select_v(uint32_t r)
@@ -298,19 +370,31 @@ static inline uint32_t riscv_bcr_ctrl_valid_true_v(void)
 static inline uint32_t riscv_idlestate_r(void)
 {
 	/* NV_PNVDLA_FALCON_IDLESTATE */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x0000204cU;
+#else
 	return 0x0000004cU;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_os_version_r(void)
 {
 	/* NV_PNVDLA_FALCON_OS */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return 0x00002080U;
+#else
 	return 0x00000080U;
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_imemc_r(uint32_t index)
 {
 	/* NV_PNVDLA_FALCON_IMEM(i) */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return (0x00002180U + ((index) * 16));
+#else
 	return (0x00000180U + ((index) * 16));
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_imemc_aincw_true_f(void)
@@ -322,13 +406,21 @@ static inline uint32_t riscv_imemc_aincw_true_f(void)
 static inline uint32_t riscv_imemd_r(uint32_t index)
 {
 	/* NV_PNVDLA_FALCON_IMEMD(i) */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return (0x00002184U + ((index) * 16));
+#else
 	return (0x00000184U + ((index) * 16));
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_dmemc_r(uint32_t index)
 {
 	/* NV_PNVDLA_FALCON_DMEMC(i) */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return (0x000021c0U + ((index) * 8));
+#else
 	return (0x000001c0U + ((index) * 8));
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 
 static inline uint32_t riscv_dmemc_aincw_true_f(void)
@@ -340,6 +432,10 @@ static inline uint32_t riscv_dmemc_aincw_true_f(void)
 static inline uint32_t riscv_dmemd_r(uint32_t index)
 {
 	/* NV_PNVDLA_FALCON_DMEMD(i) */
+#if defined(NVDLA_HAVE_CONFIG_FIREWALL) && (NVDLA_HAVE_CONFIG_FIREWALL == 1)
+	return (0x000021c4U + ((index) * 8));
+#else
 	return (0x000001c4U + ((index) * 8));
+#endif /* NVDLA_HAVE_CONFIG_FIREWALL */
 }
 #endif /* End of __NVDLA_FW_RISCV_REG_H__ */