diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c index a23fa2be..085cc621 100644 --- a/drivers/gpu/drm/tegra/nvdec.c +++ b/drivers/gpu/drm/tegra/nvdec.c @@ -3,6 +3,7 @@ * Copyright (c) 2015-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved. */ +#include #include #include #include @@ -29,14 +30,23 @@ #include "riscv.h" #include "util.h" -#define NVDEC_FW_MTHD_ADDR_ACTMON_WEIGHT 0xC9U +#define NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_MASK 0xCAU +#define NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_BORPS 0xCBU +#define NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_WEIGHT 0xC9U #define NVDEC_FALCON_UCLASS_METHOD_OFFSET 0x40 #define NVDEC_FALCON_UCLASS_METHOD_DATA 0x44 #define NVDEC_FALCON_DEBUGINFO 0x1094 #define NVDEC_TFBIF_TRANSCFG 0x2c44 +#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK 0x2c4c +#define NVDEC_TFBIF_ACTMON_ACTIVE_BORPS 0x2c50 #define NVDEC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x2c54 #define NVDEC_AXI_RW_BANDWIDTH 512 +#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0) +#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1) +#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2) +#define NVDEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7) + struct nvdec_config { const char *firmware; unsigned int version; @@ -109,7 +119,7 @@ static int nvdec_set_rate(struct nvdec *nvdec, unsigned long rate) nvdec_writel(nvdec, weight, NVDEC_TFBIF_ACTMON_ACTIVE_WEIGHT); } else { nvdec_writel(nvdec, - NVDEC_FW_MTHD_ADDR_ACTMON_WEIGHT, + NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_WEIGHT, NVDEC_FALCON_UCLASS_METHOD_OFFSET); nvdec_writel(nvdec, weight, NVDEC_FALCON_UCLASS_METHOD_DATA); } @@ -523,6 +533,22 @@ static __maybe_unused int nvdec_runtime_resume(struct device *dev) err = nvdec_boot_riscv(nvdec); if (err < 0) goto disable; + + nvdec_writel(nvdec, + NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_MASK, + NVDEC_FALCON_UCLASS_METHOD_OFFSET); + nvdec_writel(nvdec, + NVDEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED | + NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED | + NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED, + NVDEC_FALCON_UCLASS_METHOD_DATA); + + nvdec_writel(nvdec, + NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_BORPS, + NVDEC_FALCON_UCLASS_METHOD_OFFSET); + nvdec_writel(nvdec, + NVDEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE, + NVDEC_FALCON_UCLASS_METHOD_DATA); } else { err = nvdec_load_falcon_firmware(nvdec); if (err < 0) @@ -531,6 +557,16 @@ static __maybe_unused int nvdec_runtime_resume(struct device *dev) err = nvdec_boot_falcon(nvdec); if (err < 0) goto disable; + + nvdec_writel(nvdec, + NVDEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED | + NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED | + NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED, + NVDEC_TFBIF_ACTMON_ACTIVE_MASK); + + nvdec_writel(nvdec, + NVDEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE, + NVDEC_TFBIF_ACTMON_ACTIVE_BORPS); } devfreq_resume_device(nvdec->devfreq); diff --git a/drivers/gpu/drm/tegra/nvenc.c b/drivers/gpu/drm/tegra/nvenc.c index 7eb63787..e6f5ddda 100644 --- a/drivers/gpu/drm/tegra/nvenc.c +++ b/drivers/gpu/drm/tegra/nvenc.c @@ -3,6 +3,7 @@ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved. */ +#include #include #include #include @@ -27,9 +28,16 @@ #include "util.h" #define NVENC_TFBIF_TRANSCFG 0x1844 +#define NVENC_TFBIF_ACTMON_ACTIVE_MASK 0x184c +#define NVENC_TFBIF_ACTMON_ACTIVE_BORPS 0x1850 #define NVENC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x1854 #define NVENC_AXI_RW_BANDWIDTH 512 +#define NVENC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0) +#define NVENC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1) +#define NVENC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2) +#define NVENC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7) + struct nvenc_config { const char *firmware; unsigned int version; @@ -444,6 +452,16 @@ static __maybe_unused int nvenc_runtime_resume(struct device *dev) if (err < 0) goto disable; + nvenc_writel(nvenc, + NVENC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED | + NVENC_TFBIF_ACTMON_ACTIVE_MASK_STALLED | + NVENC_TFBIF_ACTMON_ACTIVE_MASK_STARVED, + NVENC_TFBIF_ACTMON_ACTIVE_MASK); + + nvenc_writel(nvenc, + NVENC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE, + NVENC_TFBIF_ACTMON_ACTIVE_BORPS); + devfreq_resume_device(nvenc->devfreq); return 0; diff --git a/drivers/gpu/drm/tegra/nvjpg.c b/drivers/gpu/drm/tegra/nvjpg.c index 41b03ecf..44a6ca44 100644 --- a/drivers/gpu/drm/tegra/nvjpg.c +++ b/drivers/gpu/drm/tegra/nvjpg.c @@ -3,6 +3,7 @@ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved. */ +#include #include #include #include @@ -27,9 +28,16 @@ #include "util.h" #define NVJPG_TFBIF_TRANSCFG 0x1444 +#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK 0x144c +#define NVJPG_TFBIF_ACTMON_ACTIVE_BORPS 0x1450 #define NVJPG_TFBIF_ACTMON_ACTIVE_WEIGHT 0x1454 #define NVJPG_AXI_RW_BANDWIDTH 512 +#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0) +#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1) +#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2) +#define NVJPG_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7) + struct nvjpg_config { const char *firmware; unsigned int version; @@ -443,6 +451,16 @@ static __maybe_unused int nvjpg_runtime_resume(struct device *dev) if (err < 0) goto disable; + nvjpg_writel(nvjpg, + NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STARVED | + NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STALLED | + NVJPG_TFBIF_ACTMON_ACTIVE_MASK_DELAYED, + NVJPG_TFBIF_ACTMON_ACTIVE_MASK); + + nvjpg_writel(nvjpg, + NVJPG_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE, + NVJPG_TFBIF_ACTMON_ACTIVE_BORPS); + devfreq_resume_device(nvjpg->devfreq); return 0; diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c index 358adb5a..7f877944 100644 --- a/drivers/gpu/drm/tegra/vic.c +++ b/drivers/gpu/drm/tegra/vic.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2023 NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include @@ -507,6 +508,16 @@ static int __maybe_unused vic_runtime_resume(struct device *dev) if (err < 0) goto assert; + vic_writel(vic, + VIC_TFBIF_ACTMON_ACTIVE_MASK_STARVED | + VIC_TFBIF_ACTMON_ACTIVE_MASK_STALLED | + VIC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED, + NV_PVIC_TFBIF_ACTMON_ACTIVE_MASK); + + vic_writel(vic, + VIC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE, + NV_PVIC_TFBIF_ACTMON_ACTIVE_BORPS); + devfreq_resume_device(vic->devfreq); return 0; diff --git a/drivers/gpu/drm/tegra/vic.h b/drivers/gpu/drm/tegra/vic.h index 38daa510..ba292468 100644 --- a/drivers/gpu/drm/tegra/vic.h +++ b/drivers/gpu/drm/tegra/vic.h @@ -18,8 +18,15 @@ #define CG_IDLE_CG_EN (1 << 6) #define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16) +#define NV_PVIC_TFBIF_ACTMON_ACTIVE_MASK 0x0000204c +#define NV_PVIC_TFBIF_ACTMON_ACTIVE_BORPS 0x00002050 #define NV_PVIC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x00002054 +#define VIC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0) +#define VIC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1) +#define VIC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2) +#define VIC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7) + #define VIC_TFBIF_TRANSCFG 0x00002044 /* Firmware offsets */