ASoC: tegra: Provision for fixed PLL config

Tegra Audio HW subsystem has many I/O module instances and currently a
single PLL source is used for all these modules. Any I2S configuration
is supported now by dynamically updating PLL base rate. But as of today
this has few limitations.

  - AUD_MCLK factor is not considered while updating PLL base rate.

  - Two module instances can request conflicting PLL base rate and
    the last request overrides existing session. This would also mean
    simultaneous 8x and 11x configurations are not possible.

  - Tegra210 has problems with specific PLL requests.

Multiple PLLs would be required if concurrent audio sessions need to be
supported and dynamic rate update is needed to support any configuration.
But this has few limitions too.

  - Since number of available PLLs for modules are limited, specific PLL
    cannot be dedicated to a module. The PLL would be shared and may
    cause problems when there are simultaneous conflicting requirements.

  - Logic for runtime distribution of PLLs to modules and rate updates
    has to be managed in module drivers only as machine driver does not
    have intelligence to know for which audio path exactly the hw_param()
    call comes. This can make the code complicated and buggy where each
    module driver tries to control specific PLL.

Instead the problem can be simplified by fixing PLL rates in DT. User
can employ one or more PLLs to realize their design. Of course this won't
support all configurations simultaneously since this is not what users
require generally. They have specific requirements which can be addressed
via DT configurations. For example,

  - Some users may use single PLL and decide on compatible set of audio
    configurations for their use cases.

  - Some users may want to use two PLLs, one each for 8x and 11x. Then
    via DT specific modules can use specific PLL sources to realize
    simultaneous 8x and 11x configurations. In fact two PLLs can be
    used when there are conflicting requirements which cannot be met
    by a single PLL source.

To realize above add new DT property "fixed-pll" and bypass PLL rate
updates from the driver. Users can populate this in their platform
sound DT node, whenever static configurations are preferred.

Bug 200726704

Change-Id: I0416f201fd26c49bb6c09594d86394c46a0bbad2
(cherry-picked from commit 0c84a3fe1e2e40d20ddb449a948da6fdebd85efe)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2548361
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Change-Id: I51d5b502f728baee2d6d075951dc186503cbf76f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.10/+/2556536
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

sound/soc/tegra/tegra_asoc_machine.c

@@ -449,6 +449,7 @@ cleanup:
 int parse_card_info(struct snd_soc_card *card, struct snd_soc_ops *pcm_ops,
 		    struct snd_soc_compr_ops *compr_ops)
 {
+	struct tegra_machine *machine = snd_soc_card_get_drvdata(card);
 	struct device_node *node = card->dev->of_node;
 	int ret;
 
@@ -478,6 +479,11 @@ int parse_card_info(struct snd_soc_card *card, struct snd_soc_ops *pcm_ops,
 
 	parse_mclk_fs(card);
 
+	if (of_property_read_bool(node, "fixed-pll")) {
+		machine->audio_clock.fixed_pll = true;
+		dev_info(card->dev, "PLL configuration is fixed from DT\n");
+	}
+
 	ret = parse_dt_dai_links(card, pcm_ops, compr_ops);
 	if (ret < 0)
 		return ret;

sound/soc/tegra/tegra_asoc_utils.c

@@ -175,6 +175,9 @@ int tegra_asoc_utils_set_tegra210_rate(struct tegra_asoc_utils_data *data,
 	unsigned int new_pll_base, pll_out, aud_mclk = 0;
 	int err;
 
+	if (data->fixed_pll)
+		goto update_mclk_rate;
+
 	switch (sample_rate) {
 	case 11025:
 	case 22050:
@@ -200,8 +203,6 @@ int tegra_asoc_utils_set_tegra210_rate(struct tegra_asoc_utils_data *data,
 	/* reduce pll_out rate to support lower sampling rates */
 	if (sample_rate <= 11025)
 		pll_out = pll_out >> 1;
-	if (data->mclk_fs)
-		aud_mclk = sample_rate * data->mclk_fs;
 
 	if (data->set_baseclock != new_pll_base) {
 		err = clk_set_rate(data->clk_pll_a, new_pll_base);
@@ -223,6 +224,10 @@ int tegra_asoc_utils_set_tegra210_rate(struct tegra_asoc_utils_data *data,
 		data->set_pll_out = pll_out;
 	}
 
+update_mclk_rate:
+	if (data->mclk_fs)
+		aud_mclk = sample_rate * data->mclk_fs;
+
 	if (data->set_mclk != aud_mclk) {
 		err = clk_set_rate(data->clk_cdev1, aud_mclk);
 		if (err) {

sound/soc/tegra/tegra_asoc_utils.h

@@ -3,7 +3,7 @@
  * tegra_asoc_utils.h - Definitions for Tegra DAS driver
  *
  * Author: Stephen Warren <swarren@nvidia.com>
- * Copyright (C) 2010,2012 - NVIDIA, Inc.
+ * Copyright (c) 2010,2012-2021, NVIDIA CORPORATION.  All rights reserved.
  */
 
 #ifndef __TEGRA_ASOC_UTILS_H__
@@ -33,6 +33,7 @@ struct tegra_asoc_utils_data {
 	unsigned int set_pll_out;
 	unsigned int *pll_base_rate;
 	unsigned int mclk_fs;
+	bool fixed_pll;
 };
 
 int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,