From 43b4285832ddcf189318e368f7c85f9bb2f855f8 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Mon, 3 May 2021 18:31:56 +0530 Subject: [PATCH] ASoC: tegra: Cleanup macros in AMX/ADX driver Remove unused macros in AMX/ADX driver and use shorter names for remaining macros wherever possible. This makes code look relatively compact and cleaner. Currently in AMX driver, Tegra210 regmap readable/writeable_reg() callbacks use Tegra194 specific register range. As this looks incorrect, maintain separate callbacks for readable/writeable_reg() for Tegra210 and Tegra194. Use register range in these callbacks to make it compact. Bug 200698314 Change-Id: Iae466da9aaef722736ccaf49a490a3b24b6d683a Signed-off-by: Sameer Pujar --- sound/soc/tegra/tegra210_adx.c | 128 ++++++++-------------- sound/soc/tegra/tegra210_adx.h | 151 ++++++++------------------ sound/soc/tegra/tegra210_amx.c | 164 ++++++++++++----------------- sound/soc/tegra/tegra210_amx.h | 187 +++++++++++---------------------- 4 files changed, 214 insertions(+), 416 deletions(-) diff --git a/sound/soc/tegra/tegra210_adx.c b/sound/soc/tegra/tegra210_adx.c index 2c2eb9bb..2a86d12b 100644 --- a/sound/soc/tegra/tegra210_adx.c +++ b/sound/soc/tegra/tegra210_adx.c @@ -23,15 +23,15 @@ #include "tegra_cif.h" static const struct reg_default tegra210_adx_reg_defaults[] = { - { TEGRA210_ADX_AXBAR_RX_INT_MASK, 0x00000001}, - { TEGRA210_ADX_AXBAR_RX_CIF_CTRL, 0x00007000}, - { TEGRA210_ADX_AXBAR_TX_INT_MASK, 0x0000000f }, - { TEGRA210_ADX_AXBAR_TX1_CIF_CTRL, 0x00007000}, - { TEGRA210_ADX_AXBAR_TX2_CIF_CTRL, 0x00007000}, - { TEGRA210_ADX_AXBAR_TX3_CIF_CTRL, 0x00007000}, - { TEGRA210_ADX_AXBAR_TX4_CIF_CTRL, 0x00007000}, + { TEGRA210_ADX_RX_INT_MASK, 0x00000001}, + { TEGRA210_ADX_RX_CIF_CTRL, 0x00007000}, + { TEGRA210_ADX_TX_INT_MASK, 0x0000000f }, + { TEGRA210_ADX_TX1_CIF_CTRL, 0x00007000}, + { TEGRA210_ADX_TX2_CIF_CTRL, 0x00007000}, + { TEGRA210_ADX_TX3_CIF_CTRL, 0x00007000}, + { TEGRA210_ADX_TX4_CIF_CTRL, 0x00007000}, { TEGRA210_ADX_CG, 0x1}, - { TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, 0x00004000}, + { TEGRA210_ADX_CFG_RAM_CTRL, 0x00004000}, }; /** @@ -116,20 +116,20 @@ static void tegra210_adx_write_map_ram(struct tegra210_adx *adx, { unsigned int reg; - regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, - (addr << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RAM_ADDR_SHIFT)); + regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, + (addr << TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT)); - regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_DATA, val); + regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_DATA, val); - regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, ®); - reg |= TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN; + regmap_read(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, ®); + reg |= TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN; - regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, reg); + regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, reg); - regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, ®); - reg |= TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_WRITE; + regmap_read(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, ®); + reg |= TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE; - regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, reg); + regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, reg); } static void tegra210_adx_update_map_ram(struct tegra210_adx *adx) @@ -182,23 +182,23 @@ static unsigned int __maybe_unused unsigned int val; int err; - regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, - (addr << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RAM_ADDR_SHIFT)); + regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, + (addr << TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT)); - regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, &val); - val |= TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN; - regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, val); - regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, &val); - val &= ~(TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_WRITE); - regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, val); + regmap_read(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, &val); + val |= TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN; + regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, val); + regmap_read(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, &val); + val &= ~(TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE); + regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, val); err = regmap_read_poll_timeout(adx->regmap, - TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, + TEGRA210_ADX_CFG_RAM_CTRL, val, !(val & 0x80000000), 10, 10000); if (err < 0) return err; - regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_DATA, &val); + regmap_read(adx->regmap, TEGRA210_ADX_CFG_RAM_DATA, &val); return val; } @@ -279,7 +279,7 @@ static int tegra210_adx_out_hw_params(struct snd_pcm_substream *substream, channels = params_channels(params); return tegra210_adx_set_audio_cif(dai, channels, params_format(params), - TEGRA210_ADX_AXBAR_TX1_CIF_CTRL + + TEGRA210_ADX_TX1_CIF_CTRL + (dai->id * TEGRA210_ADX_AUDIOCIF_CH_STRIDE)); } @@ -320,7 +320,7 @@ static int tegra210_adx_in_hw_params(struct snd_pcm_substream *substream, channels = params_channels(params); return tegra210_adx_set_audio_cif(dai, channels, params_format(params), - TEGRA210_ADX_AXBAR_RX_CIF_CTRL); + TEGRA210_ADX_RX_CIF_CTRL); } static int tegra210_adx_set_channel_map(struct snd_soc_dai *dai, @@ -639,26 +639,11 @@ static bool tegra210_adx_wr_reg(struct device *dev, unsigned int reg) { switch (reg) { - case TEGRA210_ADX_AXBAR_TX_INT_MASK: - case TEGRA210_ADX_AXBAR_TX_INT_SET: - case TEGRA210_ADX_AXBAR_TX_INT_CLEAR: - case TEGRA210_ADX_AXBAR_TX1_CIF_CTRL: - case TEGRA210_ADX_AXBAR_TX2_CIF_CTRL: - case TEGRA210_ADX_AXBAR_TX3_CIF_CTRL: - case TEGRA210_ADX_AXBAR_TX4_CIF_CTRL: - case TEGRA210_ADX_AXBAR_RX_INT_MASK: - case TEGRA210_ADX_AXBAR_RX_INT_SET: - case TEGRA210_ADX_AXBAR_RX_INT_CLEAR: - case TEGRA210_ADX_AXBAR_RX_CIF_CTRL: - case TEGRA210_ADX_ENABLE: - case TEGRA210_ADX_SOFT_RESET: - case TEGRA210_ADX_CG: - case TEGRA210_ADX_CTRL: - case TEGRA210_ADX_IN_BYTE_EN0: - case TEGRA210_ADX_IN_BYTE_EN1: - case TEGRA210_ADX_CYA: - case TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL: - case TEGRA210_ADX_AHUBRAMCTL_ADX_DATA: + case TEGRA210_ADX_TX_INT_MASK ... TEGRA210_ADX_TX4_CIF_CTRL: + case TEGRA210_ADX_RX_INT_MASK ... TEGRA210_ADX_RX_CIF_CTRL: + case TEGRA210_ADX_ENABLE ... TEGRA210_ADX_CG: + case TEGRA210_ADX_CTRL ... TEGRA210_ADX_CYA: + case TEGRA210_ADX_CFG_RAM_CTRL ... TEGRA210_ADX_CFG_RAM_DATA: return true; default: return false; @@ -669,32 +654,7 @@ static bool tegra210_adx_rd_reg(struct device *dev, unsigned int reg) { switch (reg) { - case TEGRA210_ADX_AXBAR_RX_STATUS: - case TEGRA210_ADX_AXBAR_RX_INT_STATUS: - case TEGRA210_ADX_AXBAR_RX_INT_MASK: - case TEGRA210_ADX_AXBAR_RX_INT_SET: - case TEGRA210_ADX_AXBAR_RX_INT_CLEAR: - case TEGRA210_ADX_AXBAR_RX_CIF_CTRL: - case TEGRA210_ADX_AXBAR_TX_STATUS: - case TEGRA210_ADX_AXBAR_TX_INT_STATUS: - case TEGRA210_ADX_AXBAR_TX_INT_MASK: - case TEGRA210_ADX_AXBAR_TX_INT_SET: - case TEGRA210_ADX_AXBAR_TX_INT_CLEAR: - case TEGRA210_ADX_AXBAR_TX1_CIF_CTRL: - case TEGRA210_ADX_AXBAR_TX2_CIF_CTRL: - case TEGRA210_ADX_AXBAR_TX3_CIF_CTRL: - case TEGRA210_ADX_AXBAR_TX4_CIF_CTRL: - case TEGRA210_ADX_ENABLE: - case TEGRA210_ADX_SOFT_RESET: - case TEGRA210_ADX_CG: - case TEGRA210_ADX_STATUS: - case TEGRA210_ADX_INT_STATUS: - case TEGRA210_ADX_CTRL: - case TEGRA210_ADX_IN_BYTE_EN0: - case TEGRA210_ADX_IN_BYTE_EN1: - case TEGRA210_ADX_CYA: - case TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL: - case TEGRA210_ADX_AHUBRAMCTL_ADX_DATA: + case TEGRA210_ADX_RX_STATUS ... TEGRA210_ADX_CFG_RAM_DATA: return true; default: return false; @@ -705,17 +665,17 @@ static bool tegra210_adx_volatile_reg(struct device *dev, unsigned int reg) { switch (reg) { - case TEGRA210_ADX_AXBAR_RX_STATUS: - case TEGRA210_ADX_AXBAR_RX_INT_STATUS: - case TEGRA210_ADX_AXBAR_RX_INT_SET: - case TEGRA210_ADX_AXBAR_TX_STATUS: - case TEGRA210_ADX_AXBAR_TX_INT_STATUS: - case TEGRA210_ADX_AXBAR_TX_INT_SET: + case TEGRA210_ADX_RX_STATUS: + case TEGRA210_ADX_RX_INT_STATUS: + case TEGRA210_ADX_RX_INT_SET: + case TEGRA210_ADX_TX_STATUS: + case TEGRA210_ADX_TX_INT_STATUS: + case TEGRA210_ADX_TX_INT_SET: case TEGRA210_ADX_SOFT_RESET: case TEGRA210_ADX_STATUS: case TEGRA210_ADX_INT_STATUS: - case TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL: - case TEGRA210_ADX_AHUBRAMCTL_ADX_DATA: + case TEGRA210_ADX_CFG_RAM_CTRL: + case TEGRA210_ADX_CFG_RAM_DATA: return true; default: break; @@ -728,7 +688,7 @@ static const struct regmap_config tegra210_adx_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .max_register = TEGRA210_ADX_AHUBRAMCTL_ADX_DATA, + .max_register = TEGRA210_ADX_CFG_RAM_DATA, .writeable_reg = tegra210_adx_wr_reg, .readable_reg = tegra210_adx_rd_reg, .volatile_reg = tegra210_adx_volatile_reg, diff --git a/sound/soc/tegra/tegra210_adx.h b/sound/soc/tegra/tegra210_adx.h index 30f82dc7..49d45d87 100644 --- a/sound/soc/tegra/tegra210_adx.h +++ b/sound/soc/tegra/tegra210_adx.h @@ -11,128 +11,63 @@ #define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 4 -#define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 4 - /* Register offsets from TEGRA210_ADX*_BASE */ -#define TEGRA210_ADX_AXBAR_RX_STATUS 0x0c -#define TEGRA210_ADX_AXBAR_RX_INT_STATUS 0x10 -#define TEGRA210_ADX_AXBAR_RX_INT_MASK 0x14 -#define TEGRA210_ADX_AXBAR_RX_INT_SET 0x18 -#define TEGRA210_ADX_AXBAR_RX_INT_CLEAR 0x1c -#define TEGRA210_ADX_AXBAR_RX_CIF_CTRL 0x20 -#define TEGRA210_ADX_AXBAR_TX_STATUS 0x4c -#define TEGRA210_ADX_AXBAR_TX_INT_STATUS 0x50 -#define TEGRA210_ADX_AXBAR_TX_INT_MASK 0x54 -#define TEGRA210_ADX_AXBAR_TX_INT_SET 0x58 -#define TEGRA210_ADX_AXBAR_TX_INT_CLEAR 0x5c -#define TEGRA210_ADX_AXBAR_TX1_CIF_CTRL 0x60 -#define TEGRA210_ADX_AXBAR_TX2_CIF_CTRL 0x64 -#define TEGRA210_ADX_AXBAR_TX3_CIF_CTRL 0x68 -#define TEGRA210_ADX_AXBAR_TX4_CIF_CTRL 0x6c -#define TEGRA210_ADX_ENABLE 0x80 -#define TEGRA210_ADX_SOFT_RESET 0x84 -#define TEGRA210_ADX_CG 0x88 -#define TEGRA210_ADX_STATUS 0x8c -#define TEGRA210_ADX_INT_STATUS 0x90 -#define TEGRA210_ADX_CTRL 0xa4 -#define TEGRA210_ADX_IN_BYTE_EN0 0xa8 -#define TEGRA210_ADX_IN_BYTE_EN1 0xac -#define TEGRA210_ADX_CYA 0xb0 -#define TEGRA210_ADX_DBG 0xb4 -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL 0xb8 -#define TEGRA210_ADX_AHUBRAMCTL_ADX_DATA 0xbc - - -/* Fields in TEGRA210_ADX_AXBAR_RX_CIF_CTRL */ -/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_ahub.h */ - -/* Fields in TEGRA210_ADX_AXBAR_TX1_CIF_CTRL */ -/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_ahub.h */ - -/* Fields in TEGRA210_ADX_AXBAR_TX2_CIF_CTRL */ -/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_ahub.h */ - -/* Fields in TEGRA210_ADX_AXBAR_TX3_CIF_CTRL */ -/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_ahub.h */ - -/* Fields in TEGRA210_ADX_AXBAR_TX_CIF_CTRL */ -/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_ahub.h */ +#define TEGRA210_ADX_RX_STATUS 0x0c +#define TEGRA210_ADX_RX_INT_STATUS 0x10 +#define TEGRA210_ADX_RX_INT_MASK 0x14 +#define TEGRA210_ADX_RX_INT_SET 0x18 +#define TEGRA210_ADX_RX_INT_CLEAR 0x1c +#define TEGRA210_ADX_RX_CIF_CTRL 0x20 +#define TEGRA210_ADX_TX_STATUS 0x4c +#define TEGRA210_ADX_TX_INT_STATUS 0x50 +#define TEGRA210_ADX_TX_INT_MASK 0x54 +#define TEGRA210_ADX_TX_INT_SET 0x58 +#define TEGRA210_ADX_TX_INT_CLEAR 0x5c +#define TEGRA210_ADX_TX1_CIF_CTRL 0x60 +#define TEGRA210_ADX_TX2_CIF_CTRL 0x64 +#define TEGRA210_ADX_TX3_CIF_CTRL 0x68 +#define TEGRA210_ADX_TX4_CIF_CTRL 0x6c +#define TEGRA210_ADX_ENABLE 0x80 +#define TEGRA210_ADX_SOFT_RESET 0x84 +#define TEGRA210_ADX_CG 0x88 +#define TEGRA210_ADX_STATUS 0x8c +#define TEGRA210_ADX_INT_STATUS 0x90 +#define TEGRA210_ADX_CTRL 0xa4 +#define TEGRA210_ADX_IN_BYTE_EN0 0xa8 +#define TEGRA210_ADX_IN_BYTE_EN1 0xac +#define TEGRA210_ADX_CYA 0xb0 +#define TEGRA210_ADX_DBG 0xb4 +#define TEGRA210_ADX_CFG_RAM_CTRL 0xb8 +#define TEGRA210_ADX_CFG_RAM_DATA 0xbc /* Fields in TEGRA210_ADX_ENABLE */ -#define TEGRA210_ADX_ENABLE_SHIFT 0 -#define TEGRA210_ADX_ENABLE_MASK (1 << TEGRA210_ADX_ENABLE_SHIFT) -#define TEGRA210_ADX_EN (1 << TEGRA210_ADX_ENABLE_SHIFT) +#define TEGRA210_ADX_ENABLE_SHIFT 0 -/* Fields inTEGRA210_ADX_CTRL */ -#define TEGRA210_ADX_CTRL_TX4_FORCE_DISABLE_SHIFT 11 -#define TEGRA210_ADX_CTRL_TX4_FORCE_DISABLE_MASK (1 << TEGRA210_ADX_CTRL_TX4_FORCE_DISABLE_SHIFT) -#define TEGRA210_ADX_CTRL_TX4_FORCE_DISABLE_EN (1 << TEGRA210_ADX_CTRL_TX4_FORCE_DISABLE_SHIFT) +/* Fields in TEGRA210_ADX_CFG_RAM_CTRL */ +#define TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT 14 +#define TEGRA210_ADX_CFG_RAM_CTRL_RW_MASK (1 << TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT) +#define TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT) -#define TEGRA210_ADX_CTRL_TX3_FORCE_DISABLE_SHIFT 10 -#define TEGRA210_ADX_CTRL_TX3_FORCE_DISABLE_MASK (1 << TEGRA210_ADX_CTRL_TX3_FORCE_DISABLE_SHIFT) -#define TEGRA210_ADX_CTRL_TX3_FORCE_DISABLE_EN (1 << TEGRA210_ADX_CTRL_TX3_FORCE_DISABLE_SHIFT) +#define TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT 0 -#define TEGRA210_ADX_CTRL_TX2_FORCE_DISABLE_SHIFT 9 -#define TEGRA210_ADX_CTRL_TX2_FORCE_DISABLE_MASK (1 << TEGRA210_ADX_CTRL_TX2_FORCE_DISABLE_SHIFT) -#define TEGRA210_ADX_CTRL_TX2_FORCE_DISABLE_EN (1 << TEGRA210_ADX_CTRL_TX2_FORCE_DISABLE_SHIFT) - -#define TEGRA210_ADX_CTRL_TX1_FORCE_DISABLE_SHIFT 8 -#define TEGRA210_ADX_CTRL_TX1_FORCE_DISABLE_MASK (1 << TEGRA210_ADX_CTRL_TX1_FORCE_DISABLE_SHIFT) -#define TEGRA210_ADX_CTRL_TX1_FORCE_DISABLE_EN (1 << TEGRA210_ADX_CTRL_TX1_FORCE_DISABLE_SHIFT) - -#define TEGRA210_ADX_CTRL_TX4_ENABLE_SHIFT 3 -#define TEGRA210_ADX_CTRL_TX4_ENABLE_MASK (1 << TEGRA210_ADX_CTRL_TX4_ENABLE_SHIFT) -#define TEGRA210_ADX_CTRL_TX4_EN (1 << TEGRA210_ADX_CTRL_TX4_ENABLE_SHIFT) - -#define TEGRA210_ADX_CTRL_TX3_ENABLE_SHIFT 2 -#define TEGRA210_ADX_CTRL_TX3_ENABLE_MASK (1 << TEGRA210_ADX_CTRL_TX3_ENABLE_SHIFT) -#define TEGRA210_ADX_CTRL_TX3_EN (1 << TEGRA210_ADX_CTRL_TX3_ENABLE_SHIFT) - -#define TEGRA210_ADX_CTRL_TX2_ENABLE_SHIFT 1 -#define TEGRA210_ADX_CTRL_TX2_ENABLE_MASK (1 << TEGRA210_ADX_CTRL_TX2_ENABLE_SHIFT) -#define TEGRA210_ADX_CTRL_TX2_EN (1 << TEGRA210_ADX_CTRL_TX2_ENABLE_SHIFT) - -#define TEGRA210_ADX_CTRL_TX1_ENABLE_SHIFT 0 -#define TEGRA210_ADX_CTRL_TX1_ENABLE_MASK (1 << TEGRA210_ADX_CTRL_TX1_ENABLE_SHIFT) -#define TEGRA210_ADX_CTRL_TX1_EN (1 << TEGRA210_ADX_CTRL_TX1_ENABLE_SHIFT) - -/* Fields in TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL */ -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_READ_BUSY_SHIFT 31 -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_READ_BUSY_MASK (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_READ_BUSY_SHIFT) -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_READ_BUSY (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_READ_BUSY_SHIFT) - -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_READ_COUNT_SHIFT 16 -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_READ_COUNT_MASK (0xff << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_READ_COUNT_SHIFT) - -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_SHIFT 14 -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_MASK (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_SHIFT) -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_WRITE (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_SHIFT) - -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN_SHIFT 13 -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN_MASK (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN_SHIFT) -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN_SHIFT) - -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_ACCESS_EN_SHIFT 12 -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_ACCESS_EN_MASK (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_ACCESS_EN_SHIFT) -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_ACCESS_EN_SHIFT) - -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RAM_ADDR_SHIFT 0 -#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RAM_ADDR_MASK (0xff << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RAM_ADDR_SHIFT) +#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13 +#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_MASK (1 << TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT) +#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT) /* Fields in TEGRA210_ADX_SOFT_RESET */ -#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT 0 -#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) +#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT 0 +#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) #define TEGRA210_ADX_SOFT_RESET_SOFT_EN (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) -#define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) +#define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) /* - * Those defines are not in register field. + * These defines are not in register field. */ #define TEGRA210_ADX_NUM_OUTPUTS 4 -#define TEGRA210_ADX_RAM_DEPTH 16 +#define TEGRA210_ADX_RAM_DEPTH 16 #define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 6 -#define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2 -#define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0 +#define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2 +#define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0 enum { TEGRA210_ADX_TX_DISABLE, diff --git a/sound/soc/tegra/tegra210_amx.c b/sound/soc/tegra/tegra210_amx.c index 6e4edc40..cf45b40c 100644 --- a/sound/soc/tegra/tegra210_amx.c +++ b/sound/soc/tegra/tegra210_amx.c @@ -23,15 +23,15 @@ #include "tegra_cif.h" static const struct reg_default tegra210_amx_reg_defaults[] = { - { TEGRA210_AMX_AXBAR_RX_INT_MASK, 0x0000000f}, - { TEGRA210_AMX_AXBAR_RX1_CIF_CTRL, 0x00007000}, - { TEGRA210_AMX_AXBAR_RX2_CIF_CTRL, 0x00007000}, - { TEGRA210_AMX_AXBAR_RX3_CIF_CTRL, 0x00007000}, - { TEGRA210_AMX_AXBAR_RX4_CIF_CTRL, 0x00007000}, - { TEGRA210_AMX_AXBAR_TX_INT_MASK, 0x00000001}, - { TEGRA210_AMX_AXBAR_TX_CIF_CTRL, 0x00007000}, + { TEGRA210_AMX_RX_INT_MASK, 0x0000000f}, + { TEGRA210_AMX_RX1_CIF_CTRL, 0x00007000}, + { TEGRA210_AMX_RX2_CIF_CTRL, 0x00007000}, + { TEGRA210_AMX_RX3_CIF_CTRL, 0x00007000}, + { TEGRA210_AMX_RX4_CIF_CTRL, 0x00007000}, + { TEGRA210_AMX_TX_INT_MASK, 0x00000001}, + { TEGRA210_AMX_TX_CIF_CTRL, 0x00007000}, { TEGRA210_AMX_CG, 0x1}, - { TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, 0x00004000}, + { TEGRA210_AMX_CFG_RAM_CTRL, 0x00004000}, }; /** @@ -140,20 +140,20 @@ static void tegra210_amx_write_map_ram(struct tegra210_amx *amx, unsigned int val) { unsigned int reg; - regmap_write(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, - (addr << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RAM_ADDR_SHIFT)); + regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, + (addr << TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT)); - regmap_write(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_DATA, val); + regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA, val); - regmap_read(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, ®); - reg |= TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_ADDR_INIT_EN; + regmap_read(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, ®); + reg |= TEGRA210_AMX_CFG_CTRL_ADDR_INIT_EN; - regmap_write(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, reg); + regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, reg); - regmap_read(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, ®); - reg |= TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RW_WRITE; + regmap_read(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, ®); + reg |= TEGRA210_AMX_CFG_CTRL_RW_WRITE; - regmap_write(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, reg); + regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, reg); } static void tegra210_amx_update_map_ram(struct tegra210_amx *amx) @@ -216,23 +216,23 @@ static unsigned int __maybe_unused unsigned int val; int err; - regmap_write(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, - (addr << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RAM_ADDR_SHIFT)); + regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, + (addr << TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT)); - regmap_read(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, &val); - val |= TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_ADDR_INIT_EN; - regmap_write(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, val); - regmap_read(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, &val); - val &= ~(TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RW_WRITE); - regmap_write(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, val); + regmap_read(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, &val); + val |= TEGRA210_AMX_CFG_CTRL_ADDR_INIT_EN; + regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, val); + regmap_read(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, &val); + val &= ~(TEGRA210_AMX_CFG_CTRL_RW_WRITE); + regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, val); err = regmap_read_poll_timeout(amx->regmap, - TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, + TEGRA210_AMX_CFG_RAM_CTRL, val, !(val & 0x80000000), 10, 10000); if (err < 0) return err; - regmap_read(amx->regmap, TEGRA210_AMX_AHUBRAMCTL_AMX_DATA, &val); + regmap_read(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA, &val); return val; } @@ -321,14 +321,14 @@ static int tegra210_amx_in_hw_params(struct snd_pcm_substream *substream, */ if (amx->soc_data->is_auto_disable_supported) { regmap_write(amx->regmap, - TEGRA194_AMX_RX1_CTRL_FRAME_PERIOD + + TEGRA194_AMX_RX1_FRAME_PERIOD + (dai->id * TEGRA210_AMX_AUDIOCIF_CH_STRIDE), 0x1800); regmap_write(amx->regmap, TEGRA210_AMX_CYA, 1); } err = tegra210_amx_set_audio_cif(dai, params, - TEGRA210_AMX_AXBAR_RX1_CIF_CTRL + + TEGRA210_AMX_RX1_CIF_CTRL + (dai->id * TEGRA210_AMX_AUDIOCIF_CH_STRIDE)); return err; @@ -363,7 +363,7 @@ static int tegra210_amx_out_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { return tegra210_amx_set_audio_cif(dai, params, - TEGRA210_AMX_AXBAR_TX_CIF_CTRL); + TEGRA210_AMX_TX_CIF_CTRL); } static int tegra210_amx_set_channel_map(struct snd_soc_dai *dai, @@ -678,92 +678,64 @@ static bool tegra210_amx_wr_reg(struct device *dev, unsigned int reg) { switch (reg) { - case TEGRA210_AMX_AXBAR_RX_INT_MASK: - case TEGRA210_AMX_AXBAR_RX_INT_SET: - case TEGRA210_AMX_AXBAR_RX_INT_CLEAR: - case TEGRA210_AMX_AXBAR_RX1_CIF_CTRL: - case TEGRA210_AMX_AXBAR_RX2_CIF_CTRL: - case TEGRA210_AMX_AXBAR_RX3_CIF_CTRL: - case TEGRA210_AMX_AXBAR_RX4_CIF_CTRL: - case TEGRA210_AMX_AXBAR_TX_INT_MASK: - case TEGRA210_AMX_AXBAR_TX_INT_SET: - case TEGRA210_AMX_AXBAR_TX_INT_CLEAR: - case TEGRA210_AMX_AXBAR_TX_CIF_CTRL: - case TEGRA210_AMX_ENABLE: - case TEGRA210_AMX_SOFT_RESET: - case TEGRA210_AMX_CG: - case TEGRA210_AMX_CTRL: - case TEGRA210_AMX_OUT_BYTE_EN0: - case TEGRA210_AMX_OUT_BYTE_EN1: - case TEGRA210_AMX_CYA: - case TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL: - case TEGRA210_AMX_AHUBRAMCTL_AMX_DATA: - case TEGRA194_AMX_RX1_CTRL_FRAME_PERIOD: - case TEGRA194_AMX_RX2_CTRL_FRAME_PERIOD: - case TEGRA194_AMX_RX3_CTRL_FRAME_PERIOD: - case TEGRA194_AMX_RX4_CTRL_FRAME_PERIOD: + case TEGRA210_AMX_RX_INT_MASK ... TEGRA210_AMX_RX4_CIF_CTRL: + case TEGRA210_AMX_TX_INT_MASK ... TEGRA210_AMX_CG: + case TEGRA210_AMX_CTRL ... TEGRA210_AMX_CYA: + case TEGRA210_AMX_CFG_RAM_CTRL ... TEGRA210_AMX_CFG_RAM_DATA: return true; default: return false; } } +static bool tegra194_amx_wr_reg(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD: + return true; + default: + return tegra210_amx_wr_reg(dev, reg); + } +} + static bool tegra210_amx_rd_reg(struct device *dev, unsigned int reg) { switch (reg) { - case TEGRA210_AMX_AXBAR_RX_STATUS: - case TEGRA210_AMX_AXBAR_RX_INT_STATUS: - case TEGRA210_AMX_AXBAR_RX_INT_MASK: - case TEGRA210_AMX_AXBAR_RX_INT_SET: - case TEGRA210_AMX_AXBAR_RX_INT_CLEAR: - case TEGRA210_AMX_AXBAR_RX1_CIF_CTRL: - case TEGRA210_AMX_AXBAR_RX2_CIF_CTRL: - case TEGRA210_AMX_AXBAR_RX3_CIF_CTRL: - case TEGRA210_AMX_AXBAR_RX4_CIF_CTRL: - case TEGRA210_AMX_AXBAR_TX_STATUS: - case TEGRA210_AMX_AXBAR_TX_INT_STATUS: - case TEGRA210_AMX_AXBAR_TX_INT_MASK: - case TEGRA210_AMX_AXBAR_TX_INT_SET: - case TEGRA210_AMX_AXBAR_TX_INT_CLEAR: - case TEGRA210_AMX_AXBAR_TX_CIF_CTRL: - case TEGRA210_AMX_ENABLE: - case TEGRA210_AMX_SOFT_RESET: - case TEGRA210_AMX_CG: - case TEGRA210_AMX_STATUS: - case TEGRA210_AMX_INT_STATUS: - case TEGRA210_AMX_CTRL: - case TEGRA210_AMX_OUT_BYTE_EN0: - case TEGRA210_AMX_OUT_BYTE_EN1: - case TEGRA210_AMX_CYA: - case TEGRA210_AMX_DBG: - case TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL: - case TEGRA210_AMX_AHUBRAMCTL_AMX_DATA: - case TEGRA194_AMX_RX1_CTRL_FRAME_PERIOD: - case TEGRA194_AMX_RX2_CTRL_FRAME_PERIOD: - case TEGRA194_AMX_RX3_CTRL_FRAME_PERIOD: - case TEGRA194_AMX_RX4_CTRL_FRAME_PERIOD: + case TEGRA210_AMX_RX_STATUS ... TEGRA210_AMX_CFG_RAM_DATA: return true; default: return false; } } +static bool tegra194_amx_rd_reg(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD: + return true; + default: + return tegra210_amx_rd_reg(dev, reg); + } +} + static bool tegra210_amx_volatile_reg(struct device *dev, unsigned int reg) { switch (reg) { - case TEGRA210_AMX_AXBAR_RX_STATUS: - case TEGRA210_AMX_AXBAR_RX_INT_STATUS: - case TEGRA210_AMX_AXBAR_RX_INT_SET: - case TEGRA210_AMX_AXBAR_TX_STATUS: - case TEGRA210_AMX_AXBAR_TX_INT_STATUS: - case TEGRA210_AMX_AXBAR_TX_INT_SET: + case TEGRA210_AMX_RX_STATUS: + case TEGRA210_AMX_RX_INT_STATUS: + case TEGRA210_AMX_RX_INT_SET: + case TEGRA210_AMX_TX_STATUS: + case TEGRA210_AMX_TX_INT_STATUS: + case TEGRA210_AMX_TX_INT_SET: case TEGRA210_AMX_SOFT_RESET: case TEGRA210_AMX_STATUS: case TEGRA210_AMX_INT_STATUS: - case TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL: - case TEGRA210_AMX_AHUBRAMCTL_AMX_DATA: + case TEGRA210_AMX_CFG_RAM_CTRL: + case TEGRA210_AMX_CFG_RAM_DATA: return true; default: break; @@ -776,7 +748,7 @@ static const struct regmap_config tegra210_amx_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .max_register = TEGRA210_AMX_AHUBRAMCTL_AMX_DATA, + .max_register = TEGRA210_AMX_CFG_RAM_DATA, .writeable_reg = tegra210_amx_wr_reg, .readable_reg = tegra210_amx_rd_reg, .volatile_reg = tegra210_amx_volatile_reg, @@ -790,8 +762,8 @@ static const struct regmap_config tegra194_amx_regmap_config = { .reg_stride = 4, .val_bits = 32, .max_register = TEGRA194_AMX_RX4_LAST_FRAME_PERIOD, - .writeable_reg = tegra210_amx_wr_reg, - .readable_reg = tegra210_amx_rd_reg, + .writeable_reg = tegra194_amx_wr_reg, + .readable_reg = tegra194_amx_rd_reg, .volatile_reg = tegra210_amx_volatile_reg, .reg_defaults = tegra210_amx_reg_defaults, .num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults), diff --git a/sound/soc/tegra/tegra210_amx.h b/sound/soc/tegra/tegra210_amx.h index ed78c1b3..4c49e725 100644 --- a/sound/soc/tegra/tegra210_amx.h +++ b/sound/soc/tegra/tegra210_amx.h @@ -12,157 +12,88 @@ #define TEGRA210_AMX_AUDIOCIF_CH_STRIDE 4 /* Register offsets from TEGRA210_AMX*_BASE */ -#define TEGRA210_AMX_AXBAR_RX_STATUS 0x0c -#define TEGRA210_AMX_AXBAR_RX_INT_STATUS 0x10 -#define TEGRA210_AMX_AXBAR_RX_INT_MASK 0x14 -#define TEGRA210_AMX_AXBAR_RX_INT_SET 0x18 -#define TEGRA210_AMX_AXBAR_RX_INT_CLEAR 0x1c -#define TEGRA210_AMX_AXBAR_RX1_CIF_CTRL 0x20 -#define TEGRA210_AMX_AXBAR_RX2_CIF_CTRL 0x24 -#define TEGRA210_AMX_AXBAR_RX3_CIF_CTRL 0x28 -#define TEGRA210_AMX_AXBAR_RX4_CIF_CTRL 0x2c -#define TEGRA210_AMX_AXBAR_TX_STATUS 0x4c -#define TEGRA210_AMX_AXBAR_TX_INT_STATUS 0x50 -#define TEGRA210_AMX_AXBAR_TX_INT_MASK 0x54 -#define TEGRA210_AMX_AXBAR_TX_INT_SET 0x58 -#define TEGRA210_AMX_AXBAR_TX_INT_CLEAR 0x5c -#define TEGRA210_AMX_AXBAR_TX_CIF_CTRL 0x60 -#define TEGRA210_AMX_ENABLE 0x80 -#define TEGRA210_AMX_SOFT_RESET 0x84 -#define TEGRA210_AMX_CG 0x88 -#define TEGRA210_AMX_STATUS 0x8c -#define TEGRA210_AMX_INT_STATUS 0x90 -#define TEGRA210_AMX_CTRL 0xa4 -#define TEGRA210_AMX_OUT_BYTE_EN0 0xa8 -#define TEGRA210_AMX_OUT_BYTE_EN1 0xac -#define TEGRA210_AMX_CYA 0xb0 -#define TEGRA210_AMX_DBG 0xb4 -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL 0xb8 -#define TEGRA210_AMX_AHUBRAMCTL_AMX_DATA 0xbc -#define TEGRA194_AMX_RX1_CTRL_FRAME_PERIOD 0xc0 -#define TEGRA194_AMX_RX2_CTRL_FRAME_PERIOD 0xc4 -#define TEGRA194_AMX_RX3_CTRL_FRAME_PERIOD 0xc8 -#define TEGRA194_AMX_RX4_CTRL_FRAME_PERIOD 0xcc +#define TEGRA210_AMX_RX_STATUS 0x0c +#define TEGRA210_AMX_RX_INT_STATUS 0x10 +#define TEGRA210_AMX_RX_INT_MASK 0x14 +#define TEGRA210_AMX_RX_INT_SET 0x18 +#define TEGRA210_AMX_RX_INT_CLEAR 0x1c +#define TEGRA210_AMX_RX1_CIF_CTRL 0x20 +#define TEGRA210_AMX_RX2_CIF_CTRL 0x24 +#define TEGRA210_AMX_RX3_CIF_CTRL 0x28 +#define TEGRA210_AMX_RX4_CIF_CTRL 0x2c +#define TEGRA210_AMX_TX_STATUS 0x4c +#define TEGRA210_AMX_TX_INT_STATUS 0x50 +#define TEGRA210_AMX_TX_INT_MASK 0x54 +#define TEGRA210_AMX_TX_INT_SET 0x58 +#define TEGRA210_AMX_TX_INT_CLEAR 0x5c +#define TEGRA210_AMX_TX_CIF_CTRL 0x60 +#define TEGRA210_AMX_ENABLE 0x80 +#define TEGRA210_AMX_SOFT_RESET 0x84 +#define TEGRA210_AMX_CG 0x88 +#define TEGRA210_AMX_STATUS 0x8c +#define TEGRA210_AMX_INT_STATUS 0x90 +#define TEGRA210_AMX_CTRL 0xa4 +#define TEGRA210_AMX_OUT_BYTE_EN0 0xa8 +#define TEGRA210_AMX_OUT_BYTE_EN1 0xac +#define TEGRA210_AMX_CYA 0xb0 +#define TEGRA210_AMX_DBG 0xb4 +#define TEGRA210_AMX_CFG_RAM_CTRL 0xb8 +#define TEGRA210_AMX_CFG_RAM_DATA 0xbc + +#define TEGRA194_AMX_RX1_FRAME_PERIOD 0xc0 +#define TEGRA194_AMX_RX2_FRAME_PERIOD 0xc4 +#define TEGRA194_AMX_RX3_FRAME_PERIOD 0xc8 +#define TEGRA194_AMX_RX4_FRAME_PERIOD 0xcc #define TEGRA194_AMX_RX4_LAST_FRAME_PERIOD 0xdc -/* Fields in TEGRA210_AMX_AXBAR_RX1_CIF_CTRL */ -/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_ahub.h */ - -/* Fields in TEGRA210_AMX_AXBAR_RX2_CIF_CTRL */ -/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_ahub.h */ - -/* Fields in TEGRA210_AMX_AXBAR_RX3_CIF_CTRL */ -/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_ahub.h */ - -/* Fields in TEGRA210_AMX_AXBAR_RX4_CIF_CTRL */ -/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_ahub.h */ - -/* Fields in TEGRA210_AMX_AXBAR_TX_CIF_CTRL */ -/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_ahub.h */ - /* Fields in TEGRA210_AMX_ENABLE */ -#define TEGRA210_AMX_ENABLE_SHIFT 0 -#define TEGRA210_AMX_ENABLE_MASK (1 << TEGRA210_AMX_ENABLE_SHIFT) -#define TEGRA210_AMX_EN (1 << TEGRA210_AMX_ENABLE_SHIFT) +#define TEGRA210_AMX_ENABLE_SHIFT 0 /* Fields in TEGRA210_AMX_CTRL */ -#define TEGRA210_AMX_CTRL_MSTR_RX_NUN_SHIFT 14 -#define TEGRA210_AMX_CTRL_MSTR_RX_NUM_MASK (3 << TEGRA210_AMX_CTRL_MSTR_RX_NUN_SHIFT) +#define TEGRA210_AMX_CTRL_MSTR_RX_NUN_SHIFT 14 +#define TEGRA210_AMX_CTRL_MSTR_RX_NUM_MASK (3 << TEGRA210_AMX_CTRL_MSTR_RX_NUN_SHIFT) -#define TEGRA210_AMX_CTRL_RX_DEP_SHIFT 12 -#define TEGRA210_AMX_CTRL_RX_DEP_MASK (3 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT) -#define TEGRA210_AMX_CTRL_RX_DEP_WT_ON_ALL 0 -#define TEGRA210_AMX_CTRL_RX_DEP_WT_ON_ANY (1 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT) -#define TEGRA210_AMX_CTRL_RX_DEP_RSVD (3 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT) +#define TEGRA210_AMX_CTRL_RX_DEP_SHIFT 12 +#define TEGRA210_AMX_CTRL_RX_DEP_MASK (3 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT) +#define TEGRA210_AMX_CTRL_RX_DEP_WT_ON_ALL 0 +#define TEGRA210_AMX_CTRL_RX_DEP_WT_ON_ANY (1 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT) +#define TEGRA210_AMX_CTRL_RX_DEP_RSVD (3 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT) -#define TEGRA210_AMX_CTRL_RX4_FORCE_DISABLE_SHIFT 11 -#define TEGRA210_AMX_CTRL_RX4_FORCE_DISABLE_MASK (1 << TEGRA210_AMX_CTRL_RX4_FORCE_DISABLE_SHIFT) -#define TEGRA210_AMX_CTRL_RX4_FORCE_DISABLE_EN (1 << TEGRA210_AMX_CTRL_RX4_FORCE_DISABLE_SHIFT) +/* Fields in TEGRA210_AMX_CFG_RAM_CTRL */ +#define TEGRA210_AMX_CFG_CTRL_RW_SHIFT 14 +#define TEGRA210_AMX_CFG_CTRL_RW_MASK (1 << TEGRA210_AMX_CFG_CTRL_RW_SHIFT) +#define TEGRA210_AMX_CFG_CTRL_RW_WRITE (1 << TEGRA210_AMX_CFG_CTRL_RW_SHIFT) -#define TEGRA210_AMX_CTRL_RX3_FORCE_DISABLE_SHIFT 10 -#define TEGRA210_AMX_CTRL_RX3_FORCE_DISABLE_MASK (1 << TEGRA210_AMX_CTRL_RX3_FORCE_DISABLE_SHIFT) -#define TEGRA210_AMX_CTRL_RX3_FORCE_DISABLE_EN (1 << TEGRA210_AMX_CTRL_RX3_FORCE_DISABLE_SHIFT) +#define TEGRA210_AMX_CFG_CTRL_ADDR_INIT_EN_SHIFT 13 +#define TEGRA210_AMX_CFG_CTRL_ADDR_INIT_EN_MASK (1 << TEGRA210_AMX_CFG_CTRL_ADDR_INIT_EN_SHIFT) +#define TEGRA210_AMX_CFG_CTRL_ADDR_INIT_EN (1 << TEGRA210_AMX_CFG_CTRL_ADDR_INIT_EN_SHIFT) -#define TEGRA210_AMX_CTRL_RX2_FORCE_DISABLE_SHIFT 9 -#define TEGRA210_AMX_CTRL_RX2_FORCE_DISABLE_MASK (1 << TEGRA210_AMX_CTRL_RX2_FORCE_DISABLE_SHIFT) -#define TEGRA210_AMX_CTRL_RX2_FORCE_DISABLE_EN (1 << TEGRA210_AMX_CTRL_RX2_FORCE_DISABLE_SHIFT) - -#define TEGRA210_AMX_CTRL_RX1_FORCE_DISABLE_SHIFT 8 -#define TEGRA210_AMX_CTRL_RX1_FORCE_DISABLE_MASK (1 << TEGRA210_AMX_CTRL_RX1_FORCE_DISABLE_SHIFT) -#define TEGRA210_AMX_CTRL_RX1_FORCE_DISABLE_EN (1 << TEGRA210_AMX_CTRL_RX1_FORCE_DISABLE_SHIFT) - -#define TEGRA210_AMX_CTRL_RX4_ENABLE_SHIFT 3 -#define TEGRA210_AMX_CTRL_RX4_ENABLE_MASK (1 << TEGRA210_AMX_CTRL_RX4_ENABLE_SHIFT) -#define TEGRA210_AMX_CTRL_RX4_EN (1 << TEGRA210_AMX_CTRL_RX4_ENABLE_SHIFT) - -#define TEGRA210_AMX_CTRL_RX3_ENABLE_SHIFT 2 -#define TEGRA210_AMX_CTRL_RX3_ENABLE_MASK (1 << TEGRA210_AMX_CTRL_RX3_ENABLE_SHIFT) -#define TEGRA210_AMX_CTRL_RX3_EN (1 << TEGRA210_AMX_CTRL_RX3_ENABLE_SHIFT) - -#define TEGRA210_AMX_CTRL_RX2_ENABLE_SHIFT 1 -#define TEGRA210_AMX_CTRL_RX2_ENABLE_MASK (1 << TEGRA210_AMX_CTRL_RX2_ENABLE_SHIFT) -#define TEGRA210_AMX_CTRL_RX2_EN (1 << TEGRA210_AMX_CTRL_RX2_ENABLE_SHIFT) - -#define TEGRA210_AMX_CTRL_RX1_ENABLE_SHIFT 0 -#define TEGRA210_AMX_CTRL_RX1_ENABLE_MASK (1 << TEGRA210_AMX_CTRL_RX1_ENABLE_SHIFT) -#define TEGRA210_AMX_CTRL_RX1_EN (1 << TEGRA210_AMX_CTRL_RX1_ENABLE_SHIFT) - -/* Fields in TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL */ -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_READ_BUSY_SHIFT 31 -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_READ_BUSY_MASK (1 << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_READ_BUSY_SHIFT) -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_READ_BUSY (1 << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_READ_BUSY_SHIFT) - -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RW_SHIFT 14 -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RW_MASK (1 << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RW_SHIFT) -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RW_WRITE (1 << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RW_SHIFT) - -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_ADDR_INIT_EN_SHIFT 13 -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_ADDR_INIT_EN_MASK (1 << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_ADDR_INIT_EN_SHIFT) -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_ADDR_INIT_EN (1 << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_ADDR_INIT_EN_SHIFT) - -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RAM_ADDR_SHIFT 0 -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RAM_ADDR_MASK (0xff << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_RAM_ADDR_SHIFT) - -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_SEQ_ACCESS_EN_SHIFT 12 -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_SEQ_ACCESS_EN_MASK (1 << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_SEQ_ACCESS_EN_SHIFT) -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_SEQ_ACCESS_EN_SHIFT) - -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_SEQ_READ_COUNT_SHIFT 16 -#define TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_SEQ_READ_COUNT_MASK (0xff << TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL_SEQ_READ_COUNT_SHIFT) +#define TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT 0 +#define TEGRA210_AMX_CFG_CTRL_RAM_ADDR_MASK (0xff << TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT) /* Fields in TEGRA210_AMX_SOFT_RESET */ -#define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_SHIFT 0 -#define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_AMX_SOFT_RESET_SOFT_RESET_SHIFT) +#define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_SHIFT 0 +#define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_AMX_SOFT_RESET_SOFT_RESET_SHIFT) #define TEGRA210_AMX_SOFT_RESET_SOFT_EN (1 << TEGRA210_AMX_SOFT_RESET_SOFT_RESET_SHIFT) -#define TEGRA210_AMX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_AMX_SOFT_RESET_SOFT_RESET_SHIFT) +#define TEGRA210_AMX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_AMX_SOFT_RESET_SOFT_RESET_SHIFT) /* * Those defines are not in register field. */ -#define TEGRA210_AMX_NUM_INPUTS 4 -#define TEGRA210_AMX_RAM_DEPTH 16 +#define TEGRA210_AMX_NUM_INPUTS 4 +#define TEGRA210_AMX_RAM_DEPTH 16 #define TEGRA210_AMX_MAP_STREAM_NUMBER_SHIFT 6 -#define TEGRA210_AMX_MAP_STREAM_NUMBER_MASK (0x3 << TEGRA210_AMX_MAP_STREAM_NUMBER_SHIFT) -#define TEGRA210_AMX_MAP_WORD_NUMBER_SHIFT 2 -#define TEGRA210_AMX_MAP_WORD_NUMBER_MASK (0xF << TEGRA210_AMX_MAP_WORD_NUMBER_SHIFT) -#define TEGRA210_AMX_MAP_BYTE_NUMBER_SHIFT 0 -#define TEGRA210_AMX_MAP_BYTE_NUMBER_MASK (0x3 << TEGRA210_AMX_MAP_BYTE_NUMBER_SHIFT) +#define TEGRA210_AMX_MAP_STREAM_NUMBER_MASK (0x3 << TEGRA210_AMX_MAP_STREAM_NUMBER_SHIFT) +#define TEGRA210_AMX_MAP_WORD_NUMBER_SHIFT 2 +#define TEGRA210_AMX_MAP_WORD_NUMBER_MASK (0xF << TEGRA210_AMX_MAP_WORD_NUMBER_SHIFT) +#define TEGRA210_AMX_MAP_BYTE_NUMBER_SHIFT 0 +#define TEGRA210_AMX_MAP_BYTE_NUMBER_MASK (0x3 << TEGRA210_AMX_MAP_BYTE_NUMBER_SHIFT) enum { TEGRA210_AMX_WAIT_ON_ALL, TEGRA210_AMX_WAIT_ON_ANY, }; -enum { - /* Code assumes that IN_STREAM values of AMX start at 0 */ - TEGRA210_AMX_IN_STREAM0 = 0, - TEGRA210_AMX_IN_STREAM1, - TEGRA210_AMX_IN_STREAM2, - TEGRA210_AMX_IN_STREAM3, - TEGRA210_AMX_OUT_STREAM, - TEGRA210_AMX_TOTAL_STREAM -}; - enum { TEGRA210_AMX_RX_DISABLE, TEGRA210_AMX_RX_ENABLE,