From 44419231b08413a47af26762f8113ef0a19e93ab Mon Sep 17 00:00:00 2001 From: Mahesh Patil Date: Wed, 9 Nov 2022 12:26:34 -0800 Subject: [PATCH] nvethernet: eqos pad calibration reg offsets Make eqos pad calibration reg ETHER_QOS_AUTO_CAL_CONFIG_0 offsets AUTO_CAL_PD_OFFSET and AUTO_CAL_PU_OFFSET configurable as per customer boards tuning Bug 3846183 Bug 4088361 Change-Id: I77521f83cac56650c6a6d1a2dd8b8c7cbdc3f3fc Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2806180 (cherry picked from commit 8eea133d313ba3b1b4ced9f58a65ecf870a2b0e6) Signed-off-by: Mahesh Patil Signed-off-by: Revanth Kumar Uppala Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2897231 Tested-by: mobile promotions Reviewed-by: mobile promotions --- .../ethernet/nvidia/nvethernet/ether_linux.c | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c index ab891be0..799988c0 100644 --- a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c +++ b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c @@ -5558,6 +5558,8 @@ static int ether_parse_dt(struct ether_priv_data *pdata) int ret = -EINVAL; unsigned int i, mtlq, chan, bitmap; unsigned int dt_pad_calibration_enable; + unsigned int dt_pad_auto_cal_pu_offset; + unsigned int dt_pad_auto_cal_pd_offset; /* This variable is for DT entry which should not fail bootup */ int ret_val = 0; @@ -6004,6 +6006,44 @@ static int ether_parse_dt(struct ether_priv_data *pdata) osi_core->padctrl.pad_calibration_enable = dt_pad_calibration_enable; } + /* Read pad calibration config reg offset, default 0 */ + ret = of_property_read_u32(np, "nvidia,pad_auto_cal_pu_offset", + &dt_pad_auto_cal_pu_offset); + if (ret < 0) { + dev_info(dev, "missing nvidia,pad_auto_cal_pu_offset, " + "setting default 0\n"); + osi_core->padctrl.pad_auto_cal_pu_offset = 0U; + ret = 0; + } else if (dt_pad_auto_cal_pu_offset > + OSI_PAD_CAL_CONFIG_PD_PU_OFFSET_MAX) { + dev_err(dev, "Error: Invalid dt " + "pad_auto_cal_pu_offset: %u value\n", + dt_pad_auto_cal_pu_offset); + ret = -EINVAL; + goto exit; + } else { + osi_core->padctrl.pad_auto_cal_pu_offset = + dt_pad_auto_cal_pu_offset; + } + ret = of_property_read_u32(np, "nvidia,pad_auto_cal_pd_offset", + &dt_pad_auto_cal_pd_offset); + if (ret < 0) { + dev_info(dev, "missing nvidia,pad_auto_cal_pd_offset, " + "setting default 0\n"); + osi_core->padctrl.pad_auto_cal_pd_offset = 0U; + ret = 0; + } else if (dt_pad_auto_cal_pd_offset > + OSI_PAD_CAL_CONFIG_PD_PU_OFFSET_MAX) { + dev_err(dev, "Error: Invalid dt " + "pad_auto_cal_pu_offset: %u value\n", + dt_pad_auto_cal_pd_offset); + ret = -EINVAL; + goto exit; + } else { + osi_core->padctrl.pad_auto_cal_pd_offset = + dt_pad_auto_cal_pd_offset; + } + pdata->pin = devm_pinctrl_get(dev); if (IS_ERR(pdata->pin)) { dev_err(dev, "DT: missing eqos pinctrl device\n");