diff --git a/sound/soc/tegra/tegra186_dspk.c b/sound/soc/tegra/tegra186_dspk.c index 0cbe31e2..bc93ad2f 100644 --- a/sound/soc/tegra/tegra186_dspk.c +++ b/sound/soc/tegra/tegra186_dspk.c @@ -1,8 +1,17 @@ // SPDX-License-Identifier: GPL-2.0-only +<<<<<<< HEAD +/* + * tegra186_dspk.c - Tegra186 DSPK driver + * + * Copyright (c) 2015-2020 NVIDIA CORPORATION. All rights reserved. + * + */ +======= // // tegra186_dspk.c - Tegra186 DSPK driver // // Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. +>>>>>>> v5.9-rc4 #include #include @@ -38,8 +47,19 @@ static int tegra186_dspk_get_control(struct snd_kcontrol *kcontrol, ucontrol->value.integer.value[0] = dspk->osr_val; else if (strstr(kcontrol->id.name, "LR Polarity Select")) ucontrol->value.integer.value[0] = dspk->lrsel; +<<<<<<< HEAD + else if (strstr(kcontrol->id.name, "Sample Rate")) + ucontrol->value.integer.value[0] = dspk->srate_override; + else if (strstr(kcontrol->id.name, "Audio Channels")) + ucontrol->value.integer.value[0] = dspk->audio_ch_override; else if (strstr(kcontrol->id.name, "Channel Select")) ucontrol->value.integer.value[0] = dspk->ch_sel; + else if (strstr(kcontrol->id.name, "Audio Bit Format")) + ucontrol->value.integer.value[0] = dspk->audio_fmt_override; +======= + else if (strstr(kcontrol->id.name, "Channel Select")) + ucontrol->value.integer.value[0] = dspk->ch_sel; +>>>>>>> v5.9-rc4 else if (strstr(kcontrol->id.name, "Mono To Stereo")) ucontrol->value.integer.value[0] = dspk->mono_to_stereo; else if (strstr(kcontrol->id.name, "Stereo To Mono")) @@ -61,8 +81,19 @@ static int tegra186_dspk_put_control(struct snd_kcontrol *kcontrol, dspk->osr_val = val; else if (strstr(kcontrol->id.name, "LR Polarity Select")) dspk->lrsel = val; +<<<<<<< HEAD + else if (strstr(kcontrol->id.name, "Sample Rate")) + dspk->srate_override = val; + else if (strstr(kcontrol->id.name, "Audio Channels")) + dspk->audio_ch_override = val; else if (strstr(kcontrol->id.name, "Channel Select")) dspk->ch_sel = val; + else if (strstr(kcontrol->id.name, "Audio Bit Format")) + dspk->audio_fmt_override = val; +======= + else if (strstr(kcontrol->id.name, "Channel Select")) + dspk->ch_sel = val; +>>>>>>> v5.9-rc4 else if (strstr(kcontrol->id.name, "Mono To Stereo")) dspk->mono_to_stereo = val; else if (strstr(kcontrol->id.name, "Stereo To Mono")) @@ -71,7 +102,11 @@ static int tegra186_dspk_put_control(struct snd_kcontrol *kcontrol, return 0; } +<<<<<<< HEAD +static int tegra186_dspk_runtime_suspend(struct device *dev) +======= static int __maybe_unused tegra186_dspk_runtime_suspend(struct device *dev) +>>>>>>> v5.9-rc4 { struct tegra186_dspk *dspk = dev_get_drvdata(dev); @@ -83,7 +118,11 @@ static int __maybe_unused tegra186_dspk_runtime_suspend(struct device *dev) return 0; } +<<<<<<< HEAD +static int tegra186_dspk_runtime_resume(struct device *dev) +======= static int __maybe_unused tegra186_dspk_runtime_resume(struct device *dev) +>>>>>>> v5.9-rc4 { struct tegra186_dspk *dspk = dev_get_drvdata(dev); int err; @@ -100,6 +139,15 @@ static int __maybe_unused tegra186_dspk_runtime_resume(struct device *dev) return 0; } +<<<<<<< HEAD +static const unsigned int tegra186_dspk_fmts[] = { + 0, + TEGRA_ACIF_BITS_16, + TEGRA_ACIF_BITS_32, +}; + +======= +>>>>>>> v5.9-rc4 static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -116,6 +164,13 @@ static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream, channels = params_channels(params); cif_conf.audio_ch = channels; +<<<<<<< HEAD + /* Override audio channel */ + if (dspk->audio_ch_override) + cif_conf.audio_ch = dspk->audio_ch_override; + +======= +>>>>>>> v5.9-rc4 /* Client channel */ switch (dspk->ch_sel) { case DSPK_CH_SELECT_LEFT: @@ -135,16 +190,35 @@ static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream, switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: cif_conf.audio_bits = TEGRA_ACIF_BITS_16; +<<<<<<< HEAD + cif_conf.client_bits = TEGRA_ACIF_BITS_16; +======= +>>>>>>> v5.9-rc4 break; case SNDRV_PCM_FORMAT_S32_LE: cif_conf.audio_bits = TEGRA_ACIF_BITS_32; break; default: dev_err(dev, "unsupported format!\n"); +<<<<<<< HEAD + return -ENOTSUPP; + } + + /* Audio bit format override */ + if (dspk->audio_fmt_override) + cif_conf.audio_bits = + tegra186_dspk_fmts[dspk->audio_fmt_override]; + + srate = params_rate(params); + /* Sample rate override */ + if (dspk->srate_override) + srate = dspk->srate_override; +======= return -EOPNOTSUPP; } srate = params_rate(params); +>>>>>>> v5.9-rc4 /* RX FIFO threshold in terms of frames */ max_th = (TEGRA186_DSPK_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1; @@ -194,11 +268,22 @@ static const struct snd_soc_dai_ops tegra186_dspk_dai_ops = { .hw_params = tegra186_dspk_hw_params, }; +<<<<<<< HEAD +/* + * Three DAIs are exposed + * 1. "CIF" DAI for connecting with XBAR + * 2. "DAP" DAI for connecting with CODEC + * 3. "DUMMY_SINK" can be used when no external + * codec connection is available. In such case + * "DAP" is connected with "DUMMY_SINK" + * Order of these DAIs should not be changed, since DAI links in DT refer + * to these DAIs depending on the index. + */ static struct snd_soc_dai_driver tegra186_dspk_dais[] = { { - .name = "DSPK-CIF", + .name = "CIF", .playback = { - .stream_name = "CIF-Playback", + .stream_name = "CIF Receive", .channels_min = 1, .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_48000, @@ -207,15 +292,99 @@ static struct snd_soc_dai_driver tegra186_dspk_dais[] = { }, }, { - .name = "DSPK-DAP", + .name = "DAP", + .capture = { + .stream_name = "DAP Transmit", +======= +static struct snd_soc_dai_driver tegra186_dspk_dais[] = { + { + .name = "DSPK-CIF", .playback = { - .stream_name = "DAP-Playback", + .stream_name = "CIF-Playback", +>>>>>>> v5.9-rc4 .channels_min = 1, .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_48000, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, }, +<<<<<<< HEAD + .ops = &tegra186_dspk_dai_ops, + .symmetric_rates = 1, + }, + /* The second DAI is used when the output of the DSPK is connected + * to two mono codecs. When the output of the DSPK is connected to + * a single stereo codec, then only the first DAI should be used. + */ + { + .name = "CIF2", + .playback = { + .stream_name = "CIF2 Receive", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + }, + { + .name = "DAP2", + .capture = { + .stream_name = "DAP2 Transmit", +======= + }, + { + .name = "DSPK-DAP", + .playback = { + .stream_name = "DAP-Playback", +>>>>>>> v5.9-rc4 + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, +<<<<<<< HEAD + .symmetric_rates = 1, + }, + { + .name = "DUMMY_SINK", + .playback = { + .stream_name = "Dummy Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + }, +}; + +static const struct snd_soc_dapm_widget tegra186_dspk_widgets[] = { + SND_SOC_DAPM_AIF_OUT("DAP TX", NULL, 0, TEGRA186_DSPK_ENABLE, 0, 0), + SND_SOC_DAPM_AIF_OUT("DAP2 TX", NULL, 0, 0, 0, 0), + SND_SOC_DAPM_SPK("Dummy Output", NULL), +}; + +static const struct snd_soc_dapm_route tegra186_dspk_routes[] = { + { "DAP TX", NULL, "CIF Receive" }, + { "DAP Transmit", NULL, "DAP TX" }, + { "DAP2 TX", NULL, "CIF2 Receive" }, + { "DAP2 Transmit", NULL, "DAP2 TX" }, + { "Dummy Output", NULL, "Dummy Playback" }, +}; + +static const char * const tegra186_dspk_format_text[] = { + "None", + "16", + "32", +}; + +static const struct soc_enum tegra186_dspk_format_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_format_text), + tegra186_dspk_format_text); + +======= .ops = &tegra186_dspk_dai_ops, .symmetric_rates = 1, }, @@ -234,6 +403,7 @@ static const struct snd_soc_dapm_route tegra186_dspk_routes[] = { { "SPK", NULL, "DAP-Playback" }, }; +>>>>>>> v5.9-rc4 static const char * const tegra186_dspk_ch_sel_text[] = { "Left", "Right", "Stereo", }; @@ -255,7 +425,11 @@ static const char * const tegra186_dspk_lrsel_text[] = { }; static const char * const tegra186_dspk_mono_conv_text[] = { +<<<<<<< HEAD + "ZERO", "COPY", +======= "Zero", "Copy", +>>>>>>> v5.9-rc4 }; static const struct soc_enum tegra186_dspk_mono_conv_enum = @@ -284,8 +458,19 @@ static const struct snd_kcontrol_new tegrat186_dspk_controls[] = { tegra186_dspk_get_control, tegra186_dspk_put_control), SOC_ENUM_EXT("LR Polarity Select", tegra186_dspk_lrsel_enum, tegra186_dspk_get_control, tegra186_dspk_put_control), +<<<<<<< HEAD + SOC_SINGLE_EXT("Sample Rate", SND_SOC_NOPM, 0, 48000, 0, + tegra186_dspk_get_control, tegra186_dspk_put_control), + SOC_SINGLE_EXT("Audio Channels", SND_SOC_NOPM, 0, 2, 0, + tegra186_dspk_get_control, tegra186_dspk_put_control), SOC_ENUM_EXT("Channel Select", tegra186_dspk_ch_sel_enum, tegra186_dspk_get_control, tegra186_dspk_put_control), + SOC_ENUM_EXT("Audio Bit Format", tegra186_dspk_format_enum, + tegra186_dspk_get_control, tegra186_dspk_put_control), +======= + SOC_ENUM_EXT("Channel Select", tegra186_dspk_ch_sel_enum, + tegra186_dspk_get_control, tegra186_dspk_put_control), +>>>>>>> v5.9-rc4 SOC_ENUM_EXT("Mono To Stereo", tegra186_dspk_mono_conv_enum, tegra186_dspk_get_control, tegra186_dspk_put_control), SOC_ENUM_EXT("Stereo To Mono", tegra186_dspk_stereo_conv_enum, @@ -375,7 +560,11 @@ static int tegra186_dspk_platform_probe(struct platform_device *pdev) dspk->osr_val = DSPK_OSR_64; dspk->lrsel = DSPK_LRSEL_LEFT; dspk->ch_sel = DSPK_CH_SELECT_STEREO; +<<<<<<< HEAD + dspk->mono_to_stereo = 0; /* "ZERO" */ +======= dspk->mono_to_stereo = 0; /* "Zero" */ +>>>>>>> v5.9-rc4 dev_set_drvdata(dev, dspk); diff --git a/sound/soc/tegra/tegra186_dspk.h b/sound/soc/tegra/tegra186_dspk.h index b2a87906..62e21275 100644 --- a/sound/soc/tegra/tegra186_dspk.h +++ b/sound/soc/tegra/tegra186_dspk.h @@ -2,7 +2,11 @@ /* * tegra186_dspk.h - Definitions for Tegra186 DSPK driver * +<<<<<<< HEAD + * Copyright (c) 2015-2020 NVIDIA CORPORATION. All rights reserved. +======= * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. +>>>>>>> v5.9-rc4 * */ @@ -60,7 +64,14 @@ struct tegra186_dspk { unsigned int rx_fifo_th; unsigned int osr_val; unsigned int lrsel; +<<<<<<< HEAD + unsigned int srate_override; + unsigned int audio_ch_override; + unsigned int ch_sel; /* Used for client channel override */ + unsigned int audio_fmt_override; +======= unsigned int ch_sel; +>>>>>>> v5.9-rc4 unsigned int mono_to_stereo; unsigned int stereo_to_mono; struct clk *clk_dspk; diff --git a/sound/soc/tegra/tegra210_admaif.c b/sound/soc/tegra/tegra210_admaif.c index 8ae4649c..2976a30c 100644 --- a/sound/soc/tegra/tegra210_admaif.c +++ b/sound/soc/tegra/tegra210_admaif.c @@ -1,10 +1,17 @@ // SPDX-License-Identifier: GPL-2.0-only +<<<<<<< HEAD /* * tegra210_admaif.c - Tegra ADMAIF driver * * Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved. * */ +======= +// +// tegra210_admaif.c - Tegra ADMAIF driver +// +// Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. +>>>>>>> v5.9-rc4 #include #include @@ -17,7 +24,10 @@ #include #include "tegra210_admaif.h" #include "tegra_cif.h" +<<<<<<< HEAD #include "tegra_isomgr_bw.h" +======= +>>>>>>> v5.9-rc4 #include "tegra_pcm.h" #define CH_REG(offset, reg, id) \ @@ -222,7 +232,11 @@ static const struct regmap_config tegra186_admaif_regmap_config = { .cache_type = REGCACHE_FLAT, }; +<<<<<<< HEAD static int tegra_admaif_runtime_suspend(struct device *dev) +======= +static int __maybe_unused tegra_admaif_runtime_suspend(struct device *dev) +>>>>>>> v5.9-rc4 { struct tegra_admaif *admaif = dev_get_drvdata(dev); @@ -232,7 +246,11 @@ static int tegra_admaif_runtime_suspend(struct device *dev) return 0; } +<<<<<<< HEAD static int tegra_admaif_runtime_resume(struct device *dev) +======= +static int __maybe_unused tegra_admaif_runtime_resume(struct device *dev) +>>>>>>> v5.9-rc4 { struct tegra_admaif *admaif = dev_get_drvdata(dev); @@ -265,6 +283,7 @@ static int tegra_admaif_set_pack_mode(struct regmap *map, unsigned int reg, return 0; } +<<<<<<< HEAD static int tegra_admaif_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { @@ -285,6 +304,8 @@ static void tegra_admaif_shutdown(struct snd_pcm_substream *substream, tegra_isomgr_adma_setbw(substream, false); } +======= +>>>>>>> v5.9-rc4 static int tegra_admaif_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -308,11 +329,14 @@ static int tegra_admaif_hw_params(struct snd_pcm_substream *substream, cif_conf.client_bits = TEGRA_ACIF_BITS_16; valid_bit = DATA_16BIT; break; +<<<<<<< HEAD case SNDRV_PCM_FORMAT_S24_LE: cif_conf.audio_bits = TEGRA_ACIF_BITS_24; cif_conf.client_bits = TEGRA_ACIF_BITS_24; valid_bit = DATA_32BIT; break; +======= +>>>>>>> v5.9-rc4 case SNDRV_PCM_FORMAT_S32_LE: cif_conf.audio_bits = TEGRA_ACIF_BITS_32; cif_conf.client_bits = TEGRA_ACIF_BITS_32; @@ -320,7 +344,11 @@ static int tegra_admaif_hw_params(struct snd_pcm_substream *substream, break; default: dev_err(dev, "unsupported format!\n"); +<<<<<<< HEAD return -ENOTSUPP; +======= + return -EOPNOTSUPP; +>>>>>>> v5.9-rc4 } channels = params_channels(params); @@ -335,12 +363,15 @@ static int tegra_admaif_hw_params(struct snd_pcm_substream *substream, reg = CH_RX_REG(TEGRA_ADMAIF_CH_ACIF_RX_CTRL, dai->id); } +<<<<<<< HEAD if (admaif->audio_ch_override[path][dai->id]) cif_conf.audio_ch = admaif->audio_ch_override[path][dai->id]; if (admaif->client_ch_override[path][dai->id]) cif_conf.client_ch = admaif->client_ch_override[path][dai->id]; +======= +>>>>>>> v5.9-rc4 cif_conf.mono_conv = admaif->mono_to_stereo[path][dai->id]; cif_conf.stereo_conv = admaif->stereo_to_mono[path][dai->id]; @@ -456,6 +487,7 @@ static int tegra_admaif_trigger(struct snd_pcm_substream *substream, int cmd, static const struct snd_soc_dai_ops tegra_admaif_dai_ops = { .hw_params = tegra_admaif_hw_params, .trigger = tegra_admaif_trigger, +<<<<<<< HEAD .shutdown = tegra_admaif_shutdown, .prepare = tegra_admaif_prepare, }; @@ -513,16 +545,24 @@ static void tegra_admaif_reg_dump(struct device *dev) pm_runtime_put_sync(dev); } +======= +}; + +>>>>>>> v5.9-rc4 static int tegra_admaif_get_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); +<<<<<<< HEAD struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; +======= +>>>>>>> v5.9-rc4 struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value; struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt); long *uctl_val = &ucontrol->value.integer.value[0]; +<<<<<<< HEAD if (strstr(kcontrol->id.name, "Playback Audio Channels")) *uctl_val = admaif->audio_ch_override[ADMAIF_TX_PATH][mc->reg]; else if (strstr(kcontrol->id.name, "Capture Audio Channels")) @@ -532,6 +572,9 @@ static int tegra_admaif_get_control(struct snd_kcontrol *kcontrol, else if (strstr(kcontrol->id.name, "Capture Client Channels")) *uctl_val = admaif->client_ch_override[ADMAIF_RX_PATH][mc->reg]; else if (strstr(kcontrol->id.name, "Playback Mono To Stereo")) +======= + if (strstr(kcontrol->id.name, "Playback Mono To Stereo")) +>>>>>>> v5.9-rc4 *uctl_val = admaif->mono_to_stereo[ADMAIF_TX_PATH][ec->reg]; else if (strstr(kcontrol->id.name, "Capture Mono To Stereo")) *uctl_val = admaif->mono_to_stereo[ADMAIF_RX_PATH][ec->reg]; @@ -539,8 +582,11 @@ static int tegra_admaif_get_control(struct snd_kcontrol *kcontrol, *uctl_val = admaif->stereo_to_mono[ADMAIF_TX_PATH][ec->reg]; else if (strstr(kcontrol->id.name, "Capture Stereo To Mono")) *uctl_val = admaif->stereo_to_mono[ADMAIF_RX_PATH][ec->reg]; +<<<<<<< HEAD else if (strstr(kcontrol->id.name, "APE Reg Dump")) *uctl_val = admaif->reg_dump_flag; +======= +>>>>>>> v5.9-rc4 return 0; } @@ -548,13 +594,17 @@ static int tegra_admaif_get_control(struct snd_kcontrol *kcontrol, static int tegra_admaif_put_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { +<<<<<<< HEAD struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; +======= +>>>>>>> v5.9-rc4 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value; struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt); int value = ucontrol->value.integer.value[0]; +<<<<<<< HEAD if (strstr(kcontrol->id.name, "Playback Audio Channels")) admaif->audio_ch_override[ADMAIF_TX_PATH][mc->reg] = value; else if (strstr(kcontrol->id.name, "Capture Audio Channels")) @@ -564,6 +614,9 @@ static int tegra_admaif_put_control(struct snd_kcontrol *kcontrol, else if (strstr(kcontrol->id.name, "Capture Client Channels")) admaif->client_ch_override[ADMAIF_RX_PATH][mc->reg] = value; else if (strstr(kcontrol->id.name, "Playback Mono To Stereo")) +======= + if (strstr(kcontrol->id.name, "Playback Mono To Stereo")) +>>>>>>> v5.9-rc4 admaif->mono_to_stereo[ADMAIF_TX_PATH][ec->reg] = value; else if (strstr(kcontrol->id.name, "Capture Mono To Stereo")) admaif->mono_to_stereo[ADMAIF_RX_PATH][ec->reg] = value; @@ -571,6 +624,7 @@ static int tegra_admaif_put_control(struct snd_kcontrol *kcontrol, admaif->stereo_to_mono[ADMAIF_TX_PATH][ec->reg] = value; else if (strstr(kcontrol->id.name, "Capture Stereo To Mono")) admaif->stereo_to_mono[ADMAIF_RX_PATH][ec->reg] = value; +<<<<<<< HEAD else if (strstr(kcontrol->id.name, "APE Reg Dump")) { admaif->reg_dump_flag = value; @@ -581,6 +635,8 @@ static int tegra_admaif_put_control(struct snd_kcontrol *kcontrol, tegra_admaif_reg_dump(cmpnt->dev); } } +======= +>>>>>>> v5.9-rc4 return 0; } @@ -595,33 +651,53 @@ static int tegra_admaif_dai_probe(struct snd_soc_dai *dai) return 0; } +<<<<<<< HEAD #define ADMAIF_DAI(id) \ { \ .name = "ADMAIF" #id, \ .probe = tegra_admaif_dai_probe, \ .playback = { \ .stream_name = "Playback " #id, \ +======= +#define DAI(dai_name) \ + { \ + .name = dai_name, \ + .probe = tegra_admaif_dai_probe, \ + .playback = { \ + .stream_name = dai_name " Playback", \ +>>>>>>> v5.9-rc4 .channels_min = 1, \ .channels_max = 16, \ .rates = SNDRV_PCM_RATE_8000_192000, \ .formats = SNDRV_PCM_FMTBIT_S8 | \ SNDRV_PCM_FMTBIT_S16_LE | \ +<<<<<<< HEAD SNDRV_PCM_FMTBIT_S24_LE | \ SNDRV_PCM_FMTBIT_S32_LE, \ }, \ .capture = { \ .stream_name = "Capture " #id, \ +======= + SNDRV_PCM_FMTBIT_S32_LE, \ + }, \ + .capture = { \ + .stream_name = dai_name " Capture", \ +>>>>>>> v5.9-rc4 .channels_min = 1, \ .channels_max = 16, \ .rates = SNDRV_PCM_RATE_8000_192000, \ .formats = SNDRV_PCM_FMTBIT_S8 | \ SNDRV_PCM_FMTBIT_S16_LE | \ +<<<<<<< HEAD SNDRV_PCM_FMTBIT_S24_LE | \ +======= +>>>>>>> v5.9-rc4 SNDRV_PCM_FMTBIT_S32_LE, \ }, \ .ops = &tegra_admaif_dai_ops, \ } +<<<<<<< HEAD #define ADMAIF_CODEC_FIFO_DAI(id) \ { \ .name = "ADMAIF" #id " FIFO", \ @@ -827,6 +903,42 @@ static const struct snd_soc_dapm_route tegra_admaif_routes[] = { ADMAIF_ROUTES(18), ADMAIF_ROUTES(19), ADMAIF_ROUTES(20) +======= +static struct snd_soc_dai_driver tegra210_admaif_cmpnt_dais[] = { + DAI("ADMAIF1"), + DAI("ADMAIF2"), + DAI("ADMAIF3"), + DAI("ADMAIF4"), + DAI("ADMAIF5"), + DAI("ADMAIF6"), + DAI("ADMAIF7"), + DAI("ADMAIF8"), + DAI("ADMAIF9"), + DAI("ADMAIF10"), +}; + +static struct snd_soc_dai_driver tegra186_admaif_cmpnt_dais[] = { + DAI("ADMAIF1"), + DAI("ADMAIF2"), + DAI("ADMAIF3"), + DAI("ADMAIF4"), + DAI("ADMAIF5"), + DAI("ADMAIF6"), + DAI("ADMAIF7"), + DAI("ADMAIF8"), + DAI("ADMAIF9"), + DAI("ADMAIF10"), + DAI("ADMAIF11"), + DAI("ADMAIF12"), + DAI("ADMAIF13"), + DAI("ADMAIF14"), + DAI("ADMAIF15"), + DAI("ADMAIF16"), + DAI("ADMAIF17"), + DAI("ADMAIF18"), + DAI("ADMAIF19"), + DAI("ADMAIF20"), +>>>>>>> v5.9-rc4 }; static const char * const tegra_admaif_stereo_conv_text[] = { @@ -834,6 +946,7 @@ static const char * const tegra_admaif_stereo_conv_text[] = { }; static const char * const tegra_admaif_mono_conv_text[] = { +<<<<<<< HEAD "ZERO", "COPY", }; @@ -851,6 +964,11 @@ static const char * const tegra_admaif_mono_conv_text[] = { 0, 16, 0, tegra_admaif_get_control, \ tegra_admaif_put_control) +======= + "Zero", "Copy", +}; + +>>>>>>> v5.9-rc4 /* * Below macro is added to avoid looping over all ADMAIFx controls related * to mono/stereo conversions in get()/put() callbacks. @@ -881,6 +999,7 @@ static const char * const tegra_admaif_mono_conv_text[] = { tegra_admaif_stereo_conv_text) static struct snd_kcontrol_new tegra210_admaif_controls[] = { +<<<<<<< HEAD TEGRA_ADMAIF_CHANNEL_CTRL(1), TEGRA_ADMAIF_CHANNEL_CTRL(2), TEGRA_ADMAIF_CHANNEL_CTRL(3), @@ -891,6 +1010,8 @@ static struct snd_kcontrol_new tegra210_admaif_controls[] = { TEGRA_ADMAIF_CHANNEL_CTRL(8), TEGRA_ADMAIF_CHANNEL_CTRL(9), TEGRA_ADMAIF_CHANNEL_CTRL(10), +======= +>>>>>>> v5.9-rc4 TEGRA_ADMAIF_CIF_CTRL(1), TEGRA_ADMAIF_CIF_CTRL(2), TEGRA_ADMAIF_CIF_CTRL(3), @@ -901,6 +1022,7 @@ static struct snd_kcontrol_new tegra210_admaif_controls[] = { TEGRA_ADMAIF_CIF_CTRL(8), TEGRA_ADMAIF_CIF_CTRL(9), TEGRA_ADMAIF_CIF_CTRL(10), +<<<<<<< HEAD SOC_SINGLE_EXT("APE Reg Dump", SND_SOC_NOPM, 0, 1, 0, tegra_admaif_get_control, tegra_admaif_put_control), }; @@ -926,6 +1048,11 @@ static struct snd_kcontrol_new tegra186_admaif_controls[] = { TEGRA_ADMAIF_CHANNEL_CTRL(18), TEGRA_ADMAIF_CHANNEL_CTRL(19), TEGRA_ADMAIF_CHANNEL_CTRL(20), +======= +}; + +static struct snd_kcontrol_new tegra186_admaif_controls[] = { +>>>>>>> v5.9-rc4 TEGRA_ADMAIF_CIF_CTRL(1), TEGRA_ADMAIF_CIF_CTRL(2), TEGRA_ADMAIF_CIF_CTRL(3), @@ -946,6 +1073,7 @@ static struct snd_kcontrol_new tegra186_admaif_controls[] = { TEGRA_ADMAIF_CIF_CTRL(18), TEGRA_ADMAIF_CIF_CTRL(19), TEGRA_ADMAIF_CIF_CTRL(20), +<<<<<<< HEAD SOC_SINGLE_EXT("APE Reg Dump", SND_SOC_NOPM, 0, 1, 0, tegra_admaif_get_control, tegra_admaif_put_control), }; @@ -955,6 +1083,11 @@ static const struct snd_soc_component_driver tegra210_admaif_cmpnt = { .num_dapm_widgets = TEGRA210_ADMAIF_CHANNEL_COUNT * 4, .dapm_routes = tegra_admaif_routes, .num_dapm_routes = TEGRA210_ADMAIF_CHANNEL_COUNT * 6, +======= +}; + +static const struct snd_soc_component_driver tegra210_admaif_cmpnt = { +>>>>>>> v5.9-rc4 .controls = tegra210_admaif_controls, .num_controls = ARRAY_SIZE(tegra210_admaif_controls), .pcm_construct = tegra_pcm_construct, @@ -968,10 +1101,13 @@ static const struct snd_soc_component_driver tegra210_admaif_cmpnt = { }; static const struct snd_soc_component_driver tegra186_admaif_cmpnt = { +<<<<<<< HEAD .dapm_widgets = tegra_admaif_widgets, .num_dapm_widgets = TEGRA186_ADMAIF_CHANNEL_COUNT * 4, .dapm_routes = tegra_admaif_routes, .num_dapm_routes = TEGRA186_ADMAIF_CHANNEL_COUNT * 6, +======= +>>>>>>> v5.9-rc4 .controls = tegra186_admaif_controls, .num_controls = ARRAY_SIZE(tegra186_admaif_controls), .pcm_construct = tegra_pcm_construct, @@ -992,7 +1128,10 @@ static const struct tegra_admaif_soc_data soc_data_tegra210 = { .global_base = TEGRA210_ADMAIF_GLOBAL_BASE, .tx_base = TEGRA210_ADMAIF_TX_BASE, .rx_base = TEGRA210_ADMAIF_RX_BASE, +<<<<<<< HEAD .is_isomgr_client = false, +======= +>>>>>>> v5.9-rc4 }; static const struct tegra_admaif_soc_data soc_data_tegra186 = { @@ -1003,7 +1142,10 @@ static const struct tegra_admaif_soc_data soc_data_tegra186 = { .global_base = TEGRA186_ADMAIF_GLOBAL_BASE, .tx_base = TEGRA186_ADMAIF_TX_BASE, .rx_base = TEGRA186_ADMAIF_RX_BASE, +<<<<<<< HEAD .is_isomgr_client = true, +======= +>>>>>>> v5.9-rc4 }; static const struct of_device_id tegra_admaif_of_match[] = { @@ -1045,6 +1187,7 @@ static int tegra_admaif_probe(struct platform_device *pdev) return -ENOMEM; for (i = 0; i < ADMAIF_PATHS; i++) { +<<<<<<< HEAD admaif->audio_ch_override[i] = devm_kcalloc(&pdev->dev, admaif->soc_data->num_ch, sizeof(unsigned int), GFP_KERNEL); @@ -1057,6 +1200,8 @@ static int tegra_admaif_probe(struct platform_device *pdev) if (!admaif->client_ch_override[i]) return -ENOMEM; +======= +>>>>>>> v5.9-rc4 admaif->mono_to_stereo[i] = devm_kcalloc(&pdev->dev, admaif->soc_data->num_ch, sizeof(unsigned int), GFP_KERNEL); @@ -1076,8 +1221,11 @@ static int tegra_admaif_probe(struct platform_device *pdev) if (IS_ERR(regs)) return PTR_ERR(regs); +<<<<<<< HEAD admaif->base_addr = regs; +======= +>>>>>>> v5.9-rc4 admaif->regmap = devm_regmap_init_mmio(&pdev->dev, regs, admaif->soc_data->regmap_conf); if (IS_ERR(admaif->regmap)) { @@ -1087,9 +1235,12 @@ static int tegra_admaif_probe(struct platform_device *pdev) regcache_cache_only(admaif->regmap, true); +<<<<<<< HEAD if (admaif->soc_data->is_isomgr_client) tegra_isomgr_adma_register(); +======= +>>>>>>> v5.9-rc4 regmap_update_bits(admaif->regmap, admaif->soc_data->global_base + TEGRA_ADMAIF_GLOBAL_ENABLE, 1, 1); @@ -1101,7 +1252,10 @@ static int tegra_admaif_probe(struct platform_device *pdev) CH_RX_REG(TEGRA_ADMAIF_RX_FIFO_READ, i); admaif->playback_dma_data[i].addr_width = 32; +<<<<<<< HEAD admaif->playback_dma_data[i].slave_id = i + 1; +======= +>>>>>>> v5.9-rc4 if (of_property_read_string_index(pdev->dev.of_node, "dma-names", (i * 2) + 1, @@ -1113,7 +1267,10 @@ static int tegra_admaif_probe(struct platform_device *pdev) } admaif->capture_dma_data[i].addr_width = 32; +<<<<<<< HEAD admaif->capture_dma_data[i].slave_id = i + 1; +======= +>>>>>>> v5.9-rc4 if (of_property_read_string_index(pdev->dev.of_node, "dma-names", @@ -1129,7 +1286,11 @@ static int tegra_admaif_probe(struct platform_device *pdev) err = devm_snd_soc_register_component(&pdev->dev, admaif->soc_data->cmpnt, admaif->soc_data->dais, +<<<<<<< HEAD admaif->soc_data->num_ch * 3); +======= + admaif->soc_data->num_ch); +>>>>>>> v5.9-rc4 if (err) { dev_err(&pdev->dev, "can't register ADMAIF component, err: %d\n", err); @@ -1143,11 +1304,14 @@ static int tegra_admaif_probe(struct platform_device *pdev) static int tegra_admaif_remove(struct platform_device *pdev) { +<<<<<<< HEAD struct tegra_admaif *admaif = dev_get_drvdata(&pdev->dev); if (admaif->soc_data->is_isomgr_client) tegra_isomgr_adma_unregister(); +======= +>>>>>>> v5.9-rc4 pm_runtime_disable(&pdev->dev); return 0; diff --git a/sound/soc/tegra/tegra210_admaif.h b/sound/soc/tegra/tegra210_admaif.h index 96686dc9..63947771 100644 --- a/sound/soc/tegra/tegra210_admaif.h +++ b/sound/soc/tegra/tegra210_admaif.h @@ -2,7 +2,11 @@ /* * tegra210_admaif.h - Tegra ADMAIF registers * +<<<<<<< HEAD + * Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved. +======= * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. +>>>>>>> v5.9-rc4 * */ @@ -148,15 +152,33 @@ struct tegra_admaif_soc_data { unsigned int tx_base; unsigned int rx_base; unsigned int num_ch; +<<<<<<< HEAD + bool is_isomgr_client; +======= +>>>>>>> v5.9-rc4 }; struct tegra_admaif { struct snd_dmaengine_dai_dma_data *capture_dma_data; struct snd_dmaengine_dai_dma_data *playback_dma_data; const struct tegra_admaif_soc_data *soc_data; +<<<<<<< HEAD + unsigned int *audio_ch_override[ADMAIF_PATHS]; + unsigned int *client_ch_override[ADMAIF_PATHS]; + unsigned int *mono_to_stereo[ADMAIF_PATHS]; + unsigned int *stereo_to_mono[ADMAIF_PATHS]; + struct regmap *regmap; + int reg_dump_flag; + void __iomem *base_addr; +}; + +extern void tegra_adma_dump_ch_reg(void); + +======= unsigned int *mono_to_stereo[ADMAIF_PATHS]; unsigned int *stereo_to_mono[ADMAIF_PATHS]; struct regmap *regmap; }; +>>>>>>> v5.9-rc4 #endif diff --git a/sound/soc/tegra/tegra210_ahub.c b/sound/soc/tegra/tegra210_ahub.c index 66287a7c..96c254ac 100644 --- a/sound/soc/tegra/tegra210_ahub.c +++ b/sound/soc/tegra/tegra210_ahub.c @@ -1,8 +1,17 @@ // SPDX-License-Identifier: GPL-2.0-only +<<<<<<< HEAD +/* + * tegra210_ahub.c - Tegra210 AHUB driver + * + * Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved. + * + */ +======= // // tegra210_ahub.c - Tegra210 AHUB driver // // Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. +>>>>>>> v5.9-rc4 #include #include @@ -30,7 +39,11 @@ static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl, unsigned int reg_val; reg = e->reg + (TEGRA210_XBAR_PART1_RX * i); +<<<<<<< HEAD + snd_soc_component_read(cmpnt, reg, ®_val); +======= reg_val = snd_soc_component_read(cmpnt, reg); +>>>>>>> v5.9-rc4 reg_val &= ahub->soc_data->mask[i]; if (reg_val) { @@ -94,6 +107,51 @@ static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl, return 0; } +<<<<<<< HEAD +void tegra210_ahub_write_ram(struct regmap *regmap, unsigned int reg_ctrl, + unsigned int reg_data, unsigned int ram_offset, + unsigned int *data, size_t size) +{ + unsigned int val = 0; + int i = 0; + + val = ram_offset & TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK; + val |= TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN; + val |= TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN; + val |= TEGRA210_AHUBRAMCTL_CTRL_RW_WRITE; + + regmap_write(regmap, reg_ctrl, val); + for (i = 0; i < size; i++) + regmap_write(regmap, reg_data, data[i]); + + return; +} +EXPORT_SYMBOL_GPL(tegra210_ahub_write_ram); + +void tegra210_ahub_read_ram(struct regmap *regmap, unsigned int reg_ctrl, + unsigned int reg_data, unsigned int ram_offset, + unsigned int *data, size_t size) +{ + unsigned int val = 0; + int i = 0; + + val = ram_offset & TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK; + val |= TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN; + val |= TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN; + val |= TEGRA210_AHUBRAMCTL_CTRL_RW_READ; + + regmap_write(regmap, reg_ctrl, val); + /* Since all ahub non-io modules work under same ahub clock it is not + necessary to check ahub read busy bit after every read */ + for (i = 0; i < size; i++) + regmap_read(regmap, reg_data, &data[i]); + + return; +} +EXPORT_SYMBOL_GPL(tegra210_ahub_read_ram); + +======= +>>>>>>> v5.9-rc4 static struct snd_soc_dai_driver tegra210_ahub_dais[] = { DAI(ADMAIF1), DAI(ADMAIF2), @@ -110,9 +168,64 @@ static struct snd_soc_dai_driver tegra210_ahub_dais[] = { DAI(I2S3), DAI(I2S4), DAI(I2S5), +<<<<<<< HEAD + DAI(SFC1), + DAI(SFC2), + DAI(SFC3), + DAI(SFC4), + DAI(MIXER1-1), + DAI(MIXER1-2), + DAI(MIXER1-3), + DAI(MIXER1-4), + DAI(MIXER1-5), + DAI(MIXER1-6), + DAI(MIXER1-7), + DAI(MIXER1-8), + DAI(MIXER1-9), + DAI(MIXER1-10), + DAI(AFC1), + DAI(AFC2), + DAI(AFC3), + DAI(AFC4), + DAI(AFC5), + DAI(AFC6), + DAI(OPE1), + DAI(SPKPROT1), + DAI(MVC1), + DAI(MVC2), + DAI(IQC1-1), + DAI(IQC1-2), + DAI(IQC2-1), + DAI(IQC2-2), DAI(DMIC1), DAI(DMIC2), DAI(DMIC3), + DAI(AMX1), + DAI(AMX1-1), + DAI(AMX1-2), + DAI(AMX1-3), + DAI(AMX1-4), + DAI(AMX2), + DAI(AMX2-1), + DAI(AMX2-2), + DAI(AMX2-3), + DAI(AMX2-4), + DAI(ADX1-1), + DAI(ADX1-2), + DAI(ADX1-3), + DAI(ADX1-4), + DAI(ADX1), + DAI(ADX2-1), + DAI(ADX2-2), + DAI(ADX2-3), + DAI(ADX2-4), + DAI(ADX2), + DAI(OPE2), +======= + DAI(DMIC1), + DAI(DMIC2), + DAI(DMIC3), +>>>>>>> v5.9-rc4 }; static struct snd_soc_dai_driver tegra186_ahub_dais[] = { @@ -126,6 +239,65 @@ static struct snd_soc_dai_driver tegra186_ahub_dais[] = { DAI(ADMAIF8), DAI(ADMAIF9), DAI(ADMAIF10), +<<<<<<< HEAD + DAI(I2S1), + DAI(I2S2), + DAI(I2S3), + DAI(I2S4), + DAI(I2S5), + DAI(SFC1), + DAI(SFC2), + DAI(SFC3), + DAI(SFC4), + DAI(MIXER1-1), + DAI(MIXER1-2), + DAI(MIXER1-3), + DAI(MIXER1-4), + DAI(MIXER1-5), + DAI(MIXER1-6), + DAI(MIXER1-7), + DAI(MIXER1-8), + DAI(MIXER1-9), + DAI(MIXER1-10), + DAI(AFC1), + DAI(AFC2), + DAI(AFC3), + DAI(AFC4), + DAI(AFC5), + DAI(AFC6), + DAI(OPE1), + DAI(SPKPROT1), + DAI(MVC1), + DAI(MVC2), + DAI(IQC1-1), + DAI(IQC1-2), + DAI(IQC2-1), + DAI(IQC2-2), + DAI(DMIC1), + DAI(DMIC2), + DAI(DMIC3), + DAI(AMX1), + DAI(AMX1-1), + DAI(AMX1-2), + DAI(AMX1-3), + DAI(AMX1-4), + DAI(AMX2), + DAI(AMX2-1), + DAI(AMX2-2), + DAI(AMX2-3), + DAI(AMX2-4), + DAI(ADX1-1), + DAI(ADX1-2), + DAI(ADX1-3), + DAI(ADX1-4), + DAI(ADX1), + DAI(ADX2-1), + DAI(ADX2-2), + DAI(ADX2-3), + DAI(ADX2-4), + DAI(ADX2), +======= +>>>>>>> v5.9-rc4 DAI(ADMAIF11), DAI(ADMAIF12), DAI(ADMAIF13), @@ -136,6 +308,38 @@ static struct snd_soc_dai_driver tegra186_ahub_dais[] = { DAI(ADMAIF18), DAI(ADMAIF19), DAI(ADMAIF20), +<<<<<<< HEAD + DAI(I2S6), + DAI(AMX3), + DAI(AMX3-1), + DAI(AMX3-2), + DAI(AMX3-3), + DAI(AMX3-4), + DAI(AMX4), + DAI(AMX4-1), + DAI(AMX4-2), + DAI(AMX4-3), + DAI(AMX4-4), + DAI(ADX3-1), + DAI(ADX3-2), + DAI(ADX3-3), + DAI(ADX3-4), + DAI(ADX3), + DAI(ADX4-1), + DAI(ADX4-2), + DAI(ADX4-3), + DAI(ADX4-4), + DAI(ADX4), + DAI(DMIC4), + DAI(ASRC1-1), + DAI(ASRC1-2), + DAI(ASRC1-3), + DAI(ASRC1-4), + DAI(ASRC1-5), + DAI(ASRC1-6), + DAI(ASRC1-7), + DAI(ARAD1), +======= DAI(I2S1), DAI(I2S2), DAI(I2S3), @@ -146,6 +350,7 @@ static struct snd_soc_dai_driver tegra186_ahub_dais[] = { DAI(DMIC2), DAI(DMIC3), DAI(DMIC4), +>>>>>>> v5.9-rc4 DAI(DSPK1), DAI(DSPK2), }; @@ -167,9 +372,52 @@ static const char * const tegra210_ahub_mux_texts[] = { "I2S3", "I2S4", "I2S5", +<<<<<<< HEAD + "SFC1", + "SFC2", + "SFC3", + "SFC4", + /* index 0..19 above are inputs of PART0 Mux */ + "MIXER1-1", + "MIXER1-2", + "MIXER1-3", + "MIXER1-4", + "MIXER1-5", + "AMX1", + "AMX2", + "AFC1", + "AFC2", + "AFC3", + "AFC4", + "AFC5", + "AFC6", + /* index 20..34 above are inputs of PART1 Mux */ + "OPE1", + "OPE2", + "SPKPROT1", + "MVC1", + "MVC2", + "IQC1-1", + "IQC1-2", + "IQC2-1", + "IQC2-2", "DMIC1", "DMIC2", "DMIC3", + "ADX1-1", + "ADX1-2", + "ADX1-3", + "ADX1-4", + "ADX2-1", + "ADX2-2", + "ADX2-3", + "ADX2-4", + /* index 35..53 above are inputs of PART2 Mux */ +======= + "DMIC1", + "DMIC2", + "DMIC3", +>>>>>>> v5.9-rc4 }; static const char * const tegra186_ahub_mux_texts[] = { @@ -196,14 +444,78 @@ static const char * const tegra186_ahub_mux_texts[] = { "I2S4", "I2S5", "I2S6", - "ADMAIF17", - "ADMAIF18", - "ADMAIF19", - "ADMAIF20", +<<<<<<< HEAD + "SFC1", + "SFC2", + "SFC3", + "SFC4", + /* index 0..19 above are inputs of PART0 Mux */ + "MIXER1-1", + "MIXER1-2", + "MIXER1-3", + "MIXER1-4", + "MIXER1-5", + "AMX1", + "AMX2", + "AMX3", + "AMX4", + "ARAD1", + "AFC1", + "AFC2", + "AFC3", + "AFC4", + "AFC5", + "AFC6", + /* index 20..34 above are inputs of PART1 Mux */ + "OPE1", + "SPKPROT1", + "MVC1", + "MVC2", + "IQC1-1", + "IQC1-2", + "IQC2-1", + "IQC2-2", "DMIC1", "DMIC2", "DMIC3", "DMIC4", + "ADX1-1", + "ADX1-2", + "ADX1-3", + "ADX1-4", + "ADX2-1", + "ADX2-2", + "ADX2-3", + "ADX2-4", + /* index 35..53 above are inputs of PART2 Mux */ + "ADX3-1", + "ADX3-2", + "ADX3-3", + "ADX3-4", + "ADX4-1", + "ADX4-2", + "ADX4-3", + "ADX4-4", +======= +>>>>>>> v5.9-rc4 + "ADMAIF17", + "ADMAIF18", + "ADMAIF19", + "ADMAIF20", +<<<<<<< HEAD + "ASRC1-1", + "ASRC1-2", + "ASRC1-3", + "ASRC1-4", + "ASRC1-5", + "ASRC1-6", + /* index 54..71 above are inputs of PART3 Mux */ +======= + "DMIC1", + "DMIC2", + "DMIC3", + "DMIC4", +>>>>>>> v5.9-rc4 }; static const unsigned int tegra210_ahub_mux_values[] = { @@ -223,9 +535,52 @@ static const unsigned int tegra210_ahub_mux_values[] = { MUX_VALUE(0, 18), MUX_VALUE(0, 19), MUX_VALUE(0, 20), +<<<<<<< HEAD + MUX_VALUE(0, 24), + MUX_VALUE(0, 25), + MUX_VALUE(0, 26), + MUX_VALUE(0, 27), + /* index 0..19 above are inputs of PART0 Mux */ + MUX_VALUE(1, 0), + MUX_VALUE(1, 1), + MUX_VALUE(1, 2), + MUX_VALUE(1, 3), + MUX_VALUE(1, 4), + MUX_VALUE(1, 8), + MUX_VALUE(1, 9), + MUX_VALUE(1, 24), + MUX_VALUE(1, 25), + MUX_VALUE(1, 26), + MUX_VALUE(1, 27), + MUX_VALUE(1, 28), + MUX_VALUE(1, 29), + /* index 20..34 above are inputs of PART1 Mux */ + MUX_VALUE(2, 0), + MUX_VALUE(2, 1), + MUX_VALUE(2, 4), + MUX_VALUE(2, 8), + MUX_VALUE(2, 9), + MUX_VALUE(2, 12), + MUX_VALUE(2, 13), + MUX_VALUE(2, 14), + MUX_VALUE(2, 15), MUX_VALUE(2, 18), MUX_VALUE(2, 19), MUX_VALUE(2, 20), + MUX_VALUE(2, 24), + MUX_VALUE(2, 25), + MUX_VALUE(2, 26), + MUX_VALUE(2, 27), + MUX_VALUE(2, 28), + MUX_VALUE(2, 29), + MUX_VALUE(2, 30), + MUX_VALUE(2, 31), + /* index 35..53 above are inputs of PART2 Mux */ +======= + MUX_VALUE(2, 18), + MUX_VALUE(2, 19), + MUX_VALUE(2, 20), +>>>>>>> v5.9-rc4 }; static const unsigned int tegra186_ahub_mux_values[] = { @@ -252,14 +607,78 @@ static const unsigned int tegra186_ahub_mux_values[] = { MUX_VALUE(0, 19), MUX_VALUE(0, 20), MUX_VALUE(0, 21), - MUX_VALUE(3, 16), - MUX_VALUE(3, 17), - MUX_VALUE(3, 18), - MUX_VALUE(3, 19), +<<<<<<< HEAD + MUX_VALUE(0, 24), + MUX_VALUE(0, 25), + MUX_VALUE(0, 26), + MUX_VALUE(0, 27), + /* index 0..19 above are inputs of PART0 Mux */ + MUX_VALUE(1, 0), + MUX_VALUE(1, 1), + MUX_VALUE(1, 2), + MUX_VALUE(1, 3), + MUX_VALUE(1, 4), + MUX_VALUE(1, 8), + MUX_VALUE(1, 9), + MUX_VALUE(1, 10), + MUX_VALUE(1, 11), + MUX_VALUE(1, 16), + MUX_VALUE(1, 24), + MUX_VALUE(1, 25), + MUX_VALUE(1, 26), + MUX_VALUE(1, 27), + MUX_VALUE(1, 28), + MUX_VALUE(1, 29), + /* index 20..34 above are inputs of PART1 Mux */ + MUX_VALUE(2, 0), + MUX_VALUE(2, 4), + MUX_VALUE(2, 8), + MUX_VALUE(2, 9), + MUX_VALUE(2, 12), + MUX_VALUE(2, 13), + MUX_VALUE(2, 14), + MUX_VALUE(2, 15), MUX_VALUE(2, 18), MUX_VALUE(2, 19), MUX_VALUE(2, 20), MUX_VALUE(2, 21), + MUX_VALUE(2, 24), + MUX_VALUE(2, 25), + MUX_VALUE(2, 26), + MUX_VALUE(2, 27), + MUX_VALUE(2, 28), + MUX_VALUE(2, 29), + MUX_VALUE(2, 30), + MUX_VALUE(2, 31), + /* index 35..53 above are inputs of PART2 Mux */ + MUX_VALUE(3, 0), + MUX_VALUE(3, 1), + MUX_VALUE(3, 2), + MUX_VALUE(3, 3), + MUX_VALUE(3, 4), + MUX_VALUE(3, 5), + MUX_VALUE(3, 6), + MUX_VALUE(3, 7), +======= +>>>>>>> v5.9-rc4 + MUX_VALUE(3, 16), + MUX_VALUE(3, 17), + MUX_VALUE(3, 18), + MUX_VALUE(3, 19), +<<<<<<< HEAD + MUX_VALUE(3, 24), + MUX_VALUE(3, 25), + MUX_VALUE(3, 26), + MUX_VALUE(3, 27), + MUX_VALUE(3, 28), + MUX_VALUE(3, 29), + /* index 54..71 above are inputs of PART3 Mux */ +======= + MUX_VALUE(2, 18), + MUX_VALUE(2, 19), + MUX_VALUE(2, 20), + MUX_VALUE(2, 21), +>>>>>>> v5.9-rc4 }; /* Controls for t210 */ @@ -278,6 +697,44 @@ MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11); MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12); MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13); MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14); +<<<<<<< HEAD +MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18); +MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19); +MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a); +MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b); +MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20); +MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21); +MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22); +MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23); +MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24); +MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25); +MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26); +MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27); +MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28); +MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29); +MUX_ENUM_CTRL_DECL(t210_afc1_tx, 0x34); +MUX_ENUM_CTRL_DECL(t210_afc2_tx, 0x35); +MUX_ENUM_CTRL_DECL(t210_afc3_tx, 0x36); +MUX_ENUM_CTRL_DECL(t210_afc4_tx, 0x37); +MUX_ENUM_CTRL_DECL(t210_afc5_tx, 0x38); +MUX_ENUM_CTRL_DECL(t210_afc6_tx, 0x39); +MUX_ENUM_CTRL_DECL(t210_ope1_tx, 0x40); +MUX_ENUM_CTRL_DECL(t210_ope2_tx, 0x41); +MUX_ENUM_CTRL_DECL(t210_spkprot_tx, 0x44); +MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48); +MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49); +MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50); +MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51); +MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52); +MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53); +MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54); +MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55); +MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56); +MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57); +MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58); +MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59); +======= +>>>>>>> v5.9-rc4 /* Controls for t186 */ MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00); @@ -295,6 +752,53 @@ MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11); MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12); MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13); MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14); +<<<<<<< HEAD +MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18); +MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19); +MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a); +MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b); +MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20); +MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21); +MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22); +MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23); +MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24); +MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25); +MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26); +MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27); +MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28); +MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29); +MUX_ENUM_CTRL_DECL_186(t186_afc1_tx, 0x38); +MUX_ENUM_CTRL_DECL_186(t186_afc2_tx, 0x39); +MUX_ENUM_CTRL_DECL_186(t186_afc3_tx, 0x3a); +MUX_ENUM_CTRL_DECL_186(t186_afc4_tx, 0x3b); +MUX_ENUM_CTRL_DECL_186(t186_afc5_tx, 0x3c); +MUX_ENUM_CTRL_DECL_186(t186_afc6_tx, 0x3d); +MUX_ENUM_CTRL_DECL_186(t186_ope1_tx, 0x40); +MUX_ENUM_CTRL_DECL_186(t186_spkprot_tx, 0x44); +MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48); +MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49); +MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50); +MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51); +MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52); +MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53); +MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54); +MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55); +MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56); +MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57); +MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60); +MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61); +MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30); +MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31); +MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58); +MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59); +MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a); +MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b); +MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64); +MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65); +MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66); +MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67); +======= +>>>>>>> v5.9-rc4 MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a); MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b); MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c); @@ -302,12 +806,27 @@ MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d); MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e); MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f); MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15); +<<<<<<< HEAD +MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62); +MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63); +======= MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30); MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31); +>>>>>>> v5.9-rc4 MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68); MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69); MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a); MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b); +<<<<<<< HEAD +MUX_ENUM_CTRL_DECL_186(t186_asrc11_tx, 0x6c); +MUX_ENUM_CTRL_DECL_186(t186_asrc12_tx, 0x6d); +MUX_ENUM_CTRL_DECL_186(t186_asrc13_tx, 0x6e); +MUX_ENUM_CTRL_DECL_186(t186_asrc14_tx, 0x6f); +MUX_ENUM_CTRL_DECL_186(t186_asrc15_tx, 0x70); +MUX_ENUM_CTRL_DECL_186(t186_asrc16_tx, 0x71); +MUX_ENUM_CTRL_DECL_186(t186_asrc17_tx, 0x72); +======= +>>>>>>> v5.9-rc4 /* * The number of entries in, and order of, this array is closely tied to the @@ -330,9 +849,64 @@ static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = { WIDGETS("I2S3", t210_i2s3_tx), WIDGETS("I2S4", t210_i2s4_tx), WIDGETS("I2S5", t210_i2s5_tx), +<<<<<<< HEAD + WIDGETS("SFC1", t210_sfc1_tx), + WIDGETS("SFC2", t210_sfc2_tx), + WIDGETS("SFC3", t210_sfc3_tx), + WIDGETS("SFC4", t210_sfc4_tx), + WIDGETS("MIXER1-1", t210_mixer11_tx), + WIDGETS("MIXER1-2", t210_mixer12_tx), + WIDGETS("MIXER1-3", t210_mixer13_tx), + WIDGETS("MIXER1-4", t210_mixer14_tx), + WIDGETS("MIXER1-5", t210_mixer15_tx), + WIDGETS("MIXER1-6", t210_mixer16_tx), + WIDGETS("MIXER1-7", t210_mixer17_tx), + WIDGETS("MIXER1-8", t210_mixer18_tx), + WIDGETS("MIXER1-9", t210_mixer19_tx), + WIDGETS("MIXER1-10", t210_mixer110_tx), + WIDGETS("AFC1", t210_afc1_tx), + WIDGETS("AFC2", t210_afc2_tx), + WIDGETS("AFC3", t210_afc3_tx), + WIDGETS("AFC4", t210_afc4_tx), + WIDGETS("AFC5", t210_afc5_tx), + WIDGETS("AFC6", t210_afc6_tx), + WIDGETS("OPE1", t210_ope1_tx), + WIDGETS("OPE2", t210_ope2_tx), + WIDGETS("SPKPROT1", t210_spkprot_tx), + WIDGETS("MVC1", t210_mvc1_tx), + WIDGETS("MVC2", t210_mvc2_tx), + WIDGETS("AMX1-1", t210_amx11_tx), + WIDGETS("AMX1-2", t210_amx12_tx), + WIDGETS("AMX1-3", t210_amx13_tx), + WIDGETS("AMX1-4", t210_amx14_tx), + WIDGETS("AMX2-1", t210_amx21_tx), + WIDGETS("AMX2-2", t210_amx22_tx), + WIDGETS("AMX2-3", t210_amx23_tx), + WIDGETS("AMX2-4", t210_amx24_tx), + WIDGETS("ADX1", t210_adx1_tx), + WIDGETS("ADX2", t210_adx2_tx), + TX_WIDGETS("IQC1-1"), + TX_WIDGETS("IQC1-2"), + TX_WIDGETS("IQC2-1"), + TX_WIDGETS("IQC2-2"), TX_WIDGETS("DMIC1"), TX_WIDGETS("DMIC2"), TX_WIDGETS("DMIC3"), + TX_WIDGETS("AMX1"), + TX_WIDGETS("ADX1-1"), + TX_WIDGETS("ADX1-2"), + TX_WIDGETS("ADX1-3"), + TX_WIDGETS("ADX1-4"), + TX_WIDGETS("AMX2"), + TX_WIDGETS("ADX2-1"), + TX_WIDGETS("ADX2-2"), + TX_WIDGETS("ADX2-3"), + TX_WIDGETS("ADX2-4"), +======= + TX_WIDGETS("DMIC1"), + TX_WIDGETS("DMIC2"), + TX_WIDGETS("DMIC3"), +>>>>>>> v5.9-rc4 }; static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = { @@ -346,6 +920,65 @@ static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = { WIDGETS("ADMAIF8", t186_admaif8_tx), WIDGETS("ADMAIF9", t186_admaif9_tx), WIDGETS("ADMAIF10", t186_admaif10_tx), +<<<<<<< HEAD + WIDGETS("I2S1", t186_i2s1_tx), + WIDGETS("I2S2", t186_i2s2_tx), + WIDGETS("I2S3", t186_i2s3_tx), + WIDGETS("I2S4", t186_i2s4_tx), + WIDGETS("I2S5", t186_i2s5_tx), + WIDGETS("SFC1", t186_sfc1_tx), + WIDGETS("SFC2", t186_sfc2_tx), + WIDGETS("SFC3", t186_sfc3_tx), + WIDGETS("SFC4", t186_sfc4_tx), + WIDGETS("MIXER1-1", t186_mixer11_tx), + WIDGETS("MIXER1-2", t186_mixer12_tx), + WIDGETS("MIXER1-3", t186_mixer13_tx), + WIDGETS("MIXER1-4", t186_mixer14_tx), + WIDGETS("MIXER1-5", t186_mixer15_tx), + WIDGETS("MIXER1-6", t186_mixer16_tx), + WIDGETS("MIXER1-7", t186_mixer17_tx), + WIDGETS("MIXER1-8", t186_mixer18_tx), + WIDGETS("MIXER1-9", t186_mixer19_tx), + WIDGETS("MIXER1-10", t186_mixer110_tx), + WIDGETS("AFC1", t186_afc1_tx), + WIDGETS("AFC2", t186_afc2_tx), + WIDGETS("AFC3", t186_afc3_tx), + WIDGETS("AFC4", t186_afc4_tx), + WIDGETS("AFC5", t186_afc5_tx), + WIDGETS("AFC6", t186_afc6_tx), + WIDGETS("OPE1", t186_ope1_tx), + WIDGETS("SPKPROT1", t186_spkprot_tx), + WIDGETS("MVC1", t186_mvc1_tx), + WIDGETS("MVC2", t186_mvc2_tx), + WIDGETS("AMX1-1", t186_amx11_tx), + WIDGETS("AMX1-2", t186_amx12_tx), + WIDGETS("AMX1-3", t186_amx13_tx), + WIDGETS("AMX1-4", t186_amx14_tx), + WIDGETS("AMX2-1", t186_amx21_tx), + WIDGETS("AMX2-2", t186_amx22_tx), + WIDGETS("AMX2-3", t186_amx23_tx), + WIDGETS("AMX2-4", t186_amx24_tx), + WIDGETS("ADX1", t186_adx1_tx), + WIDGETS("ADX2", t186_adx2_tx), + TX_WIDGETS("IQC1-1"), + TX_WIDGETS("IQC1-2"), + TX_WIDGETS("IQC2-1"), + TX_WIDGETS("IQC2-2"), + TX_WIDGETS("DMIC1"), + TX_WIDGETS("DMIC2"), + TX_WIDGETS("DMIC3"), + TX_WIDGETS("AMX1"), + TX_WIDGETS("ADX1-1"), + TX_WIDGETS("ADX1-2"), + TX_WIDGETS("ADX1-3"), + TX_WIDGETS("ADX1-4"), + TX_WIDGETS("AMX2"), + TX_WIDGETS("ADX2-1"), + TX_WIDGETS("ADX2-2"), + TX_WIDGETS("ADX2-3"), + TX_WIDGETS("ADX2-4"), +======= +>>>>>>> v5.9-rc4 WIDGETS("ADMAIF11", t186_admaif11_tx), WIDGETS("ADMAIF12", t186_admaif12_tx), WIDGETS("ADMAIF13", t186_admaif13_tx), @@ -356,6 +989,138 @@ static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = { WIDGETS("ADMAIF18", t186_admaif18_tx), WIDGETS("ADMAIF19", t186_admaif19_tx), WIDGETS("ADMAIF20", t186_admaif20_tx), +<<<<<<< HEAD + WIDGETS("I2S6", t186_i2s6_tx), + WIDGETS("AMX3-1", t186_amx31_tx), + WIDGETS("AMX3-2", t186_amx32_tx), + WIDGETS("AMX3-3", t186_amx33_tx), + WIDGETS("AMX3-4", t186_amx34_tx), + WIDGETS("AMX4-1", t186_amx41_tx), + WIDGETS("AMX4-2", t186_amx42_tx), + WIDGETS("AMX4-3", t186_amx43_tx), + WIDGETS("AMX4-4", t186_amx44_tx), + WIDGETS("ADX3", t186_adx3_tx), + WIDGETS("ADX4", t186_adx4_tx), + WIDGETS("ASRC1-1", t186_asrc11_tx), + WIDGETS("ASRC1-2", t186_asrc12_tx), + WIDGETS("ASRC1-3", t186_asrc13_tx), + WIDGETS("ASRC1-4", t186_asrc14_tx), + WIDGETS("ASRC1-5", t186_asrc15_tx), + WIDGETS("ASRC1-6", t186_asrc16_tx), + WIDGETS("ASRC1-7", t186_asrc17_tx), + WIDGETS("DSPK1", t186_dspk1_tx), + WIDGETS("DSPK2", t186_dspk2_tx), + TX_WIDGETS("AMX3"), + TX_WIDGETS("ADX3-1"), + TX_WIDGETS("ADX3-2"), + TX_WIDGETS("ADX3-3"), + TX_WIDGETS("ADX3-4"), + TX_WIDGETS("AMX4"), + TX_WIDGETS("ADX4-1"), + TX_WIDGETS("ADX4-2"), + TX_WIDGETS("ADX4-3"), + TX_WIDGETS("ADX4-4"), + TX_WIDGETS("DMIC4"), + TX_WIDGETS("ARAD1"), +}; + +#define TEGRA_COMMON_ROUTES(name) \ + { name " RX", NULL, name " Receive"}, \ + { name " Transmit", NULL, name " TX"}, \ + { name " TX", NULL, name " Mux"}, \ + { name " Mux", "ADMAIF1", "ADMAIF1 RX" }, \ + { name " Mux", "ADMAIF2", "ADMAIF2 RX" }, \ + { name " Mux", "ADMAIF3", "ADMAIF3 RX" }, \ + { name " Mux", "ADMAIF4", "ADMAIF4 RX" }, \ + { name " Mux", "ADMAIF5", "ADMAIF5 RX" }, \ + { name " Mux", "ADMAIF6", "ADMAIF6 RX" }, \ + { name " Mux", "ADMAIF7", "ADMAIF7 RX" }, \ + { name " Mux", "ADMAIF8", "ADMAIF8 RX" }, \ + { name " Mux", "ADMAIF9", "ADMAIF9 RX" }, \ + { name " Mux", "ADMAIF10", "ADMAIF10 RX" }, \ + { name " Mux", "I2S1", "I2S1 RX" }, \ + { name " Mux", "I2S2", "I2S2 RX" }, \ + { name " Mux", "I2S3", "I2S3 RX" }, \ + { name " Mux", "I2S4", "I2S4 RX" }, \ + { name " Mux", "I2S5", "I2S5 RX" }, \ + { name " Mux", "SFC1", "SFC1 RX" }, \ + { name " Mux", "SFC2", "SFC2 RX" }, \ + { name " Mux", "SFC3", "SFC3 RX" }, \ + { name " Mux", "SFC4", "SFC4 RX" }, \ + { name " Mux", "MIXER1-1", "MIXER1-1 RX" }, \ + { name " Mux", "MIXER1-2", "MIXER1-2 RX" }, \ + { name " Mux", "MIXER1-3", "MIXER1-3 RX" }, \ + { name " Mux", "MIXER1-4", "MIXER1-4 RX" }, \ + { name " Mux", "MIXER1-5", "MIXER1-5 RX" }, \ + { name " Mux", "AFC1", "AFC1 RX" }, \ + { name " Mux", "AFC2", "AFC2 RX" }, \ + { name " Mux", "AFC3", "AFC3 RX" }, \ + { name " Mux", "AFC4", "AFC4 RX" }, \ + { name " Mux", "AFC5", "AFC5 RX" }, \ + { name " Mux", "AFC6", "AFC6 RX" }, \ + { name " Mux", "OPE1", "OPE1 RX" }, \ + { name " Mux", "MVC1", "MVC1 RX" }, \ + { name " Mux", "MVC2", "MVC2 RX" }, \ + { name " Mux", "IQC1-1", "IQC1-1 RX" }, \ + { name " Mux", "IQC1-2", "IQC1-2 RX" }, \ + { name " Mux", "IQC2-1", "IQC2-1 RX" }, \ + { name " Mux", "IQC2-2", "IQC2-2 RX" }, \ + { name " Mux", "DMIC1", "DMIC1 RX" }, \ + { name " Mux", "DMIC2", "DMIC2 RX" }, \ + { name " Mux", "DMIC3", "DMIC3 RX" }, \ + { name " Mux", "AMX1", "AMX1 RX" }, \ + { name " Mux", "ADX1-1", "ADX1-1 RX" }, \ + { name " Mux", "ADX1-2", "ADX1-2 RX" }, \ + { name " Mux", "ADX1-3", "ADX1-3 RX" }, \ + { name " Mux", "ADX1-4", "ADX1-4 RX" }, \ + { name " Mux", "AMX2", "AMX2 RX" }, \ + { name " Mux", "ADX2-1", "ADX2-1 RX" }, \ + { name " Mux", "ADX2-2", "ADX2-2 RX" }, \ + { name " Mux", "ADX2-3", "ADX2-3 RX" }, \ + { name " Mux", "ADX2-4", "ADX2-4 RX" }, + +#define TEGRA210_ONLY_ROUTES(name) \ + { name " Mux", "OPE2", "OPE2 RX" }, + +#define TEGRA186_ONLY_ROUTES(name) \ + { name " Mux", "ADMAIF11", "ADMAIF11 RX" }, \ + { name " Mux", "ADMAIF12", "ADMAIF12 RX" }, \ + { name " Mux", "ADMAIF13", "ADMAIF13 RX" }, \ + { name " Mux", "ADMAIF14", "ADMAIF14 RX" }, \ + { name " Mux", "ADMAIF15", "ADMAIF15 RX" }, \ + { name " Mux", "ADMAIF16", "ADMAIF16 RX" }, \ + { name " Mux", "ADMAIF17", "ADMAIF17 RX" }, \ + { name " Mux", "ADMAIF18", "ADMAIF18 RX" }, \ + { name " Mux", "ADMAIF19", "ADMAIF19 RX" }, \ + { name " Mux", "ADMAIF20", "ADMAIF20 RX" }, \ + { name " Mux", "DMIC4", "DMIC4 RX" }, \ + { name " Mux", "I2S6", "I2S6 RX" }, \ + { name " Mux", "ASRC1-1", "ASRC1-1 RX" }, \ + { name " Mux", "ASRC1-2", "ASRC1-2 RX" }, \ + { name " Mux", "ASRC1-3", "ASRC1-3 RX" }, \ + { name " Mux", "ASRC1-4", "ASRC1-4 RX" }, \ + { name " Mux", "ASRC1-5", "ASRC1-5 RX" }, \ + { name " Mux", "ASRC1-6", "ASRC1-6 RX" }, \ + { name " Mux", "AMX3", "AMX3 RX" }, \ + { name " Mux", "ADX3-1", "ADX3-1 RX" }, \ + { name " Mux", "ADX3-2", "ADX3-2 RX" }, \ + { name " Mux", "ADX3-3", "ADX3-3 RX" }, \ + { name " Mux", "ADX3-4", "ADX3-4 RX" }, \ + { name " Mux", "AMX4", "AMX4 RX" }, \ + { name " Mux", "ADX4-1", "ADX4-1 RX" }, \ + { name " Mux", "ADX4-2", "ADX4-2 RX" }, \ + { name " Mux", "ADX4-3", "ADX4-3 RX" }, \ + { name " Mux", "ADX4-4", "ADX4-4 RX" }, \ + { name " Mux", "ARAD1", "ARAD1 RX" }, + +#define TEGRA210_ROUTES(name) \ + TEGRA_COMMON_ROUTES(name) \ + TEGRA210_ONLY_ROUTES(name) + +#define TEGRA186_ROUTES(name) \ + TEGRA_COMMON_ROUTES(name) \ + TEGRA186_ONLY_ROUTES(name) +======= WIDGETS("I2S1", t186_i2s1_tx), WIDGETS("I2S2", t186_i2s2_tx), WIDGETS("I2S3", t186_i2s3_tx), @@ -419,12 +1184,193 @@ static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = { { name " XBAR-Capture", NULL, name " XBAR-TX" }, \ { name " Capture", NULL, name " XBAR-Capture" }, +>>>>>>> v5.9-rc4 /* * The number of entries in, and order of, this array is closely tied to the * calculation of tegra210_ahub_codec.num_dapm_routes near the end of * tegra210_ahub_probe() */ static const struct snd_soc_dapm_route tegra210_ahub_routes[] = { +<<<<<<< HEAD + TEGRA210_ROUTES("ADMAIF1") + TEGRA210_ROUTES("ADMAIF2") + TEGRA210_ROUTES("ADMAIF3") + TEGRA210_ROUTES("ADMAIF4") + TEGRA210_ROUTES("ADMAIF5") + TEGRA210_ROUTES("ADMAIF6") + TEGRA210_ROUTES("ADMAIF7") + TEGRA210_ROUTES("ADMAIF8") + TEGRA210_ROUTES("ADMAIF9") + TEGRA210_ROUTES("ADMAIF10") + TEGRA210_ROUTES("I2S1") + TEGRA210_ROUTES("I2S2") + TEGRA210_ROUTES("I2S3") + TEGRA210_ROUTES("I2S4") + TEGRA210_ROUTES("I2S5") + TEGRA210_ROUTES("SFC1") + TEGRA210_ROUTES("SFC2") + TEGRA210_ROUTES("SFC3") + TEGRA210_ROUTES("SFC4") + TEGRA210_ROUTES("MIXER1-1") + TEGRA210_ROUTES("MIXER1-2") + TEGRA210_ROUTES("MIXER1-3") + TEGRA210_ROUTES("MIXER1-4") + TEGRA210_ROUTES("MIXER1-5") + TEGRA210_ROUTES("MIXER1-6") + TEGRA210_ROUTES("MIXER1-7") + TEGRA210_ROUTES("MIXER1-8") + TEGRA210_ROUTES("MIXER1-9") + TEGRA210_ROUTES("MIXER1-10") + TEGRA210_ROUTES("AFC1") + TEGRA210_ROUTES("AFC2") + TEGRA210_ROUTES("AFC3") + TEGRA210_ROUTES("AFC4") + TEGRA210_ROUTES("AFC5") + TEGRA210_ROUTES("AFC6") + TEGRA210_ROUTES("OPE1") + TEGRA210_ROUTES("OPE2") + TEGRA210_ROUTES("SPKPROT1") + TEGRA210_ROUTES("MVC1") + TEGRA210_ROUTES("MVC2") + TEGRA210_ROUTES("AMX1-1") + TEGRA210_ROUTES("AMX1-2") + TEGRA210_ROUTES("AMX1-3") + TEGRA210_ROUTES("AMX1-4") + TEGRA210_ROUTES("AMX2-1") + TEGRA210_ROUTES("AMX2-2") + TEGRA210_ROUTES("AMX2-3") + TEGRA210_ROUTES("AMX2-4") + TEGRA210_ROUTES("ADX1") + TEGRA210_ROUTES("ADX2") + IN_OUT_ROUTES("IQC1-1") + IN_OUT_ROUTES("IQC1-2") + IN_OUT_ROUTES("IQC2-1") + IN_OUT_ROUTES("IQC2-1") + IN_OUT_ROUTES("DMIC1") + IN_OUT_ROUTES("DMIC2") + IN_OUT_ROUTES("DMIC3") + IN_OUT_ROUTES("AMX1") + IN_OUT_ROUTES("AMX2") + IN_OUT_ROUTES("ADX1-1") + IN_OUT_ROUTES("ADX1-2") + IN_OUT_ROUTES("ADX1-3") + IN_OUT_ROUTES("ADX1-4") + IN_OUT_ROUTES("ADX2-1") + IN_OUT_ROUTES("ADX2-2") + IN_OUT_ROUTES("ADX2-3") + IN_OUT_ROUTES("ADX2-4") +}; + +static const struct snd_soc_dapm_route tegra186_ahub_routes[] = { + TEGRA186_ROUTES("ADMAIF1") + TEGRA186_ROUTES("ADMAIF2") + TEGRA186_ROUTES("ADMAIF3") + TEGRA186_ROUTES("ADMAIF4") + TEGRA186_ROUTES("ADMAIF5") + TEGRA186_ROUTES("ADMAIF6") + TEGRA186_ROUTES("ADMAIF7") + TEGRA186_ROUTES("ADMAIF8") + TEGRA186_ROUTES("ADMAIF9") + TEGRA186_ROUTES("ADMAIF10") + TEGRA186_ROUTES("I2S1") + TEGRA186_ROUTES("I2S2") + TEGRA186_ROUTES("I2S3") + TEGRA186_ROUTES("I2S4") + TEGRA186_ROUTES("I2S5") + TEGRA186_ROUTES("SFC1") + TEGRA186_ROUTES("SFC2") + TEGRA186_ROUTES("SFC3") + TEGRA186_ROUTES("SFC4") + TEGRA186_ROUTES("MIXER1-1") + TEGRA186_ROUTES("MIXER1-2") + TEGRA186_ROUTES("MIXER1-3") + TEGRA186_ROUTES("MIXER1-4") + TEGRA186_ROUTES("MIXER1-5") + TEGRA186_ROUTES("MIXER1-6") + TEGRA186_ROUTES("MIXER1-7") + TEGRA186_ROUTES("MIXER1-8") + TEGRA186_ROUTES("MIXER1-9") + TEGRA186_ROUTES("MIXER1-10") + TEGRA186_ROUTES("AFC1") + TEGRA186_ROUTES("AFC2") + TEGRA186_ROUTES("AFC3") + TEGRA186_ROUTES("AFC4") + TEGRA186_ROUTES("AFC5") + TEGRA186_ROUTES("AFC6") + TEGRA186_ROUTES("OPE1") + TEGRA186_ROUTES("SPKPROT1") + TEGRA186_ROUTES("MVC1") + TEGRA186_ROUTES("MVC2") + TEGRA186_ROUTES("AMX1-1") + TEGRA186_ROUTES("AMX1-2") + TEGRA186_ROUTES("AMX1-3") + TEGRA186_ROUTES("AMX1-4") + TEGRA186_ROUTES("AMX2-1") + TEGRA186_ROUTES("AMX2-2") + TEGRA186_ROUTES("AMX2-3") + TEGRA186_ROUTES("AMX2-4") + TEGRA186_ROUTES("ADX1") + TEGRA186_ROUTES("ADX2") + IN_OUT_ROUTES("IQC1-1") + IN_OUT_ROUTES("IQC1-2") + IN_OUT_ROUTES("IQC2-1") + IN_OUT_ROUTES("IQC2-1") + IN_OUT_ROUTES("DMIC1") + IN_OUT_ROUTES("DMIC2") + IN_OUT_ROUTES("DMIC3") + IN_OUT_ROUTES("AMX1") + IN_OUT_ROUTES("AMX2") + IN_OUT_ROUTES("ADX1-1") + IN_OUT_ROUTES("ADX1-2") + IN_OUT_ROUTES("ADX1-3") + IN_OUT_ROUTES("ADX1-4") + IN_OUT_ROUTES("ADX2-1") + IN_OUT_ROUTES("ADX2-2") + IN_OUT_ROUTES("ADX2-3") + IN_OUT_ROUTES("ADX2-4") + TEGRA186_ROUTES("ADMAIF11") + TEGRA186_ROUTES("ADMAIF12") + TEGRA186_ROUTES("ADMAIF13") + TEGRA186_ROUTES("ADMAIF14") + TEGRA186_ROUTES("ADMAIF15") + TEGRA186_ROUTES("ADMAIF16") + TEGRA186_ROUTES("ADMAIF17") + TEGRA186_ROUTES("ADMAIF18") + TEGRA186_ROUTES("ADMAIF19") + TEGRA186_ROUTES("ADMAIF20") + TEGRA186_ROUTES("AMX3-1") + TEGRA186_ROUTES("AMX3-2") + TEGRA186_ROUTES("AMX3-3") + TEGRA186_ROUTES("AMX3-4") + TEGRA186_ROUTES("AMX4-1") + TEGRA186_ROUTES("AMX4-2") + TEGRA186_ROUTES("AMX4-3") + TEGRA186_ROUTES("AMX4-4") + TEGRA186_ROUTES("ADX3") + TEGRA186_ROUTES("ADX4") + TEGRA186_ROUTES("I2S6") + TEGRA186_ROUTES("ASRC1-1") + TEGRA186_ROUTES("ASRC1-2") + TEGRA186_ROUTES("ASRC1-3") + TEGRA186_ROUTES("ASRC1-4") + TEGRA186_ROUTES("ASRC1-5") + TEGRA186_ROUTES("ASRC1-6") + TEGRA186_ROUTES("ASRC1-7") + TEGRA186_ROUTES("DSPK1") + TEGRA186_ROUTES("DSPK2") + IN_OUT_ROUTES("DMIC4") + IN_OUT_ROUTES("AMX3") + IN_OUT_ROUTES("AMX4") + IN_OUT_ROUTES("ADX3-1") + IN_OUT_ROUTES("ADX3-2") + IN_OUT_ROUTES("ADX3-3") + IN_OUT_ROUTES("ADX3-4") + IN_OUT_ROUTES("ADX4-1") + IN_OUT_ROUTES("ADX4-2") + IN_OUT_ROUTES("ADX4-3") + IN_OUT_ROUTES("ADX4-4") + IN_OUT_ROUTES("ARAD1") +======= TEGRA_FE_ROUTES("ADMAIF1") TEGRA_FE_ROUTES("ADMAIF2") TEGRA_FE_ROUTES("ADMAIF3") @@ -501,6 +1447,7 @@ static const struct snd_soc_dapm_route tegra186_ahub_routes[] = { TEGRA186_MUX_ROUTES("I2S6") TEGRA186_MUX_ROUTES("DSPK1") TEGRA186_MUX_ROUTES("DSPK2") +>>>>>>> v5.9-rc4 }; static const struct snd_soc_component_driver tegra210_ahub_component = { @@ -564,7 +1511,11 @@ static const struct of_device_id tegra_ahub_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_ahub_of_match); +<<<<<<< HEAD +static int tegra_ahub_runtime_suspend(struct device *dev) +======= static int __maybe_unused tegra_ahub_runtime_suspend(struct device *dev) +>>>>>>> v5.9-rc4 { struct tegra_ahub *ahub = dev_get_drvdata(dev); @@ -576,7 +1527,11 @@ static int __maybe_unused tegra_ahub_runtime_suspend(struct device *dev) return 0; } +<<<<<<< HEAD +static int tegra_ahub_runtime_resume(struct device *dev) +======= static int __maybe_unused tegra_ahub_runtime_resume(struct device *dev) +>>>>>>> v5.9-rc4 { struct tegra_ahub *ahub = dev_get_drvdata(dev); int err; diff --git a/sound/soc/tegra/tegra210_ahub.h b/sound/soc/tegra/tegra210_ahub.h index 47802bbe..23c5c551 100644 --- a/sound/soc/tegra/tegra210_ahub.h +++ b/sound/soc/tegra/tegra210_ahub.h @@ -2,7 +2,11 @@ /* * tegra210_ahub.h - TEGRA210 AHUB * +<<<<<<< HEAD + * Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved. +======= * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. +>>>>>>> v5.9-rc4 * */ @@ -28,6 +32,16 @@ #define TEGRA186_XBAR_REG_MASK_3 0x3f0f00ff #define TEGRA186_XBAR_UPDATE_MAX_REG 4 +<<<<<<< HEAD +/* Fields in *AHUBRAMCTL_CTRL; used by different AHUB modules */ +#define TEGRA210_AHUBRAMCTL_CTRL_RW_READ 0 +#define TEGRA210_AHUBRAMCTL_CTRL_RW_WRITE (1 << 14) +#define TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN (1 << 13) +#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN (1 << 12) +#define TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK 0x1ff + +======= +>>>>>>> v5.9-rc4 #define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG) #define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX + \ @@ -40,6 +54,34 @@ #define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32) +<<<<<<< HEAD +#define DAI(sname) \ + { \ + .name = #sname, \ + .playback = { \ + .stream_name = #sname " Receive", \ + .channels_min = 1, \ + .channels_max = 16, \ + .rates = SNDRV_PCM_RATE_8000_192000, \ + .formats = SNDRV_PCM_FMTBIT_S8 | \ + SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + }, \ + .capture = { \ + .stream_name = #sname " Transmit", \ + .channels_min = 1, \ + .channels_max = 16, \ + .rates = SNDRV_PCM_RATE_8000_192000, \ + .formats = SNDRV_PCM_FMTBIT_S8 | \ + SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + }, \ + } + +======= +>>>>>>> v5.9-rc4 #define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues) \ { \ .reg = xreg, \ @@ -74,6 +116,21 @@ tegra_ahub_get_value_enum, \ tegra_ahub_put_value_enum) +<<<<<<< HEAD +#define WIDGETS(sname, ename) \ + SND_SOC_DAPM_AIF_IN(sname " RX", NULL, 0, SND_SOC_NOPM, 0, 0), \ + SND_SOC_DAPM_AIF_OUT(sname " TX", NULL, 0, SND_SOC_NOPM, 0, 0), \ + SND_SOC_DAPM_MUX(sname " Mux", SND_SOC_NOPM, 0, 0, \ + &ename##_control) + +#define TX_WIDGETS(sname) \ + SND_SOC_DAPM_AIF_IN(sname " RX", NULL, 0, SND_SOC_NOPM, 0, 0), \ + SND_SOC_DAPM_AIF_OUT(sname " TX", NULL, 0, SND_SOC_NOPM, 0, 0) + +#define IN_OUT_ROUTES(name) \ + { name " RX", NULL, name " Receive" }, \ + { name " Transmit", NULL, name " TX" }, +======= #define WIDGETS(sname, ename) \ SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \ SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \ @@ -109,6 +166,7 @@ }, \ } +>>>>>>> v5.9-rc4 struct tegra_ahub_soc_data { const struct regmap_config *regmap_config; const struct snd_soc_component_driver *cmpnt_drv; @@ -124,4 +182,14 @@ struct tegra_ahub { struct clk *clk; }; +<<<<<<< HEAD +void tegra210_ahub_write_ram(struct regmap *regmap, unsigned int reg_ctrl, + unsigned int reg_data, unsigned int ram_offset, + unsigned int *data, size_t size); +void tegra210_ahub_read_ram(struct regmap *regmap, unsigned int reg_ctrl, + unsigned int reg_data, unsigned int ram_offset, + unsigned int *data, size_t size); + +======= +>>>>>>> v5.9-rc4 #endif diff --git a/sound/soc/tegra/tegra210_dmic.c b/sound/soc/tegra/tegra210_dmic.c index a661f40b..565c3232 100644 --- a/sound/soc/tegra/tegra210_dmic.c +++ b/sound/soc/tegra/tegra210_dmic.c @@ -1,4 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only +<<<<<<< HEAD +/* + * tegra210_dmic.c - Tegra210 DMIC driver + * + * Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved. + * + */ +#include +#include +======= // // tegra210_dmic.c - Tegra210 DMIC driver // @@ -7,6 +17,7 @@ #include #include #include +>>>>>>> v5.9-rc4 #include #include #include @@ -40,7 +51,11 @@ static const struct reg_default tegra210_dmic_reg_defaults[] = { { TEGRA210_DMIC_LP_BIQUAD_1_COEF_4, 0x0 }, }; +<<<<<<< HEAD +static int tegra210_dmic_runtime_suspend(struct device *dev) +======= static int __maybe_unused tegra210_dmic_runtime_suspend(struct device *dev) +>>>>>>> v5.9-rc4 { struct tegra210_dmic *dmic = dev_get_drvdata(dev); @@ -52,7 +67,11 @@ static int __maybe_unused tegra210_dmic_runtime_suspend(struct device *dev) return 0; } +<<<<<<< HEAD +static int tegra210_dmic_runtime_resume(struct device *dev) +======= static int __maybe_unused tegra210_dmic_runtime_resume(struct device *dev) +>>>>>>> v5.9-rc4 { struct tegra210_dmic *dmic = dev_get_drvdata(dev); int err; @@ -69,6 +88,15 @@ static int __maybe_unused tegra210_dmic_runtime_resume(struct device *dev) return 0; } +<<<<<<< HEAD +static const unsigned int tegra210_dmic_fmts[] = { + 0, + TEGRA_ACIF_BITS_16, + TEGRA_ACIF_BITS_32, +}; + +======= +>>>>>>> v5.9-rc4 static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -84,6 +112,11 @@ static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream, channels = params_channels(params); cif_conf.audio_ch = channels; +<<<<<<< HEAD + if (dmic->audio_ch_override) + cif_conf.audio_ch = dmic->audio_ch_override; +======= +>>>>>>> v5.9-rc4 switch (dmic->ch_select) { case DMIC_CH_SELECT_LEFT: @@ -99,6 +132,11 @@ static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream, } srate = params_rate(params); +<<<<<<< HEAD + if (dmic->srate_override) + srate = dmic->srate_override; +======= +>>>>>>> v5.9-rc4 /* * DMIC clock rate is a multiple of 'Over Sampling Ratio' and @@ -127,10 +165,17 @@ static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream, /* * Use LP filter gain register to apply boost. +<<<<<<< HEAD + * Boost Gain control has 100x factor. + */ + if (dmic->boost_gain) + gain_q23 = (gain_q23 * dmic->boost_gain) / 100; +======= * Boost Gain Volume control has 100x factor. */ if (dmic->boost_gain) gain_q23 = div_u64(gain_q23 * dmic->boost_gain, 100); +>>>>>>> v5.9-rc4 regmap_write(dmic->regmap, TEGRA210_DMIC_LP_FILTER_GAIN, (unsigned int)gain_q23); @@ -144,9 +189,19 @@ static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream, break; default: dev_err(dai->dev, "unsupported format!\n"); +<<<<<<< HEAD + return -ENOTSUPP; + } + + if (dmic->audio_bits_override) + cif_conf.audio_bits = + tegra210_dmic_fmts[dmic->audio_bits_override]; + +======= return -EOPNOTSUPP; } +>>>>>>> v5.9-rc4 cif_conf.client_bits = TEGRA_ACIF_BITS_24; cif_conf.mono_conv = dmic->mono_to_stereo; cif_conf.stereo_conv = dmic->stereo_to_mono; @@ -162,7 +217,11 @@ static int tegra210_dmic_get_control(struct snd_kcontrol *kcontrol, struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp); +<<<<<<< HEAD + if (strstr(kcontrol->id.name, "Boost Gain")) +======= if (strstr(kcontrol->id.name, "Boost Gain Volume")) +>>>>>>> v5.9-rc4 ucontrol->value.integer.value[0] = dmic->boost_gain; else if (strstr(kcontrol->id.name, "Channel Select")) ucontrol->value.integer.value[0] = dmic->ch_select; @@ -170,6 +229,15 @@ static int tegra210_dmic_get_control(struct snd_kcontrol *kcontrol, ucontrol->value.integer.value[0] = dmic->mono_to_stereo; else if (strstr(kcontrol->id.name, "Stereo To Mono")) ucontrol->value.integer.value[0] = dmic->stereo_to_mono; +<<<<<<< HEAD + else if (strstr(kcontrol->id.name, "Audio Bit Format")) + ucontrol->value.integer.value[0] = dmic->audio_bits_override; + else if (strstr(kcontrol->id.name, "Sample Rate")) + ucontrol->value.integer.value[0] = dmic->srate_override; + else if (strstr(kcontrol->id.name, "Audio Channels")) + ucontrol->value.integer.value[0] = dmic->audio_ch_override; +======= +>>>>>>> v5.9-rc4 else if (strstr(kcontrol->id.name, "OSR Value")) ucontrol->value.integer.value[0] = dmic->osr_val; else if (strstr(kcontrol->id.name, "LR Polarity Select")) @@ -185,7 +253,11 @@ static int tegra210_dmic_put_control(struct snd_kcontrol *kcontrol, struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp); int value = ucontrol->value.integer.value[0]; +<<<<<<< HEAD + if (strstr(kcontrol->id.name, "Boost Gain")) +======= if (strstr(kcontrol->id.name, "Boost Gain Volume")) +>>>>>>> v5.9-rc4 dmic->boost_gain = value; else if (strstr(kcontrol->id.name, "Channel Select")) dmic->ch_select = ucontrol->value.integer.value[0]; @@ -193,6 +265,15 @@ static int tegra210_dmic_put_control(struct snd_kcontrol *kcontrol, dmic->mono_to_stereo = value; else if (strstr(kcontrol->id.name, "Stereo To Mono")) dmic->stereo_to_mono = value; +<<<<<<< HEAD + else if (strstr(kcontrol->id.name, "Audio Bit Format")) + dmic->audio_bits_override = value; + else if (strstr(kcontrol->id.name, "Sample Rate")) + dmic->srate_override = value; + else if (strstr(kcontrol->id.name, "Audio Channels")) + dmic->audio_ch_override = value; +======= +>>>>>>> v5.9-rc4 else if (strstr(kcontrol->id.name, "OSR Value")) dmic->osr_val = value; else if (strstr(kcontrol->id.name, "LR Polarity Select")) @@ -205,11 +286,41 @@ static const struct snd_soc_dai_ops tegra210_dmic_dai_ops = { .hw_params = tegra210_dmic_hw_params, }; +<<<<<<< HEAD +/* + * Three DAIs are exposed + * 1. "CIF" DAI for connecting with XBAR + * 2. "DAP" DAI for connecting with CODEC + * 3. "DUMMY_SOURCE" can be used when no external + * codec connection is available. In such case + * "DAP" is connected with "DUMMY_SOURCE" + */ +static struct snd_soc_dai_driver tegra210_dmic_dais[] = { + { + .name = "CIF", + .capture = { + .stream_name = "DMIC Transmit", +======= static struct snd_soc_dai_driver tegra210_dmic_dais[] = { { .name = "DMIC-CIF", .capture = { .stream_name = "CIF-Capture", +>>>>>>> v5.9-rc4 + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, +<<<<<<< HEAD + .ops = &tegra210_dmic_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "DAP", + .playback = { + .stream_name = "DMIC Receive", .channels_min = 1, .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_48000, @@ -217,16 +328,37 @@ static struct snd_soc_dai_driver tegra210_dmic_dais[] = { SNDRV_PCM_FMTBIT_S32_LE, }, }, + { + .name = "DUMMY_SOURCE", + .capture = { + .stream_name = "Dummy Capture", +======= + }, { .name = "DMIC-DAP", .capture = { .stream_name = "DAP-Capture", +>>>>>>> v5.9-rc4 .channels_min = 1, .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_48000, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, }, +<<<<<<< HEAD + } +}; + +static const struct snd_soc_dapm_widget tegra210_dmic_widgets[] = { + SND_SOC_DAPM_AIF_IN("DMIC TX", NULL, 0, TEGRA210_DMIC_ENABLE, 0, 0), + SND_SOC_DAPM_MIC("Dummy Input", NULL), +}; + +static const struct snd_soc_dapm_route tegra210_dmic_routes[] = { + { "DMIC TX", NULL, "DMIC Receive" }, + { "DMIC Transmit", NULL, "DMIC TX" }, + { "Dummy Capture", NULL, "Dummy Input" }, +======= .ops = &tegra210_dmic_dai_ops, .symmetric_rates = 1, }, @@ -243,6 +375,7 @@ static const struct snd_soc_dapm_route tegra210_dmic_routes[] = { { "CIF-Capture", NULL, "TX" }, { "TX", NULL, "DAP-Capture" }, { "DAP-Capture", NULL, "MIC" }, +>>>>>>> v5.9-rc4 }; static const char * const tegra210_dmic_ch_select[] = { @@ -254,7 +387,11 @@ static const struct soc_enum tegra210_dmic_ch_enum = tegra210_dmic_ch_select); static const char * const tegra210_dmic_mono_conv_text[] = { +<<<<<<< HEAD + "ZERO", "COPY", +======= "Zero", "Copy", +>>>>>>> v5.9-rc4 }; static const char * const tegra210_dmic_stereo_conv_text[] = { @@ -269,6 +406,19 @@ static const struct soc_enum tegra210_dmic_stereo_conv_enum = SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_stereo_conv_text), tegra210_dmic_stereo_conv_text); +<<<<<<< HEAD +static const char * const tegra210_dmic_format_text[] = { + "None", + "16", + "32", +}; + +static const struct soc_enum tegra210_dmic_format_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_format_text), + tegra210_dmic_format_text); + +======= +>>>>>>> v5.9-rc4 static const char * const tegra210_dmic_osr_text[] = { "OSR_64", "OSR_128", "OSR_256", }; @@ -286,7 +436,11 @@ static const struct soc_enum tegra210_dmic_lrsel_enum = tegra210_dmic_lrsel_text); static const struct snd_kcontrol_new tegra210_dmic_controls[] = { +<<<<<<< HEAD + SOC_SINGLE_EXT("Boost Gain", 0, 0, MAX_BOOST_GAIN, 0, +======= SOC_SINGLE_EXT("Boost Gain Volume", 0, 0, MAX_BOOST_GAIN, 0, +>>>>>>> v5.9-rc4 tegra210_dmic_get_control, tegra210_dmic_put_control), SOC_ENUM_EXT("Channel Select", tegra210_dmic_ch_enum, tegra210_dmic_get_control, tegra210_dmic_put_control), @@ -296,6 +450,15 @@ static const struct snd_kcontrol_new tegra210_dmic_controls[] = { SOC_ENUM_EXT("Stereo To Mono", tegra210_dmic_stereo_conv_enum, tegra210_dmic_get_control, tegra210_dmic_put_control), +<<<<<<< HEAD + SOC_ENUM_EXT("Audio Bit Format", tegra210_dmic_format_enum, + tegra210_dmic_get_control, tegra210_dmic_put_control), + SOC_SINGLE_EXT("Sample Rate", 0, 0, 48000, 0, tegra210_dmic_get_control, + tegra210_dmic_put_control), + SOC_SINGLE_EXT("Audio Channels", 0, 0, 2, 0, tegra210_dmic_get_control, + tegra210_dmic_put_control), +======= +>>>>>>> v5.9-rc4 SOC_ENUM_EXT("OSR Value", tegra210_dmic_osr_enum, tegra210_dmic_get_control, tegra210_dmic_put_control), SOC_ENUM_EXT("LR Polarity Select", tegra210_dmic_lrsel_enum, @@ -369,6 +532,15 @@ static const struct regmap_config tegra210_dmic_regmap_config = { .cache_type = REGCACHE_FLAT, }; +<<<<<<< HEAD +static const struct of_device_id tegra210_dmic_of_match[] = { + { .compatible = "nvidia,tegra210-dmic" }, + {}, +}; +MODULE_DEVICE_TABLE(of, tegra210_dmic_of_match); + +======= +>>>>>>> v5.9-rc4 static int tegra210_dmic_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -434,12 +606,15 @@ static const struct dev_pm_ops tegra210_dmic_pm_ops = { pm_runtime_force_resume) }; +<<<<<<< HEAD +======= static const struct of_device_id tegra210_dmic_of_match[] = { { .compatible = "nvidia,tegra210-dmic" }, {}, }; MODULE_DEVICE_TABLE(of, tegra210_dmic_of_match); +>>>>>>> v5.9-rc4 static struct platform_driver tegra210_dmic_driver = { .driver = { .name = "tegra210-dmic", diff --git a/sound/soc/tegra/tegra210_dmic.h b/sound/soc/tegra/tegra210_dmic.h index 6418c223..bcb8338d 100644 --- a/sound/soc/tegra/tegra210_dmic.h +++ b/sound/soc/tegra/tegra210_dmic.h @@ -2,7 +2,11 @@ /* * tegra210_dmic.h - Definitions for Tegra210 DMIC driver * +<<<<<<< HEAD + * Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved. +======= * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. +>>>>>>> v5.9-rc4 * */ @@ -71,6 +75,12 @@ enum tegra_dmic_lrsel { struct tegra210_dmic { struct clk *clk_dmic; struct regmap *regmap; +<<<<<<< HEAD + unsigned int audio_ch_override; + unsigned int audio_bits_override; + unsigned int srate_override; +======= +>>>>>>> v5.9-rc4 unsigned int mono_to_stereo; unsigned int stereo_to_mono; unsigned int boost_gain; diff --git a/sound/soc/tegra/tegra210_i2s.c b/sound/soc/tegra/tegra210_i2s.c index a383bd5c..3c4d84cc 100644 --- a/sound/soc/tegra/tegra210_i2s.c +++ b/sound/soc/tegra/tegra210_i2s.c @@ -1,8 +1,17 @@ // SPDX-License-Identifier: GPL-2.0-only +<<<<<<< HEAD +/* + * tegra210_i2s.c - Tegra210 I2S driver + * + * Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved. + * + */ +======= // // tegra210_i2s.c - Tegra210 I2S driver // // Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. +>>>>>>> v5.9-rc4 #include #include @@ -164,7 +173,11 @@ static int tegra210_i2s_init(struct snd_soc_dapm_widget *w, return tegra210_i2s_sw_reset(compnt, is_playback); } +<<<<<<< HEAD +static int tegra210_i2s_runtime_suspend(struct device *dev) +======= static int __maybe_unused tegra210_i2s_runtime_suspend(struct device *dev) +>>>>>>> v5.9-rc4 { struct tegra210_i2s *i2s = dev_get_drvdata(dev); @@ -176,7 +189,11 @@ static int __maybe_unused tegra210_i2s_runtime_suspend(struct device *dev) return 0; } +<<<<<<< HEAD +static int tegra210_i2s_runtime_resume(struct device *dev) +======= static int __maybe_unused tegra210_i2s_runtime_resume(struct device *dev) +>>>>>>> v5.9-rc4 { struct tegra210_i2s *i2s = dev_get_drvdata(dev); int err; @@ -196,6 +213,17 @@ static int __maybe_unused tegra210_i2s_runtime_resume(struct device *dev) static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s, unsigned int data_offset) { +<<<<<<< HEAD + unsigned int mask = I2S_CTRL_DATA_OFFSET_MASK; + unsigned int shift = I2S_DATA_SHIFT; + unsigned int reg; + + reg = TEGRA210_I2S_TX_CTRL; + regmap_update_bits(i2s->regmap, reg, mask, data_offset << shift); + + reg = TEGRA210_I2S_RX_CTRL; + regmap_update_bits(i2s->regmap, reg, mask, data_offset << shift); +======= /* Capture path */ regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL, I2S_CTRL_DATA_OFFSET_MASK, @@ -205,6 +233,7 @@ static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s, regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL, I2S_CTRL_DATA_OFFSET_MASK, data_offset << I2S_DATA_SHIFT); +>>>>>>> v5.9-rc4 } static int tegra210_i2s_set_fmt(struct snd_soc_dai *dai, @@ -321,8 +350,27 @@ static int tegra210_i2s_get_control(struct snd_kcontrol *kcontrol, if (strstr(kcontrol->id.name, "Loopback")) *uctl_val = i2s->loopback; +<<<<<<< HEAD + else if (strstr(kcontrol->id.name, "Sample Rate")) + *uctl_val = i2s->srate_override; else if (strstr(kcontrol->id.name, "FSYNC Width")) *uctl_val = i2s->fsync_width; + else if (strstr(kcontrol->id.name, "Playback Audio Bit Format")) + *uctl_val = i2s->audio_fmt_override[I2S_RX_PATH]; + else if (strstr(kcontrol->id.name, "Capture Audio Bit Format")) + *uctl_val = i2s->audio_fmt_override[I2S_TX_PATH]; + else if (strstr(kcontrol->id.name, "Client Bit Format")) + *uctl_val = i2s->client_fmt_override; + else if (strstr(kcontrol->id.name, "Playback Audio Channels")) + *uctl_val = i2s->audio_ch_override[I2S_RX_PATH]; + else if (strstr(kcontrol->id.name, "Capture Audio Channels")) + *uctl_val = i2s->audio_ch_override[I2S_TX_PATH]; + else if (strstr(kcontrol->id.name, "Client Channels")) + *uctl_val = i2s->client_ch_override; +======= + else if (strstr(kcontrol->id.name, "FSYNC Width")) + *uctl_val = i2s->fsync_width; +>>>>>>> v5.9-rc4 else if (strstr(kcontrol->id.name, "Capture Stereo To Mono")) *uctl_val = i2s->stereo_to_mono[I2S_TX_PATH]; else if (strstr(kcontrol->id.name, "Capture Mono To Stereo")) @@ -353,6 +401,11 @@ static int tegra210_i2s_put_control(struct snd_kcontrol *kcontrol, I2S_CTRL_LPBK_MASK, i2s->loopback << I2S_CTRL_LPBK_SHIFT); +<<<<<<< HEAD + } else if (strstr(kcontrol->id.name, "Sample Rate")) { + i2s->srate_override = value; +======= +>>>>>>> v5.9-rc4 } else if (strstr(kcontrol->id.name, "FSYNC Width")) { /* * Frame sync width is used only for FSYNC modes and not @@ -368,6 +421,21 @@ static int tegra210_i2s_put_control(struct snd_kcontrol *kcontrol, I2S_CTRL_FSYNC_WIDTH_MASK, i2s->fsync_width << I2S_FSYNC_WIDTH_SHIFT); +<<<<<<< HEAD + } else if (strstr(kcontrol->id.name, "Playback Audio Bit Format")) { + i2s->audio_fmt_override[I2S_RX_PATH] = value; + } else if (strstr(kcontrol->id.name, "Capture Audio Bit Format")) { + i2s->audio_fmt_override[I2S_TX_PATH] = value; + } else if (strstr(kcontrol->id.name, "Client Bit Format")) { + i2s->client_fmt_override = value; + } else if (strstr(kcontrol->id.name, "Playback Audio Channels")) { + i2s->audio_ch_override[I2S_RX_PATH] = value; + } else if (strstr(kcontrol->id.name, "Capture Audio Channels")) { + i2s->audio_ch_override[I2S_TX_PATH] = value; + } else if (strstr(kcontrol->id.name, "Client Channels")) { + i2s->client_ch_override = value; +======= +>>>>>>> v5.9-rc4 } else if (strstr(kcontrol->id.name, "Capture Stereo To Mono")) { i2s->stereo_to_mono[I2S_TX_PATH] = value; } else if (strstr(kcontrol->id.name, "Capture Mono To Stereo")) { @@ -385,6 +453,37 @@ static int tegra210_i2s_put_control(struct snd_kcontrol *kcontrol, return 0; } +<<<<<<< HEAD +static const char * const tegra210_i2s_format_text[] = { + "None", + "16", + "32", +}; + +static const unsigned int tegra210_cif_fmt[] = { + 0, + TEGRA_ACIF_BITS_16, + TEGRA_ACIF_BITS_32, +}; + +static const unsigned int tegra210_i2s_bit_fmt[] = { + 0, + I2S_BITS_16, + I2S_BITS_32, +}; + +static const unsigned int tegra210_i2s_sample_size[] = { + 0, + 16, + 32, +}; + +static const struct soc_enum tegra210_i2s_format_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_format_text), + tegra210_i2s_format_text); + +======= +>>>>>>> v5.9-rc4 static int tegra210_i2s_set_timing_params(struct device *dev, unsigned int sample_size, unsigned int srate, @@ -479,6 +578,25 @@ static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream, cif_conf.audio_bits = TEGRA_ACIF_BITS_16; cif_conf.client_bits = TEGRA_ACIF_BITS_16; break; +<<<<<<< HEAD + case SNDRV_PCM_FORMAT_S24_LE: + val = I2S_BITS_24; + + /* + * I2S bit clock is derived from PLLA_OUT0 and size of + * 24 bits results in fractional value and the clock + * is not accurate with this. To have integer clock + * division below is used. It means there are additional + * bit clocks (8 cycles) which are ignored. Codec picks + * up data for other channel when LRCK signal toggles. + */ + sample_size = 32; + + cif_conf.audio_bits = TEGRA_ACIF_BITS_24; + cif_conf.client_bits = TEGRA_ACIF_BITS_24; + break; +======= +>>>>>>> v5.9-rc4 case SNDRV_PCM_FORMAT_S32_LE: val = I2S_BITS_32; sample_size = 32; @@ -487,7 +605,19 @@ static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream, break; default: dev_err(dev, "unsupported format!\n"); +<<<<<<< HEAD + return -ENOTSUPP; + } + + if (i2s->client_fmt_override) { + val = tegra210_i2s_bit_fmt[i2s->client_fmt_override]; + sample_size = + tegra210_i2s_sample_size[i2s->client_fmt_override]; + cif_conf.client_bits = + tegra210_cif_fmt[i2s->client_fmt_override]; +======= return -EOPNOTSUPP; +>>>>>>> v5.9-rc4 } /* Program sample size */ @@ -496,6 +626,31 @@ static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream, srate = params_rate(params); +<<<<<<< HEAD + /* Override rate, channel and audio bit params as applicable */ + if (i2s->srate_override) + srate = i2s->srate_override; + + /* + * For playback I2S RX-CIF and for capture TX-CIF is used. + * With reference to AHUB, for I2S, SNDRV_PCM_STREAM_CAPTURE stream is + * actually for playback. + */ + path = (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ? + I2S_RX_PATH : I2S_TX_PATH; + + if (i2s->audio_ch_override[path]) + cif_conf.audio_ch = i2s->audio_ch_override[path]; + + if (i2s->client_ch_override) + cif_conf.client_ch = i2s->client_ch_override; + + if (i2s->audio_fmt_override[path]) + cif_conf.audio_bits = + tegra210_cif_fmt[i2s->audio_fmt_override[path]]; + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { +======= /* For playback I2S RX-CIF and for capture TX-CIF is used */ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) path = I2S_RX_PATH; @@ -503,6 +658,7 @@ static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream, path = I2S_TX_PATH; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { +>>>>>>> v5.9-rc4 unsigned int max_th; /* FIFO threshold in terms of frames */ @@ -534,51 +690,124 @@ static const struct snd_soc_dai_ops tegra210_i2s_dai_ops = { .set_tdm_slot = tegra210_i2s_set_tdm_slot, }; +<<<<<<< HEAD +/* + * Three DAIs are exposed + * 1. "CIF" DAI for connecting with XBAR + * 2. "DAP" DAI for connecting with CODEC + * 3. "DUMMY" can be used when no external codec connection is + * available. In such case "DAP" is connected with "DUMMY". + * Order of these DAIs should not be changed, since DAI links in DT refer + * to these DAIs depending on the index. + */ +static struct snd_soc_dai_driver tegra210_i2s_dais[] = { + { + .name = "CIF", + .playback = { + .stream_name = "CIF Receive", +======= static struct snd_soc_dai_driver tegra210_i2s_dais[] = { { .name = "I2S-CIF", .playback = { .stream_name = "CIF-Playback", +>>>>>>> v5.9-rc4 .channels_min = 1, .channels_max = 16, .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | +<<<<<<< HEAD + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + .capture = { + .stream_name = "CIF Transmit", +======= SNDRV_PCM_FMTBIT_S32_LE, }, .capture = { .stream_name = "CIF-Capture", +>>>>>>> v5.9-rc4 .channels_min = 1, .channels_max = 16, .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | +<<<<<<< HEAD + SNDRV_PCM_FMTBIT_S24_LE | +======= +>>>>>>> v5.9-rc4 SNDRV_PCM_FMTBIT_S32_LE, }, }, { +<<<<<<< HEAD + .name = "DAP", + .playback = { + .stream_name = "DAP Receive", +======= .name = "I2S-DAP", .playback = { .stream_name = "DAP-Playback", +>>>>>>> v5.9-rc4 .channels_min = 1, .channels_max = 16, .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | +<<<<<<< HEAD + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + .capture = { + .stream_name = "DAP Transmit", +======= SNDRV_PCM_FMTBIT_S32_LE, }, .capture = { .stream_name = "DAP-Capture", +>>>>>>> v5.9-rc4 .channels_min = 1, .channels_max = 16, .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | +<<<<<<< HEAD + SNDRV_PCM_FMTBIT_S24_LE | +======= +>>>>>>> v5.9-rc4 SNDRV_PCM_FMTBIT_S32_LE, }, .ops = &tegra210_i2s_dai_ops, .symmetric_rates = 1, }, +<<<<<<< HEAD + { + .name = "DUMMY", + .playback = { + .stream_name = "Dummy Playback", + .channels_min = 1, + .channels_max = 16, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + .capture = { + .stream_name = "Dummy Capture", + .channels_min = 1, + .channels_max = 16, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + }, +======= +>>>>>>> v5.9-rc4 }; static const char * const tegra210_i2s_stereo_conv_text[] = { @@ -586,7 +815,11 @@ static const char * const tegra210_i2s_stereo_conv_text[] = { }; static const char * const tegra210_i2s_mono_conv_text[] = { +<<<<<<< HEAD + "ZERO", "COPY", +======= "Zero", "Copy", +>>>>>>> v5.9-rc4 }; static const struct soc_enum tegra210_i2s_mono_conv_enum = @@ -602,6 +835,23 @@ static const struct snd_kcontrol_new tegra210_i2s_controls[] = { tegra210_i2s_put_control), SOC_SINGLE_EXT("FSYNC Width", 0, 0, 255, 0, tegra210_i2s_get_control, tegra210_i2s_put_control), +<<<<<<< HEAD + SOC_SINGLE_EXT("Sample Rate", 0, 0, 192000, 0, tegra210_i2s_get_control, + tegra210_i2s_put_control), + SOC_ENUM_EXT("Playback Audio Bit Format", tegra210_i2s_format_enum, + tegra210_i2s_get_control, tegra210_i2s_put_control), + SOC_ENUM_EXT("Capture Audio Bit Format", tegra210_i2s_format_enum, + tegra210_i2s_get_control, tegra210_i2s_put_control), + SOC_ENUM_EXT("Client Bit Format", tegra210_i2s_format_enum, + tegra210_i2s_get_control, tegra210_i2s_put_control), + SOC_SINGLE_EXT("Playback Audio Channels", 0, 0, 16, 0, + tegra210_i2s_get_control, tegra210_i2s_put_control), + SOC_SINGLE_EXT("Capture Audio Channels", 0, 0, 16, 0, + tegra210_i2s_get_control, tegra210_i2s_put_control), + SOC_SINGLE_EXT("Client Channels", 0, 0, 16, 0, + tegra210_i2s_get_control, tegra210_i2s_put_control), +======= +>>>>>>> v5.9-rc4 SOC_ENUM_EXT("Capture Stereo To Mono", tegra210_i2s_stereo_conv_enum, tegra210_i2s_get_control, tegra210_i2s_put_control), SOC_ENUM_EXT("Capture Mono To Stereo", tegra210_i2s_mono_conv_enum, @@ -617,6 +867,39 @@ static const struct snd_kcontrol_new tegra210_i2s_controls[] = { }; static const struct snd_soc_dapm_widget tegra210_i2s_widgets[] = { +<<<<<<< HEAD + SND_SOC_DAPM_AIF_IN("CIF RX", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("CIF TX", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN_E("DAP RX", NULL, 0, TEGRA210_I2S_TX_ENABLE, + 0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU), + SND_SOC_DAPM_AIF_OUT_E("DAP TX", NULL, 0, TEGRA210_I2S_RX_ENABLE, + 0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU), + SND_SOC_DAPM_MIC("Dummy Input", NULL), + SND_SOC_DAPM_SPK("Dummy Output", NULL), +}; + +static const struct snd_soc_dapm_route tegra210_i2s_routes[] = { + { "CIF RX", NULL, "CIF Receive" }, + { "DAP TX", NULL, "CIF RX" }, + { "DAP Transmit", NULL, "DAP TX" }, + + { "DAP RX", NULL, "DAP Receive" }, + { "CIF TX", NULL, "DAP RX" }, + { "CIF Transmit", NULL, "CIF TX" }, + + { "Dummy Capture", NULL, "Dummy Input" }, + { "Dummy Output", NULL, "Dummy Playback" }, +}; + +static const struct snd_soc_component_driver tegra210_i2s_cmpnt = { + .dapm_widgets = tegra210_i2s_widgets, + .num_dapm_widgets = ARRAY_SIZE(tegra210_i2s_widgets), + .dapm_routes = tegra210_i2s_routes, + .num_dapm_routes = ARRAY_SIZE(tegra210_i2s_routes), + .controls = tegra210_i2s_controls, + .num_controls = ARRAY_SIZE(tegra210_i2s_controls), + .non_legacy_dai_naming = 1, +======= SND_SOC_DAPM_AIF_IN_E("RX", NULL, 0, TEGRA210_I2S_RX_ENABLE, 0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU), SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, TEGRA210_I2S_TX_ENABLE, @@ -648,6 +931,7 @@ static const struct snd_soc_component_driver tegra210_i2s_cmpnt = { .controls = tegra210_i2s_controls, .num_controls = ARRAY_SIZE(tegra210_i2s_controls), .non_legacy_dai_naming = 1, +>>>>>>> v5.9-rc4 }; static bool tegra210_i2s_wr_reg(struct device *dev, unsigned int reg) @@ -717,6 +1001,15 @@ static const struct regmap_config tegra210_i2s_regmap_config = { .cache_type = REGCACHE_FLAT, }; +<<<<<<< HEAD +static const struct of_device_id tegra210_i2s_of_match[] = { + { .compatible = "nvidia,tegra210-i2s" }, + {}, +}; +MODULE_DEVICE_TABLE(of, tegra210_i2s_of_match); + +======= +>>>>>>> v5.9-rc4 static int tegra210_i2s_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -790,12 +1083,15 @@ static const struct dev_pm_ops tegra210_i2s_pm_ops = { pm_runtime_force_resume) }; +<<<<<<< HEAD +======= static const struct of_device_id tegra210_i2s_of_match[] = { { .compatible = "nvidia,tegra210-i2s" }, {}, }; MODULE_DEVICE_TABLE(of, tegra210_i2s_of_match); +>>>>>>> v5.9-rc4 static struct platform_driver tegra210_i2s_driver = { .driver = { .name = "tegra210-i2s", diff --git a/sound/soc/tegra/tegra210_i2s.h b/sound/soc/tegra/tegra210_i2s.h index 030d70c4..d1c7e94e 100644 --- a/sound/soc/tegra/tegra210_i2s.h +++ b/sound/soc/tegra/tegra210_i2s.h @@ -2,7 +2,11 @@ /* * tegra210_i2s.h - Definitions for Tegra210 I2S driver * +<<<<<<< HEAD + * Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved. +======= * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. +>>>>>>> v5.9-rc4 * */ @@ -87,6 +91,10 @@ #define I2S_BITS_8 1 #define I2S_BITS_16 3 +<<<<<<< HEAD +#define I2S_BITS_24 5 +======= +>>>>>>> v5.9-rc4 #define I2S_BITS_32 7 #define I2S_CTRL_BIT_SIZE_MASK 0x7 @@ -114,6 +122,15 @@ struct tegra210_i2s { struct regmap *regmap; unsigned int stereo_to_mono[I2S_PATHS]; unsigned int mono_to_stereo[I2S_PATHS]; +<<<<<<< HEAD + unsigned int audio_ch_override[I2S_PATHS]; + unsigned int audio_fmt_override[I2S_PATHS]; + /* Client overrides are common for TX and RX paths */ + unsigned int client_ch_override; + unsigned int client_fmt_override; + unsigned int srate_override; +======= +>>>>>>> v5.9-rc4 unsigned int dai_fmt; unsigned int fsync_width; unsigned int bclk_ratio;