From 47917521d4a6a3cfaeccf72df2d7fa77e3bcf285 Mon Sep 17 00:00:00 2001
From: fraunak <fraunak@nvidia.com>
Date: Tue, 7 Mar 2023 22:00:46 +0000
Subject: [PATCH] kernel-oot: update pm register offsets

Added t264 specific pdata struct to
use r5_ctrl and pwr_status registers
values.

Jira CAMERASW-11038

Change-Id: I4ae6b3ffee48eff61a6b7a7309c251c38d68bf30
Signed-off-by: fraunak <fraunak@nvidia.com>
---
 .../tegra/rtcpu/tegra-camera-rtcpu-base.c     | 46 +++++++++++++++++--
 1 file changed, 41 insertions(+), 5 deletions(-)

diff --git a/drivers/platform/tegra/rtcpu/tegra-camera-rtcpu-base.c b/drivers/platform/tegra/rtcpu/tegra-camera-rtcpu-base.c
index 77c50792..0e403d1b 100644
--- a/drivers/platform/tegra/rtcpu/tegra-camera-rtcpu-base.c
+++ b/drivers/platform/tegra/rtcpu/tegra-camera-rtcpu-base.c
@@ -49,13 +49,13 @@ struct tegra_cam_rtcpu_pdata {
 	int (*wait_for_idle)(struct device *);
 	const char * const *reset_names;
 	const char * const *reg_names;
+	u32 (*pm_r5_ctrl)(void);
+	u32 (*pm_pwr_status)(void);
 };
 
 /* Register specifics */
 #define TEGRA_APS_FRSC_SC_CTL_0			0x0
 #define TEGRA_APS_FRSC_SC_MODEIN_0		0x14
-#define TEGRA_PM_R5_CTRL_0			0x40
-#define TEGRA_PM_PWR_STATUS_0			0x20
 
 #define TEGRA_R5R_SC_DISABLE			0x5
 #define TEGRA_FN_MODEIN				0x29527
@@ -82,6 +82,16 @@ static const char * const rce_reg_names[] = {
 	NULL,
 };
 
+static u32 rce_pm_r5_ctrl(void)
+{
+	return 0x40;
+}
+
+static u32 rce_pm_pwr_status(void)
+{
+	return 0x20;
+}
+
 static const struct tegra_cam_rtcpu_pdata rce_pdata = {
 	.name = "rce",
 	.wait_for_idle = tegra_rce_cam_wait_for_idle,
@@ -89,6 +99,29 @@ static const struct tegra_cam_rtcpu_pdata rce_pdata = {
 	.deassert_resets = tegra_rce_cam_deassert_resets,
 	.reset_names = rce_reset_names,
 	.reg_names = rce_reg_names,
+	.pm_r5_ctrl = rce_pm_r5_ctrl,
+	.pm_pwr_status = rce_pm_pwr_status,
+};
+
+static u32 t264_rce_pm_r5_ctrl(void)
+{
+	return 0x3008;
+}
+
+static u32 t264_rce_pm_pwr_status(void)
+{
+	return 0x5004;
+}
+
+static const struct tegra_cam_rtcpu_pdata t264_rce_pdata = {
+	.name = "t264_rce",
+	.wait_for_idle = tegra_rce_cam_wait_for_idle,
+	.assert_resets = tegra_rce_cam_assert_resets,
+	.deassert_resets = tegra_rce_cam_deassert_resets,
+	.reset_names = rce_reset_names,
+	.reg_names = rce_reg_names,
+	.pm_r5_ctrl = t264_rce_pm_r5_ctrl,
+	.pm_pwr_status = t264_rce_pm_pwr_status,
 };
 
 #define NV(p) "nvidia," #p
@@ -372,14 +405,14 @@ static void tegra_camrtc_set_fwloaddone(struct device *dev, bool fwloaddone)
 	struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev);
 
 	if (rtcpu->pm_base != NULL) {
-		u32 val = readl(rtcpu->pm_base + TEGRA_PM_R5_CTRL_0);
+		u32 val = readl(rtcpu->pm_base + rtcpu->pdata->pm_r5_ctrl());
 
 		if (fwloaddone)
 			val |= TEGRA_PM_FWLOADDONE;
 		else
 			val &= ~TEGRA_PM_FWLOADDONE;
 
-		writel(val, rtcpu->pm_base + TEGRA_PM_R5_CTRL_0);
+		writel(val, rtcpu->pm_base + rtcpu->pdata->pm_r5_ctrl());
 	}
 }
 
@@ -394,7 +427,7 @@ static int tegra_rce_cam_wait_for_idle(struct device *dev)
 
 	/* Poll for WFI assert.*/
 	for (;;) {
-		u32 val = readl(rtcpu->pm_base + TEGRA_PM_PWR_STATUS_0);
+		u32 val = readl(rtcpu->pm_base + rtcpu->pdata->pm_pwr_status());
 
 		if ((val & TEGRA_PM_WFIPIPESTOPPED) == 0)
 			break;
@@ -1029,6 +1062,9 @@ static const struct of_device_id tegra_cam_rtcpu_of_match[] = {
 	{
 		.compatible = NV(tegra194-rce), .data = &rce_pdata
 	},
+	{
+		.compatible = NV(tegra264-rce), .data = &t264_rce_pdata
+	},
 	{ },
 };
 MODULE_DEVICE_TABLE(of, tegra_cam_rtcpu_of_match);