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ASoC: tegra: Add MVC Bypass support

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- Add "MVC Bypass" kcontrol to enable MVC Bypass
  mode.
- The change is required to verify MVC bypass mode
  during bring up.

Bug 200683609

Change-Id: Ic0f2c947fa2e9bd6e9b429b86ff35e053775ec80
Signed-off-by: sheetal <sheetal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.10/+/2546568
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Viswanath L <viswanathl@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
sheetal
2021-06-17 15:46:21 +05:30
committed by Sameer Pujar
parent 9e4c08a7c2
commit 47e3d32fc0
2 changed files with 15 additions and 0 deletions
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4
sound/soc/tegra/tegra210_mvc.h
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@@ -81,6 +81,9 @@
#define TEGRA210_MVC_INIT_VOL_DEFAULT_POLY 0x01000000
#define TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR 0x00000000
#define TEGRA210_MVC_BYPASS_MODE_SHIFT 31
#define TEGRA210_MVC_BYPASS_MODE_MASK (1 << TEGRA210_MVC_BYPASS_MODE_SHIFT)
/* Fields in TEGRA210_MVC ram ctrl */
#define TEGRA210_MVC_CFG_RAM_CTRL_RW_SHIFT 14
#define TEGRA210_MVC_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_MVC_CFG_RAM_CTRL_RW_SHIFT)
@@ -113,6 +116,7 @@ struct tegra210_mvc {
unsigned int cif_channels;
unsigned int audio_bits;
unsigned int format_in;
bool bypass_mode;
};
#endif