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ufs: tegra: Set MPHY EQ timeout

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Set MPHY EQ timeout as per the HW recommendations

Bug 5136701

Change-Id: Icf8012044f13006b76921e8f783c246d2953b858
Signed-off-by: Aniruddha Rao <anrao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3373643
(cherry picked from commit b918e90ad2c7dfb649fd98a9c65d35ff70a47d0f)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3407950
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
This commit is contained in:
Aniruddha Rao
2025-05-30 09:32:31 +00:00
committed by Jon Hunter
parent 31cf676050
commit 49ebbfc3ed
2 changed files with 5 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/scsi/ufs/ufs-tegra-common.c
View File

@@ -1284,8 +1284,10 @@ static int ufs_tegra_eq_timeout(struct ufs_tegra_host *ufs_tegra)
{
struct device *dev = ufs_tegra->hba->dev;
int err;
uint32_t mphy_eq_timeout = (ufs_tegra->soc->chip_id >= TEGRA264) ?
MPHY_EQ_TIMEOUT_T264 : MPHY_EQ_TIMEOUT;
mphy_writel(ufs_tegra->mphy_l0_base, MPHY_EQ_TIMEOUT,
mphy_writel(ufs_tegra->mphy_l0_base, mphy_eq_timeout,
MPHY_RX_APB_VENDOR3B_0_T234);
mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234);
err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, MPHY_RX_APB_VENDOR2_0_T234);
@@ -1294,7 +1296,7 @@ static int ufs_tegra_eq_timeout(struct ufs_tegra_host *ufs_tegra)
goto end;
}
if (ufs_tegra->x2config) {
mphy_writel(ufs_tegra->mphy_l1_base, MPHY_EQ_TIMEOUT,
mphy_writel(ufs_tegra->mphy_l1_base, mphy_eq_timeout,
MPHY_RX_APB_VENDOR3B_0_T234);
mphy_update(ufs_tegra->mphy_l1_base, MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234);
err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, MPHY_RX_APB_VENDOR2_0_T234);

1
drivers/scsi/ufs/ufs-tegra.h
View File

@@ -86,6 +86,7 @@
#define MPHY_PWR_CHANGE_CLK_BOOST 0x0017
#define MPHY_EQ_TIMEOUT 0x1AADB5
#define MPHY_EQ_TIMEOUT_T264 0xFFFFFFFF
#define MPHY_GO_BIT 1U
#define MPHY_RX_APB_CAPABILITY_88_8B_0 0x88