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platform: tegra: Fix MC-HWPM driver
Simplify the MC-HWPM driver and fix the hang seen during probe of it. These changes are made to scale the driver for future SOCs as well. The hang is seen because MC registers are accessed in function get_platform_dram_num_channels() before the MC aperture is io-mapped. Bug 4235766 Change-Id: I3c8f9229898ac459c616aca0ef400a8b4c16e66a Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2963195 Reviewed-by: Ketan Patil <ketanp@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Ashish Mhetre
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4a11641e79
@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#define pr_fmt(fmt) "mc-hwpm: " fmt
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@@ -11,235 +11,114 @@
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <soc/tegra/fuse.h>
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#include "soc/tegra/mc.h"
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0 0xdf8
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#define CH_MASK 0xFFFF /* Change bit counting if this mask changes */
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#define MC_MAX_CHANNELS 16
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/* Total channels = Broadcast channel + MC_MAX_CHANNELS */
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#define TOTAL_CHANNELS (1 + MC_MAX_CHANNELS)
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static void __iomem *memctlr_regs[TOTAL_CHANNELS];
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static u32 platform_ch_nums;
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/* Broadcast Channel + 16 MC Channels */
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#define MAX_MC_CHANNELS 17
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static bool is_tegra_safety_build(void)
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{
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#ifdef CONFIG_OF
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return of_property_read_bool(of_chosen,
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"nvidia,tegra-safety-build");
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#else
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return false;
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#endif
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}
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/**
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* Read from the MC.
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*
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* @idx The MC channel to read from.
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* @reg The offset of the register to read.
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*
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* Read from the specified MC channel: 0 -> Broadcast channel/ Global channel
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* 1 -> MC0, 16 -> MC16, etc. If @idx
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* corresponds to a non-existent channel then 0 is returned.
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*/
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static u32 memctrl_readl(u32 chnl_no, u32 reg)
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{
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static bool warned;
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static struct tegra_soc_hwpm_ip_ops hwpm_ip_ops;
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if (is_tegra_safety_build()) {
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if (!warned) {
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pr_warn("WARNING: VM isn't allowed to read MC register space in Safety Build");
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warned = true;
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}
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return 0xffff;
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}
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if (chnl_no > platform_ch_nums)
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return 0;
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return readl(memctlr_regs[chnl_no] + reg);
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}
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struct tegra_mc_hwpm {
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struct device *dev;
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void __iomem **ch_regs;
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u32 no_ch;
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u64 base_addr;
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};
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/**
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* Write to the MC.
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*
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* @idx The MC channel to write to.
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* @val Value to write.
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* @reg The offset of the register to write.
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*
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* Write to the specified MC channel: 0 -> MC0, 1 -> MC1, etc. For writes there
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* is a special channel, %MC_BROADCAST_CHANNEL, which writes to all channels. If
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* @idx corresponds to a non-existent channel then the write is dropped.
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* ch_no == 0 = Broadcast Channel
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* ch_no == 1 = MC0
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* ch_no == 2 = MC1
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* .
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* .
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* ch_no == 16 = MC15
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*/
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static void memctrl_writel(u32 chnl_no, u32 val, u32 reg)
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static u32 mc_readl(struct tegra_mc_hwpm *mc, u32 ch_no, u32 reg)
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{
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static bool warned;
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if (is_tegra_safety_build()) {
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if (!warned) {
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pr_warn("WARNING: VM isn't allowed to write into MC register space in Safety Build");
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warned = true;
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}
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return;
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}
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if (chnl_no > platform_ch_nums) {
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pr_err("Incorrect channel number: %u\n", chnl_no);
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return;
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}
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writel(val, memctlr_regs[chnl_no] + reg);
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return readl(mc->ch_regs[ch_no] + reg);
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}
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static u32 get_platform_dram_num_channels(void)
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static void mc_writel(struct tegra_mc_hwpm *mc, u32 ch_no, u32 val, u32 reg)
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{
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u32 plt_ch_nums = 0;
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u32 ch;
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ch = memctrl_readl(0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0) & CH_MASK;
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while (ch) {
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if (ch & 1)
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plt_ch_nums++;
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ch >>= 1;
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}
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return plt_ch_nums;
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writel(val, mc->ch_regs[ch_no] + reg);
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}
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static int tegra_mc_hwpm_reg_op(void *ip_dev,
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enum tegra_soc_hwpm_ip_reg_op reg_op,
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u32 inst_element_index, u64 reg_offset, u32 *reg_data)
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{
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if (reg_offset > 0x10000) {
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pr_err("Incorrect reg offset: %llu\n", reg_offset);
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return -EPERM;
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struct device *dev = (struct device *)ip_dev;
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struct tegra_mc_hwpm *mc;
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mc = dev_get_drvdata(dev);
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if (!mc) {
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pr_err("tegra-mc-hwpm: Invalid device\n");
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return -ENODEV;
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}
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if (inst_element_index > platform_ch_nums) {
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pr_err("Incorrect channel number: %u\n", inst_element_index);
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return -EPERM;
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if (inst_element_index >= mc->no_ch) {
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dev_err(mc->dev, "Incorrect channel number: %u\n", inst_element_index);
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return -EINVAL;
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}
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if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_READ)
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*reg_data = memctrl_readl(inst_element_index, (u32)reg_offset);
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else if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_WRITE)
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memctrl_writel(inst_element_index, *reg_data, (u32)reg_offset);
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if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_READ) {
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*reg_data = mc_readl(mc, inst_element_index, (u32)reg_offset);
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} else if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_WRITE) {
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mc_writel(mc, inst_element_index, *reg_data, (u32)reg_offset);
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} else {
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dev_err(mc->dev, "Invalid operation\n");
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Map an MC register space. Each MC has a set of register ranges which must
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* be parsed. The first starting address in the set of ranges is returned as
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* it is expected that the DT file has the register ranges in ascending
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* order.
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*
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* device 0 = global channel.
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* device n = specific channel device-1, e.g device = 1 ==> channel 0.
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*/
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static void __iomem *tegra_mc_hwpm_map_regs(struct platform_device *pdev, u32 device)
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{
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struct resource res;
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const void *prop;
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void __iomem *regs;
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void __iomem *regs_start = NULL;
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u32 reg_ranges;
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u32 i, start;
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prop = of_get_property(pdev->dev.of_node, "reg-ranges", NULL);
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if (!prop) {
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pr_err("Failed to get MC MMIO region\n");
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pr_err(" device = %d: missing reg-ranges\n", device);
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return NULL;
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}
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reg_ranges = be32_to_cpup(prop);
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start = device * reg_ranges;
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for (i = 0; i < reg_ranges; i++) {
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regs = of_iomap(pdev->dev.of_node, start + i);
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if (!regs) {
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pr_err("Failed to get MC MMIO region\n");
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pr_err(" device = %d, range = %u\n", device, i);
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return NULL;
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}
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if (i == 0)
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regs_start = regs;
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}
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if (of_address_to_resource(pdev->dev.of_node, start, &res))
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return NULL;
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pr_debug("mapped MMIO address: 0x%p -> 0x%lx\n",
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regs_start, (unsigned long)res.start);
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return regs_start;
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}
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static struct tegra_soc_hwpm_ip_ops hwpm_ip_ops;
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static const struct of_device_id mc_hwpm_of_ids[] = {
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{ .compatible = "nvidia,tegra-t23x-mc-hwpm" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, mc_hwpm_of_ids);
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/*
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* MC driver init.
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*/
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static int tegra_mc_hwpm_hwpm_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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u32 dram_channels;
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const void *prop;
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int i;
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struct tegra_mc_hwpm *mc;
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struct resource *res;
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u32 i;
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if (!pdev->dev.of_node)
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return -EINVAL;
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match = of_match_device(mc_hwpm_of_ids, &pdev->dev);
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if (!match) {
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pr_err("Missing DT entry!\n");
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return -EINVAL;
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}
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/*
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* Channel count.
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*/
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prop = of_get_property(pdev->dev.of_node, "channels", NULL);
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if (!prop)
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dram_channels = 1;
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else
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dram_channels = be32_to_cpup(prop);
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platform_ch_nums = get_platform_dram_num_channels();
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if (platform_ch_nums > dram_channels) {
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pr_err("channel mismatch error: max_soc_channels: %u platform_channels %u\n",
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dram_channels,
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platform_ch_nums);
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return -EINVAL;
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}
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/*
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* Store reg mapping for broadcast channel
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*/
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memctlr_regs[0] = tegra_mc_hwpm_map_regs(pdev, 0);
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if (!memctlr_regs[0])
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mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
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if (!mc)
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return -ENOMEM;
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/* Populate the rest of the channels... */
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if (platform_ch_nums > 1) {
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for (i = 1; i <= platform_ch_nums; i++) {
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memctlr_regs[i] = tegra_mc_hwpm_map_regs(pdev, i);
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if (!memctlr_regs[i])
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return -ENOMEM;
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platform_set_drvdata(pdev, mc);
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mc->dev = &pdev->dev;
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mc->no_ch = MAX_MC_CHANNELS;
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mc->ch_regs = devm_kcalloc(mc->dev, mc->no_ch, sizeof(*mc->ch_regs),
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GFP_KERNEL);
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if (!mc->ch_regs)
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return -ENOMEM;
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for (i = 0; i < mc->no_ch; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res) {
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dev_err(mc->dev, "Missing MC channels in device tree\n");
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return -ENODEV;
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}
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mc->ch_regs[i] = devm_ioremap(mc->dev, res->start, resource_size(res));
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if (IS_ERR(mc->ch_regs[i])) {
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dev_err(mc->dev, "Failed to ioremap MC channels aperture\n");
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return PTR_ERR(mc->ch_regs[i]);
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}
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if (i == 0)
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mc->base_addr = res->start;
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}
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hwpm_ip_ops.ip_dev = (void *)pdev;
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hwpm_ip_ops.ip_dev = (void *)mc->dev;
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hwpm_ip_ops.resource_enum = TEGRA_SOC_HWPM_RESOURCE_MSS_CHANNEL;
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hwpm_ip_ops.ip_base_address = pdev->resource[0].start;
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hwpm_ip_ops.ip_base_address = mc->base_addr;
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hwpm_ip_ops.hwpm_ip_reg_op = &tegra_mc_hwpm_reg_op;
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tegra_soc_hwpm_ip_register(&hwpm_ip_ops);
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@@ -248,9 +127,18 @@ static int tegra_mc_hwpm_hwpm_probe(struct platform_device *pdev)
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static int tegra_mc_hwpm_remove(struct platform_device *pdev)
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{
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hwpm_ip_ops.ip_dev = (void *)pdev;
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struct device *dev = &pdev->dev;
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struct tegra_mc_hwpm *mc;
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mc = dev_get_drvdata(dev);
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if (!mc) {
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pr_err("tegra-mc-hwpm: Invalid device\n");
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return -ENODEV;
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}
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hwpm_ip_ops.ip_dev = (void *)mc->dev;
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hwpm_ip_ops.resource_enum = TEGRA_SOC_HWPM_RESOURCE_MSS_CHANNEL;
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hwpm_ip_ops.ip_base_address = pdev->resource[0].start;
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hwpm_ip_ops.ip_base_address = mc->base_addr;
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hwpm_ip_ops.hwpm_ip_reg_op = NULL;
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tegra_soc_hwpm_ip_unregister(&hwpm_ip_ops);
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@@ -270,21 +158,17 @@ static struct platform_driver mc_hwpm_driver = {
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static int __init tegra_mc_hwpm_init(void)
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{
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int ret;
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ret = platform_driver_register(&mc_hwpm_driver);
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if (ret)
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return ret;
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return 0;
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return platform_driver_register(&mc_hwpm_driver);
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}
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module_init(tegra_mc_hwpm_init);
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static void __exit tegra_mc_hwpm_fini(void)
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static void __exit tegra_mc_hwpm_exit(void)
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{
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platform_driver_unregister(&mc_hwpm_driver);
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}
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module_exit(tegra_mc_hwpm_fini);
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module_exit(tegra_mc_hwpm_exit);
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MODULE_DESCRIPTION("MC Hardware Performace Monitor driver");
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MODULE_AUTHOR("Puneet Saxena <puneets@nvidia.com>");
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MODULE_AUTHOR("Ashish Mhetre <amhetre@nvidia.com>");
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MODULE_DESCRIPTION("MC Hardware Performace Monitor Interface driver");
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MODULE_LICENSE("GPL v2");
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