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drivers: misc: add nvscic2c-pcie in OOT
nvscic2c enables xfer between two SoC connected over PCIe. nvscic2c already available with K5.10 Major changes in nvscic2c-pcie for K5.15: Integrate with upstream PCIe endpoint function changes. Allocate new IOVA domain to be used for empty IOVA allocation. This IOVA range would be used in iommu_map() to map physical backing with IOMMU domain attached in PCIe device. Migrate from nvhost to host1x and tegra-drm interfaces. Bug 3739487 Jira C2C-826 Jira C2C-830 Change-Id: Ic4d8ac680921807fb17247855ca7037623681cb7 Signed-off-by: dbadgaiyan <dbadgaiyan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2810806 Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com> Reviewed-by: Arihant Jejani <ajejani@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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269
include/uapi/misc/nvscic2c-pcie-ioctl.h
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269
include/uapi/misc/nvscic2c-pcie-ioctl.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __UAPI_NVSCIC2C_PCIE_IOCTL_H__
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#define __UAPI_NVSCIC2C_PCIE_IOCTL_H__
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#if !defined(__KERNEL__)
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#define __user
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#endif
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#define MAX_NAME_SZ (32)
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/* Link status between the two peers - encapsulates PCIe link also.*/
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enum nvscic2c_pcie_link {
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NVSCIC2C_PCIE_LINK_DOWN = 0,
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NVSCIC2C_PCIE_LINK_UP,
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};
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/**
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* stream extensions - object type.
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*/
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enum nvscic2c_pcie_obj_type {
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NVSCIC2C_PCIE_OBJ_TYPE_INVALID = 0,
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/* local NvRmMemHandle(tegra) /NvRmHandle(x86) obj. */
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NVSCIC2C_PCIE_OBJ_TYPE_SOURCE_MEM,
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/* Exported NvRmMemHandle(tegra) /NvRmHandle(x86) obj. */
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NVSCIC2C_PCIE_OBJ_TYPE_TARGET_MEM,
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/* local NvRmHost1xSyncpoint(tegra) /GPU Semaphore(x86) obj. */
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NVSCIC2C_PCIE_OBJ_TYPE_LOCAL_SYNC,
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/* Exported NvRmHost1xSyncpoint(tegra) /GPU Semaphore(x86) obj. */
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NVSCIC2C_PCIE_OBJ_TYPE_REMOTE_SYNC,
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/* (virtual) objects imported from remote SoC. */
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NVSCIC2C_PCIE_OBJ_TYPE_IMPORT,
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NVSCIC2C_PCIE_OBJ_TYPE_MAXIMUM,
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};
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/**
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* PCIe aperture and PCIe shared memory
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* are divided in different C2C endpoints.
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* Data structure represents endpoint's
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* physical address and size.
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*/
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struct nvscic2c_pcie_endpoint_mem_info {
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/* would be one of the enum nvscic2c_mem_type.*/
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__u32 offset;
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/* size of this memory type device would like user-space to map.*/
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__u32 size;
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};
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/**
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* NvSciIpc endpoint information relayed to UMD. This information
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* is per endpoint which shall allow UMD to mmap the endpoint's
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* send, recv and pcie link area in user-space.
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*/
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struct nvscic2c_pcie_endpoint_info {
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__u32 nframes;
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__u32 frame_size;
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struct nvscic2c_pcie_endpoint_mem_info peer;
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struct nvscic2c_pcie_endpoint_mem_info self;
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struct nvscic2c_pcie_endpoint_mem_info link;
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};
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/**
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* stream extensions - Pin/Map.
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*/
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struct nvscic2c_pcie_map_in_arg {
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/*
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* Mem obj - NvRmMemHandle FD. Sync obj - NvRmHost1xSyncpointHandle FD.
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*/
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__s32 fd;
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/*
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* Mem obj - padding. Sync obj - Syncpoint Id.
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*/
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__u32 id;
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};
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struct nvscic2c_pcie_map_out_arg {
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__s32 handle;
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__u32 pad;
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};
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struct nvscic2c_pcie_map_obj_args {
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__s32 obj_type;
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__u32 pad;
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struct nvscic2c_pcie_map_in_arg in;
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struct nvscic2c_pcie_map_out_arg out;
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};
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/**
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* stream extensions - Export.
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*/
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struct nvscic2c_pcie_export_in_arg {
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__s32 handle;
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__u32 pad;
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};
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struct nvscic2c_pcie_export_out_arg {
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__u64 desc;
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};
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struct nvscic2c_pcie_export_obj_args {
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__s32 obj_type;
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__u32 pad;
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struct nvscic2c_pcie_export_in_arg in;
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struct nvscic2c_pcie_export_out_arg out;
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};
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/**
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* stream extensions - Import.
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*/
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struct nvscic2c_pcie_import_in_arg {
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__u64 desc;
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};
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struct nvscic2c_pcie_import_out_arg {
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__s32 handle;
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__u32 pad;
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};
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struct nvscic2c_pcie_import_obj_args {
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__s32 obj_type;
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__u32 pad;
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struct nvscic2c_pcie_import_in_arg in;
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struct nvscic2c_pcie_import_out_arg out;
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};
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/**
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* stream extensions - Free Pinned Or Imported objects.
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*/
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struct nvscic2c_pcie_free_obj_args {
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__s32 obj_type;
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__s32 handle;
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};
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/**
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* stream extensions - one transfer/copy unit.
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*/
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struct nvscic2c_pcie_flush_range {
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__s32 src_handle;
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__s32 dst_handle;
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__u64 offset;
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__u64 size;
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};
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/*
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* @local_post_fences: user memory atleast of size:
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* num_local_post_fences * sizeof(__s32) - local sync handles
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*
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* @remote_post_fences: user memory atleast of size:
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* num_remote_post_fences * sizeof(__s32) - import sync handles
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*
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* @copy_requests: user memory atleast of size:
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* num_flush_ranges * sizeof(struct nvscic2c_pcie_flush_range)
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*/
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struct nvscic2c_pcie_submit_copy_args {
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__u64 num_local_post_fences;
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__u64 local_post_fences;
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__u64 num_remote_post_fences;
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__u64 remote_post_fences;
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__u64 num_flush_ranges;
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__u64 flush_ranges;
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__u64 remote_post_fence_values;
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};
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/**
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* stream extensions - Pass upper limit for the total possible outstanding
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* submit copy requests.
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* @max_copy_requests: Maximum outstanding @nvscic2c_pcie_submit_copy_args.
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* @max_flush_ranges: Maximum @nvscic2c_pcie_flush_range possible for each
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* of the @max_copy_requests (@nvscic2c_pcie_submit_copy_args)
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* @max_post_fences: Maximum post-fences possible for each of the
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* @max_copy_requests (@nvscic2c_pcie_submit_copy_args)
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*/
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struct nvscic2c_pcie_max_copy_args {
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__u64 max_copy_requests;
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__u64 max_flush_ranges;
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__u64 max_post_fences;
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};
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/* Only to facilitate calculation of maximum size of ioctl arguments.*/
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union nvscic2c_pcie_ioctl_arg_max_size {
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struct nvscic2c_pcie_max_copy_args mc;
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struct nvscic2c_pcie_submit_copy_args cr;
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struct nvscic2c_pcie_free_obj_args fo;
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struct nvscic2c_pcie_import_obj_args io;
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struct nvscic2c_pcie_export_obj_args eo;
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struct nvscic2c_pcie_map_obj_args mp;
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struct nvscic2c_pcie_endpoint_info ep;
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};
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/* IOCTL magic number - seen available in ioctl-number.txt*/
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#define NVSCIC2C_PCIE_IOCTL_MAGIC 0xC2
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#define NVSCIC2C_PCIE_IOCTL_GET_INFO \
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_IOWR(NVSCIC2C_PCIE_IOCTL_MAGIC, 1,\
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struct nvscic2c_pcie_endpoint_info)
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/**
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* notify remote
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*/
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#define NVSCIC2C_PCIE_IOCTL_NOTIFY_REMOTE \
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_IO(NVSCIC2C_PCIE_IOCTL_MAGIC, 2)
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/**
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* Pin/Map Mem or Sync objects.
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*/
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#define NVSCIC2C_PCIE_IOCTL_MAP \
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_IOWR(NVSCIC2C_PCIE_IOCTL_MAGIC, 3,\
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struct nvscic2c_pcie_map_obj_args)
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/**
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* Get Export descriptor for Target/Remote Mem/Sync objects.
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*/
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#define NVSCIC2C_PCIE_IOCTL_GET_AUTH_TOKEN \
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_IOWR(NVSCIC2C_PCIE_IOCTL_MAGIC, 4,\
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struct nvscic2c_pcie_export_obj_args)
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/**
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* Get Handle from the imported export descriptor.
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*/
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#define NVSCIC2C_PCIE_IOCTL_GET_HANDLE \
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_IOWR(NVSCIC2C_PCIE_IOCTL_MAGIC, 5,\
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struct nvscic2c_pcie_import_obj_args)
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/**
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* Free the Mapped/Pinned Source, Target or Imported Mem or Sync object handle.
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*/
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#define NVSCIC2C_PCIE_IOCTL_FREE \
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_IOW(NVSCIC2C_PCIE_IOCTL_MAGIC, 6,\
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struct nvscic2c_pcie_free_obj_args)
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/**
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* Submit a Copy request for transfer.
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*/
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#define NVSCIC2C_PCIE_IOCTL_SUBMIT_COPY_REQUEST \
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_IOW(NVSCIC2C_PCIE_IOCTL_MAGIC, 7,\
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struct nvscic2c_pcie_submit_copy_args)
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/**
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* Set the maximum possible outstanding copy requests that can be submitted.
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*/
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#define NVSCIC2C_PCIE_IOCTL_MAX_COPY_REQUESTS \
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_IOW(NVSCIC2C_PCIE_IOCTL_MAGIC, 8,\
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struct nvscic2c_pcie_max_copy_args)
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#define NVSCIC2C_PCIE_IOCTL_NUMBER_MAX 8
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#endif /*__UAPI_NVSCIC2C_PCIE_IOCTL_H__*/
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