From 4c3f0cf0b4a031c7783d20abc0db1929cb72707b Mon Sep 17 00:00:00 2001 From: mhulagabal Date: Thu, 24 Oct 2024 07:41:47 +0000 Subject: [PATCH] dce: Convert error codes to hex and group errors - Converted error codes from decimal to hexadecimal - Segregated the errors group-wise - Changed unsigned to signed - JIRA TDS-15862 Change-Id: I9da522265ce858d05065908c3e345661bf0b3f65 Signed-off-by: mhulagabal Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3236309 GVS: buildbot_gerritrpt Reviewed-by: Mahesh Kumar Reviewed-by: Vinod Gopalakrishnakurup --- .../interface/dce-core-interface-errors.h | 134 ++++++++++-------- 1 file changed, 78 insertions(+), 56 deletions(-) diff --git a/drivers/platform/tegra/dce/include/interface/dce-core-interface-errors.h b/drivers/platform/tegra/dce/include/interface/dce-core-interface-errors.h index 2d0ee32e..1bd2b841 100644 --- a/drivers/platform/tegra/dce/include/interface/dce-core-interface-errors.h +++ b/drivers/platform/tegra/dce/include/interface/dce-core-interface-errors.h @@ -1,79 +1,101 @@ /* - * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: LicenseRef-NvidiaProprietary * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. + * NVIDIA Corporation and its licensors retain all intellectual property + * and proprietary rights in and to this software, related documentation + * and any modifications thereto. Any use, reproduction, disclosure or + * distribution of this software and related documentation without an express + * license agreement from NVIDIA Corporation is strictly prohibited. */ #ifndef DCE_CORE_INTERFACE_ERRORS_H #define DCE_CORE_INTERFACE_ERRORS_H -#define DCE_ERR_CORE_SUCCESS 0U +#define DCE_ERR_CORE_SUCCESS (0x00000000) -#define DCE_ERR_CORE_NOT_IMPLEMENTED 1U -#define DCE_ERR_CORE_SC7_SEQUENCE 2U -#define DCE_ERR_CORE_RD_MEM_MAP 3U -#define DCE_ERR_CORE_WR_MEM_MAP 4U -#define DCE_ERR_CORE_IVC_INIT 5U -#define DCE_ERR_CORE_MEM_NOT_FOUND 6U -#define DCE_ERR_CORE_MEM_NOT_MAPPED 7U +#define DCE_ERR_CORE_NOT_IMPLEMENTED (0x00000001) +#define DCE_ERR_CORE_SC7_SEQUENCE (0x00000002) +#define DCE_ERR_CORE_RD_MEM_MAP (0x00000003) +#define DCE_ERR_CORE_WR_MEM_MAP (0x00000004) +#define DCE_ERR_CORE_IVC_INIT (0x00000005) +#define DCE_ERR_CORE_BAD_ADMIN_CMD (0x00000006) +#define DCE_ERR_CORE_HSP_DB_INUSE (0x00000007) -#define DCE_ERR_CORE_VMINDEX_INVALID 8U -#define DCE_ERR_CORE_VMINDEX_NO_AST_BASE 9U +#define DCE_ERR_CORE_NULL_PTR (0x00000010) +#define DCE_ERR_CORE_MEM_SIZE (0x00000011) +#define DCE_ERR_CORE_MEM_NOT_FOUND (0x00000012) +#define DCE_ERR_CORE_MEM_NOT_MAPPED (0x00000013) +#define DCE_ERR_CORE_MEM_ALREADY_MAPPED (0x00000014) +#define DCE_ERR_CORE_MEM_BAD_REGION (0x00000015) -#define DCE_ERR_CORE_MEM_ALREADY_MAPPED 10U +#define DCE_ERR_CORE_VMINDEX_INVALID (0x00000020) +#define DCE_ERR_CORE_VMINDEX_NO_AST_BASE (0x00000021) -#define DCE_ERR_CORE_BAD_ADMIN_CMD 11U -#define DCE_ERR_CORE_INTERFACE_LOCKED 12U -#define DCE_ERR_CORE_INTERFACE_INCOMPATIBLE 13U +#define DCE_ERR_CORE_INTERFACE_LOCKED (0x00000030) +#define DCE_ERR_CORE_INTERFACE_INCOMPATIBLE (0x00000031) -#define DCE_ERR_CORE_MEM_SIZE 14U +#define DCE_ERR_CORE_TIMER_INVALID (0x00000040) +#define DCE_ERR_CORE_TIMER_EXPIRED (0x00000041) +#define DCE_ERR_CORE_TIMER_NOT_CREATED (0x00000042) +#define DCE_ERR_CORE_TIMER_NOT_STARTED (0x00000043) -#define DCE_ERR_CORE_NULL_PTR 15U +#define DCE_ERR_CORE_IPC_BAD_TYPE (0x00000050) +#define DCE_ERR_CORE_IPC_NO_HANDLES (0x00000051) +#define DCE_ERR_CORE_IPC_BAD_CHANNEL (0x00000052) +#define DCE_ERR_CORE_IPC_CHAN_REGISTERED (0x00000053) +#define DCE_ERR_CORE_IPC_BAD_HANDLE (0x00000054) +#define DCE_ERR_CORE_IPC_MSG_TOO_LARGE (0x00000055) +#define DCE_ERR_CORE_IPC_NO_BUFFERS (0x00000056) +#define DCE_ERR_CORE_IPC_BAD_HEADER (0x00000057) +#define DCE_ERR_CORE_IPC_IVC_INIT (0x00000058) +#define DCE_ERR_CORE_IPC_NO_DATA (0x00000059) +#define DCE_ERR_CORE_IPC_INVALID_SIGNAL (0x0000005A) +#define DCE_ERR_CORE_IPC_IVC_ERR (0x0000005B) +#define DCE_ERR_CORE_IPC_SIGNAL_REGISTERED (0x0000005C) -#define DCE_ERR_CORE_TIMER_INVALID 16U -#define DCE_ERR_CORE_TIMER_EXPIRED 17U +#define DCE_ERR_CORE_GPIO_INVALID_ID (0x00000060) +#define DCE_ERR_CORE_GPIO_NO_SPACE (0x00000061) -#define DCE_ERR_CORE_IPC_BAD_TYPE 18U -#define DCE_ERR_CORE_IPC_NO_HANDLES 19U -#define DCE_ERR_CORE_IPC_BAD_CHANNEL 20U -#define DCE_ERR_CORE_IPC_CHAN_REGISTERED 21U -#define DCE_ERR_CORE_IPC_BAD_HANDLE 22U -#define DCE_ERR_CORE_IPC_MSG_TOO_LARGE 23U -#define DCE_ERR_CORE_IPC_NO_BUFFERS 24U -#define DCE_ERR_CORE_IPC_BAD_HEADER 25U -#define DCE_ERR_CORE_IPC_IVC_INIT 26U -#define DCE_ERR_CORE_IPC_NO_DATA 27U -#define DCE_ERR_CORE_IPC_INVALID_SIGNAL 28U -#define DCE_ERR_CORE_IPC_IVC_ERR 29U +#define DCE_ERR_CORE_RM_BOOTSTRAP (0x00000070) -#define DCE_ERR_CORE_MEM_BAD_REGION 30U +#define DCE_ERR_CORE_NOT_FOUND (0x00000080) +#define DCE_ERR_CORE_NOT_INITIALIZED (0x00000081) -#define DCE_ERR_CORE_GPIO_INVALID_ID 31U -#define DCE_ERR_CORE_GPIO_NO_SPACE 32U +#define DCE_ERR_CORE_DT_INVALID (0x00000090) +#define DCE_ERR_CORE_DT_NOT_INITIALIZED (0x00000091) +#define DCE_ERR_CORE_DT_NOT_FOUND (0x00000092) -#define DCE_ERR_CORE_RM_BOOTSTRAP 40U +#define DCE_ERR_CORE_IRQ_ENABLE_FAILED (0x000000A0) +#define DCE_ERR_CORE_IRQ_DISABLE_FAILED (0x000000A1) +#define DCE_ERR_CORE_IRQ_INVALID_PARAM (0x000000A2) +#define DCE_ERR_CORE_IRQ_INVALID_HANDLE (0x000000A3) +#define DCE_ERR_CORE_IRQ_REGISTER_FAILED (0x000000A4) +#define DCE_ERR_CORE_IRQ_INVALID_CL_TABLE (0x000000A5) +#define DCE_ERR_CORE_IRQ_NAME_NOT_FOUND (0x000000A6) +#define DCE_ERR_CORE_IRQ_IN_USE (0x000000A7) -#define DCE_ERR_CORE_IPC_SIGNAL_REGISTERED 50U +#define DCE_ERR_CORE_BPMP_MRQ_RESPONSE (0x000000B0) +#define DCE_ERR_CORE_BPMP_MRQ_INVALID_HANDLE (0x000000B1) +#define DCE_ERR_CORE_BPMP_MRQ_INVALID_PARAM (0x000000B2) +#define DCE_ERR_CORE_BPMP_MRQ_GENERIC (0x000000B3) -#define DCE_ERR_CORE_NOT_FOUND 60U -#define DCE_ERR_CORE_NOT_INITIALIZED 61U +#define DCE_ERR_CORE_MMIO_INVALID_PARAM (0x000000C0) +#define DCE_ERR_CORE_MMIO_INVALID_RANGE (0x000000C1) +#define DCE_ERR_CORE_MMIO_MAP_NOT_FOUND (0x000000C2) +#define DCE_ERR_CORE_MMIO_INVALID_HANDLE (0x000000C3) +#define DCE_ERR_CORE_MMIO_NOT_MAPPED (0x000000C4) +#define DCE_ERR_CORE_MMIO_NO_SPACE (0x000000C5) -#define DCE_ERR_CORE_OTHER 9999U +#define DCE_ERR_CORE_I2C_INIT_FAILED (0x000000D0) +#define DCE_ERR_CORE_I2C_CLK_INIT_FAILED (0x000000D1) +#define DCE_ERR_CORE_I2C_RST_INIT_FAILED (0x000000D2) +#define DCE_ERR_CORE_I2C_IRQ_INIT_FAILED (0x000000D3) +#define DCE_ERR_CORE_I2C_INVALID_PARAM (0x000000D4) +#define DCE_ERR_CORE_I2C_NOT_REGISTERED (0x000000D5) +#define DCE_ERR_CORE_I2C_XFER_TIMED_OUT (0x000000D6) +#define DCE_ERR_CORE_I2C_PORT_NOT_FOUND (0x000000D7) + +#define DCE_ERR_CORE_OTHER (0x0000FFFF) #endif