nvethernet: T26X MAC_Address0_High reg AE bit

In T26X, MAC_Address0_High reg AE bit R/W, so changing
UC and BC address indexing to 0 and 1.

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2987634

Bug 4325242

Change-Id: Id2e6d757ceee750a31bf1fdf3821bc5dd892f08b
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
This commit is contained in:
Rakesh Goyal
2023-09-28 13:05:01 +00:00
committed by Bhadram Varka
parent 62e5a277df
commit 4cd40b0b3b
2 changed files with 16 additions and 4 deletions

View File

@@ -208,8 +208,10 @@
/**
* @brief Broadcast and MAC address macros
*/
#define ETHER_MAC_ADDRESS_INDEX 1U
#define ETHER_BC_ADDRESS_INDEX 0
#define ETHER_MAC_ADDRESS_INDEX 1U
#define ETHER_BC_ADDRESS_INDEX 0U
#define ETHER_MAC_ADDRESS_INDEX_T26X 0U
#define ETHER_BC_ADDRESS_INDEX_T26X 1U
#define ETHER_ADDRESS_MAC 1
#define ETHER_ADDRESS_BC 0