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nvethernet: T26X MAC_Address0_High reg AE bit
In T26X, MAC_Address0_High reg AE bit R/W, so changing UC and BC address indexing to 0 and 1. Ported from - https://git-master.nvidia.com/r/c/nvethernet-docs/+/2987634 Bug 4325242 Change-Id: Id2e6d757ceee750a31bf1fdf3821bc5dd892f08b Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
This commit is contained in:
committed by
Bhadram Varka
parent
62e5a277df
commit
4cd40b0b3b
@@ -208,8 +208,10 @@
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/**
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* @brief Broadcast and MAC address macros
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*/
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#define ETHER_MAC_ADDRESS_INDEX 1U
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#define ETHER_BC_ADDRESS_INDEX 0
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#define ETHER_MAC_ADDRESS_INDEX 1U
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#define ETHER_BC_ADDRESS_INDEX 0U
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#define ETHER_MAC_ADDRESS_INDEX_T26X 0U
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#define ETHER_BC_ADDRESS_INDEX_T26X 1U
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#define ETHER_ADDRESS_MAC 1
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#define ETHER_ADDRESS_BC 0
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