From 5193e86207cc7576e59e5e37ab4096881f424d89 Mon Sep 17 00:00:00 2001 From: Sanath Kumar Gampa Date: Mon, 24 Feb 2025 08:59:42 +0000 Subject: [PATCH] kernel-nvidia-oot: Restrict enabling MACSec in PHY Restrict enabling MACSec support in below PHYs via MDIO - MV-Q3244 - 88Q2221M Jira NET-2795 Change-Id: I2cf767ad89762a5daa8ac29e753365af2e5d24fb Signed-off-by: Sanath Kumar Gampa Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3308513 Reviewed-by: Ashutosh Jha Reviewed-by: mobile promotions GVS: buildbot_gerritrpt Reviewed-by: Rakesh Goyal Reviewed-by: Narayana Reddy P Tested-by: mobile promotions --- .../ethernet/nvidia/nvethernet/ether_linux.c | 61 ++++++++++++++++++- .../ethernet/nvidia/nvethernet/ether_linux.h | 23 ++++++- 2 files changed, 82 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c index 57e81b61..076235ad 100644 --- a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c +++ b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c @@ -1,5 +1,18 @@ // SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: Copyright (c) 2019-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +/* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ #include #include @@ -2868,6 +2881,26 @@ static int ether_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, "%s:No clks available, skipping PHY write\n", __func__); return -ENODEV; } + if (pdata->phy_str != NULL) { + // For MV-Q3244 0x401e002a is pointing to 0x407C2780 value pointed by Sau Loh from Mrvl + if (strcmp(pdata->phy_str, "MVQ3244") == 0) { + if ((phyreg == MACSEC_REG_MVQ3244) && ((phydata & OSI_BIT(1)) == 0U)) { + dev_err(pdata->dev, + "restricting access to enable macsec in MVQ3244 PHY \n"); + return -ENODEV; + } + // For 88Q2221M dev 0x1F and Register 0xa008 is pointed to 0x401fa008 + } else if (strcmp(pdata->phy_str, "88Q2221M") == 0) { + if ((phyaddr == MACSEC_REG_88Q2221M) && + (((phydata & OSI_BIT(5)) == 0U) || ((phydata & OSI_BIT(6)) == 0U))) { + dev_err(pdata->dev, + "restricting access to enable macsec in 88Q221M PHY \n"); + return -ENODEV; + } + } else { + /** Do Nothing for other PHY types */ + } + } return osi_write_phy_reg(pdata->osi_core, (unsigned int)phyaddr, (unsigned int)phyreg, phydata); @@ -4272,6 +4305,29 @@ static int ether_handle_priv_wmdio_ioctl(struct ether_priv_data *pdata, prtad = mdio_phy_id_prtad(mii_data->phy_id); devad = mdio_phy_id_devad(mii_data->phy_id); devad = ether_mdio_c45_addr(devad, mii_data->reg_num); + + if (pdata->phy_str != NULL) { + // For MV-Q3244 0x401e002a is pointing to 0x407C2780 value pointed by Sau Loh from Mrvl + if (strcmp(pdata->phy_str, "MVQ3244") == 0) { + if ((devad == MACSEC_REG_MVQ3244) && + ((mii_data->val_in & OSI_BIT(1)) == 0U)) { + dev_err(pdata->dev, + "restricting access to enable macsec in MVQ3244 PHY \n"); + return -ENODEV; + } + // For 88Q2221M dev 0x1F and Register 0xa008 is pointed to 0x401fa008 + } else if (strcmp(pdata->phy_str, "88Q2221M") == 0) { + if ((devad == MACSEC_REG_88Q2221M) && + (((mii_data->val_in & OSI_BIT(5)) == 0U) || + ((mii_data->val_in & OSI_BIT(6)) == 0U))) { + dev_err(pdata->dev, + "restricting access to enable macsec in 88Q2221M PHY \n"); + return -ENODEV; + } + } else { + /** Do Nothing for other PHY types */ + } + } } else { prtad = mii_data->phy_id; devad = mii_data->reg_num; @@ -7403,6 +7459,9 @@ int ether_probe(struct platform_device *pdev) } } + /* Read PHY type from DT */ + (void)of_property_read_string(pdata->dev->of_node, + "nvidia,phy_type", &pdata->phy_str); /* Set netdev features based on hw features */ ether_set_ndev_features(ndev, pdata); diff --git a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h index ff14ee26..ca61fc9e 100644 --- a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h +++ b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h @@ -1,5 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2019-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved */ +/* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ #ifndef ETHER_LINUX_H #define ETHER_LINUX_H @@ -250,6 +263,12 @@ */ #define FIXED_PHY_INVALID_MDIO_ADDR 0xFFU +/** + * @brief PHY register address to enable MACSEc feature in PHY + */ +#define MACSEC_REG_MVQ3244 0x401e002aU +#define MACSEC_REG_88Q2221M 0x401fa008U + #define ETHER_ADDRESS_32BIT 0 #define ETHER_ADDRESS_40BIT 1 #define ETHER_ADDRESS_48BIT 2 @@ -662,6 +681,8 @@ struct ether_priv_data { int phy_reset_post_delay; /** PHY reset duration delay */ int phy_reset_duration; + /** Pointer to the phy type being used */ + const char *phy_str; #ifdef ETHER_NVGRO /** Master queue */ struct sk_buff_head mq;