nv-tegra-mirror/linux-nv-oot
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nv-oot.git synced 2025-12-24 02:01:36 +03:00
Code Issues Packages Projects Releases Wiki Activity

nvethernet: Set MGBE TX, TX_PCS and MAC_DIV clks

Browse Source 
There are three clks for MGBE which needs to be set based
on UPHY GBE mode and PHY line rate.

o MGBE_MAC_DIV_CLK will be set based on PHY line rate
o MGBE_MAC_TX/TX_PCS clks will be set based on UPHY GBE mode

Below are the settings -

UPHY GBE mode = 10G:
===================
Possible MAC working rates: 10G/5G/2.5G
1) MAC DIVISOR: 312.5MHz, 312.5/2MHZ and 312.5/4MHz
2) TX CLK: 644.5MHZ
3) TX PCS_CLK: 156.5MHz

UPHY GBE mode = 5G:
==================
Possible MAC working rates: 5G/2.5G
1) MAC DIVISOR: 312.5/2MHz and 312.5/4MHz
2) TX CLK: 322.2MHZ
3) TX PCS_CLK: 78.125MHz

Bug 200739493

Change-Id: Ie6b21f87d2077b8be621a32b2034b4eff1eb391e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2541313
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Bhadram Varka
2021-06-08 18:52:17 +05:30
committed by Revanth Kumar Uppala
parent 8553696ea7
commit 537d6aa16b
2 changed files with 116 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/net/ethernet/nvidia/nvethernet/ether_linux.h
View File

@@ -100,10 +100,21 @@
#define ETHER_DFLT_PTP_CLK 312500000U
/**
* @brief Ethernet default Rx Input clock frequency
* @brief Ethernet clk rates
*/
#define ETHER_RX_INPUT_CLK_RATE 125000000U
#define ETHER_RX_INPUT_CLK_RATE 125000000UL
#define ETHER_MGBE_MAC_DIV_RATE_10G 312500000UL
#define ETHER_MGBE_MAC_DIV_RATE_5G 156250000UL
#define ETHER_MGBE_MAC_DIV_RATE_2_5G 78125000UL
// gbe_pll2_txclkref (644 MHz) --> programmable link TX_CLK divider
// --> link_Tx_clk --> fixed 1/2 gear box divider --> lane TX clk.
#define ETHER_MGBE_TX_CLK_USXGMII_10G 644531250UL
#define ETHER_MGBE_TX_CLK_USXGMII_5G 322265625UL
#define ETHER_MGBE_TX_PCS_CLK_USXGMII_10G 156250000UL
#define ETHER_MGBE_TX_PCS_CLK_USXGMII_5G 78125000UL
#define ETHER_EQOS_TX_CLK_1000M 125000000UL
#define ETHER_EQOS_TX_CLK_100M 25000000UL
#define ETHER_EQOS_TX_CLK_10M 2500000UL
/**
* @addtogroup CONFIG Ethernet configuration error codes
*