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linux: Add PCIe DMA sanity header
Add common DMA sanity helper header that can be used by both EP client and EP function sanity DMA test drivers. Bug 4865361 Change-Id: Ia448065a694e3784b5bd158ebb8a9b049c1fa62c Signed-off-by: Srishti Goel <srgoel@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3225560 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Srishti Goel
259
include/linux/tegra-pcie-dma-sanity-helpers.h
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259
include/linux/tegra-pcie-dma-sanity-helpers.h
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#ifndef TEGRA_PCIE_DMA_SANITY_HELPERS_H
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#define TEGRA_PCIE_DMA_SANITY_HELPERS_H
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#include <linux/tegra-pcie-dma.h>
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#define TEGRA264_PCIE_DMA_MSI_CRC_VEC (TEGRA264_PCIE_DMA_MSI_REMOTE_VEC + 1U)
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#define EDMA_PERF (edma->dma_size * edma->nents * 8UL / (diff / 1000))
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#define NUM_EDMA_DESC 16
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/* Update DMA_DD_BUF_SIZE and DMA_LL_BUF_SIZE when changing BAR0_SIZE */
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#define BAR0_SIZE SZ_256M
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/* DMA'able memory range */
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#define BAR0_HEADER_SIZE SZ_1M
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#define BAR0_DMA_BUF_OFFSET BAR0_HEADER_SIZE
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#define BAR0_DMA_BUF_SIZE (BAR0_SIZE - BAR0_DMA_BUF_OFFSET)
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/* First 1MB of BAR0 is reserved for control data */
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struct pcie_epf_bar {
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/* RP system memory allocated for EP DMA operations */
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u64 rp_phy_addr;
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/* EP system memory allocated as BAR */
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u64 ep_phy_addr;
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};
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struct edmalib_sanity {
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void *priv;
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struct tegra_pcie_dma_desc *ll_desc;
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void *cookie;
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void *src_virt;
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void *dst_virt;
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dma_addr_t src_dma_addr;
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dma_addr_t dst_dma_addr;
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struct device *fdev;
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struct device *cdev;
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u64 priv_iter;
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nvpcie_dma_soc_t chip_id;
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ktime_t edma_start_time;
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u64 msi_addr;
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u32 msi_data;
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u32 msi_irq;
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/* Testing parameters */
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u32 dma_size;
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tegra_pcie_dma_chan_type_t edma_ch_type;
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u32 nents;
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u32 stress_count;
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bool deinit_dma;
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/* Channel parameters */
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u32 success_xfer_count;
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u32 abort_timeout_nomem_xfer_count;
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u32 other_xfer_fail_count;
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struct completion channel_completion;
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};
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static struct edmalib_sanity *l_edma;
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/**
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* @brief This function does the CPU comparison for a local READ on the EP
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*
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* @param[in] edma contains all info about the edma test
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* (including source addr, destination addr, size of transfer)
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* @param[in] priv contains information about iteration number (for address offset)
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*
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* @return
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* - count of incorrectly transferred bits
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*/
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static u64 cpu_verification(struct edmalib_sanity *edma, void *priv)
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{
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u64 cb = *(u64 *)priv;
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/* Iteration number which helps with the src and dst addr */
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u64 it_num = cb & 0xFFFF;
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u64 total_fails = 0, i, j, total_size = edma->dma_size * edma->nents, tmp_diff;
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u64 *tmp_src = edma->src_virt + (it_num * total_size);
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u64 *tmp_dst = edma->dst_virt + (it_num * total_size);
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/* Loop to check bits using CPU */
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for (i = 0; i < total_size; i += sizeof(u64)) {
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if ((*tmp_src) != (*tmp_dst)) {
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tmp_diff = (*tmp_src) ^ (*tmp_dst);
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for (j = 0; j < 64; j++) {
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total_fails += tmp_diff & 1;
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tmp_diff >>= 1;
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}
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}
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/* Updating the pointer */
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tmp_src += 1;
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tmp_dst += 1;
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}
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return total_fails;
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}
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/**
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* @brief This function prints the perf of the iteration and the CPU verification result
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*
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* @param[in] edma - contains all info about the edma test, status - returns status of DMA engine
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*/
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static void edma_sanity_complete(void *priv, tegra_pcie_dma_status_t status)
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{
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struct edmalib_sanity *edma = l_edma;
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u64 cb = *(u64 *)priv;
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/* Iteration number which helps decide if the callback status counts to be printed */
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u64 it_num = cb & 0xFFFF;
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/* Time taken for the transfer */
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u64 diff = ktime_to_ns(ktime_get()) - ktime_to_ns(edma->edma_start_time);
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u64 total_fail_bits = 0;
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/* Updating counts of the status for the callbacks */
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if (status == TEGRA_PCIE_DMA_SUCCESS)
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edma->success_xfer_count++;
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else {
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if ((status == TEGRA_PCIE_DMA_ABORT) ||
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(status == TEGRA_PCIE_DMA_FAIL_TIMEOUT) ||
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(status == TEGRA_PCIE_DMA_FAIL_NOMEM)) {
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edma->abort_timeout_nomem_xfer_count++;
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} else
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edma->other_xfer_fail_count++;
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}
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/* CPU verification */
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total_fail_bits = cpu_verification(edma, priv);
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/* Print the performance and other stats of the iteration */
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dev_info(edma->fdev, "%s: WR-Async iteration %lld | Channel 0 | %d desc of Sz %uKB each | Bit-error-count: %llu | Perf: %llu Mbps | Time-taken: %llu ns |\n",
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__func__, it_num, edma->nents, edma->dma_size / SZ_1K,
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total_fail_bits, EDMA_PERF, diff);
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/* Printing the statistics of status to callbacks if last iteration */
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if (it_num == (edma->stress_count - 1))
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dev_info(edma->fdev, "%s: successes=%d | abort/timeout/nomem=%d | other failiures=%d |\n",
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__func__, edma->success_xfer_count,
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edma->abort_timeout_nomem_xfer_count, edma->other_xfer_fail_count);
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/* Complete the iteration */
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complete(&edma->channel_completion);
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}
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/**
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* @brief This function performs the testing itself. Switch on 1 channel in SYNC/ASYNC mode
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*
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* @param[in] edma - contains all info about the edma test
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*
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* @retVal EDMA_XFER_SUCCESS, EDMA_XFER_FAIL_INVAL_INPUTS, EDMA_XFER_FAIL_NOMEM
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* EDMA_XFER_FAIL_TIMEOUT, EDMA_XFER_ABORT, EDMA_XFER_DEINIT
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*/
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static int edmalib_sanity_tester(struct edmalib_sanity *edma)
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{
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u32 j, k, max_size;
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tegra_pcie_dma_status_t ret;
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struct tegra_pcie_dma_init_info info = {};
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struct tegra_pcie_dma_chans_info *chan_info;
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struct tegra_pcie_dma_xfer_info tx_info = {};
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struct tegra_pcie_dma_desc *ll_desc = edma->ll_desc;
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l_edma = edma;
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info.dev = edma->cdev;
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info.soc = edma->chip_id;
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chan_info = &info.tx[0];
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info.msi_irq = edma->msi_irq;
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info.msi_data = edma->msi_data;
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info.msi_addr = edma->msi_addr;
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/* Setting up the channels */
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chan_info->num_descriptors = 16;
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chan_info->ch_type = edma->edma_ch_type;
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/* The src/dst addresses should not exceed the accessible memory */
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max_size = (BAR0_DMA_BUF_SIZE - BAR0_DMA_BUF_OFFSET);
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if (((edma->dma_size * edma->nents) > max_size)) {
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dev_err(edma->fdev, "%s: max dma size including all nents(%d), max_nents(%d), dma_size(%d) should be <= 0x%x\n",
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__func__, edma->nents, NUM_EDMA_DESC, edma->dma_size, max_size);
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return 0;
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}
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if (!edma->cookie) {
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ret = tegra_pcie_dma_initialize(&info, &edma->cookie);
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if (ret != TEGRA_PCIE_DMA_SUCCESS) {
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dev_err(edma->fdev, "%s: tegra_pcie_dma_initialize() fail: %d\n",
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__func__, ret);
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return -1;
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}
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/* Since this chip uses MSI interrupts for DMA: */
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if (edma->chip_id == NVPCIE_DMA_SOC_T264) {
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ret = tegra_pcie_dma_set_msi(edma->cookie, edma->msi_addr, edma->msi_data);
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if (ret != TEGRA_PCIE_DMA_SUCCESS) {
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dev_err(edma->fdev, "%s: tegra_pcie_dma_set_msi() fail: %d\n",
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__func__, ret);
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return -1;
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}
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}
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}
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/* generate random bytes to transfer */
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get_random_bytes(edma->src_virt, edma->dma_size * edma->nents * edma->stress_count);
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dev_info(edma->fdev, "%s: EDMA LIB WR started for %d chans, size %d Bytes, iterations: %d of descriptors %d\n",
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__func__, 1, edma->dma_size, edma->stress_count,
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edma->nents);
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/* Initialize the completion variable */
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init_completion(&edma->channel_completion);
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/* Refresh channel parameters */
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edma->success_xfer_count = 0;
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edma->abort_timeout_nomem_xfer_count = 0;
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edma->other_xfer_fail_count = 0;
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tx_info.desc = edma->ll_desc;
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for (k = 0; k < edma->stress_count; k++) {
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/* Populate the src and dst addresses, transfer size */
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for (j = 0; j < edma->nents; j++) {
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/* Update by j dma_size and k tsz */
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ll_desc->src = edma->src_dma_addr + ((j + (k * edma->nents)) *
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edma->dma_size);
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ll_desc->dst = edma->dst_dma_addr + ((j + (k * edma->nents)) *
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edma->dma_size);
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ll_desc->sz = edma->dma_size;
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ll_desc++;
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}
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ll_desc = edma->ll_desc;
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tx_info.channel_num = 0;
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tx_info.type = TEGRA_PCIE_DMA_WRITE;
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tx_info.nents = edma->nents;
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tx_info.complete = edma_sanity_complete;
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edma->priv_iter = k;
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tx_info.priv = &edma->priv_iter;
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edma->edma_start_time = ktime_get();
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ret = tegra_pcie_dma_submit_xfer(edma->cookie, &tx_info);
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wait_for_completion_timeout(&(edma->channel_completion),
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msecs_to_jiffies(edma->dma_size
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* 1000));
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if (ret) {
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dev_err(edma->fdev, "%s: Submission error at iteration = %d | error code: %d |\n",
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__func__, k, ret);
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return ret;
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}
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}
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if (edma->deinit_dma) {
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tegra_pcie_dma_deinit(&edma->cookie);
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edma->cookie = NULL;
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}
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return 0;
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}
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#endif
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