platform: tegra: camera: add operation callback

The Nvhost-related APIs have been deprecated and are no longer
supported since our migration from K510 to K515. Therefore, the camera
platform driver should refrain from using "nvhost_*" functions to set
the clock rate.

Integrate the common operation callback interface into the
tegra_camera_dev_info structure. This modification allows individual
drivers to achieve clock set rate operations by registering the
callback and completing the implementation.

Bug 4374126

Signed-off-by: Johnny Liu <johnliu@nvidia.com>
Change-Id: Iebed7cc974f5dbdabddded3c84d0925de3a6c4f9
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3020535
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ankur Pawar <ankurp@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>

drivers/video/tegra/camera/tegra_camera_platform.c

@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2015-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+/*
+ * SPDX-FileCopyrightText: Copyright (C) 2015-2023 NVIDIA CORPORATION.  All rights reserved.
+ */
 
 #include <linux/fs.h>
 #include <linux/platform_device.h>
@@ -656,7 +658,6 @@ EXPORT_SYMBOL(tegra_camera_get_device_list_stats);
 static int calculate_and_set_device_clock(struct tegra_camera_info *info,
 		struct tegra_camera_dev_info *cdev)
 {
-	int ret = 0;
 	u64 active_pr = info->active_pixel_rate;
 	u64 phy_pr = info->phy_pixel_rate;
 	u32 overhead = cdev->overhead + 100;
@@ -675,6 +676,9 @@ static int calculate_and_set_device_clock(struct tegra_camera_info *info,
 	if (cdev->hw_type == HWTYPE_NONE)
 		return 0;
 
+	if (!cdev->ops->set_rate)
+		return -EOPNOTSUPP;
+
 	switch (cdev->hw_type) {
 	case HWTYPE_CSI:
 		if (info->sensor_type == SENSORTYPE_SLVSEC)
@@ -720,24 +724,7 @@ static int calculate_and_set_device_clock(struct tegra_camera_info *info,
 	if (info->num_active_streams == 0)
 		clk_rate = 0;
 
-	if (clk_rate != cdev->clk_rate)
+	return cdev->ops->set_rate(cdev, clk_rate);
-		cdev->clk_rate = clk_rate;
-	/*TODO OOT nvhost_module_set_rate, nvhost_module_get_rate
-	else
-		set_clk = false;
-
-	if (set_clk) {
-		ret = nvhost_module_set_rate(cdev->pdev, &cdev->hw_type,
-				cdev->clk_rate, 0, NVHOST_CLOCK);
-		if (ret)
-			return ret;
-
-		// save the actual rate set by nvhost
-		ret = nvhost_module_get_rate(cdev->pdev,
-				&cdev->actual_clk_rate, 0);
-	}*/
-
-	return ret;
 }
 
 int tegra_camera_update_clknbw(void *priv, bool stream_on)

include/media/tegra_camera_platform.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (C) 2015-2023 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #ifndef _TEGRA_CAMERA_PLATFORM_H_
@@ -38,6 +38,16 @@ enum tegra_camera_sensor_type {
 	SENSORTYPE_MAX,
 };
 
+struct tegra_camera_dev_info;
+
+/**
+ * struct tegra_camera_dev_ops - camera device operations
+ * @set_rate: set the device clock rate
+ */
+struct tegra_camera_dev_ops {
+	int (*set_rate)(struct tegra_camera_dev_info *cdev_info, unsigned long rate);
+};
+
 /**
  * struct tegra_camera_dev_info - camera devices information
  * @priv: a unique identifier assigned during registration
@@ -45,8 +55,6 @@ enum tegra_camera_sensor_type {
  * @bus_width: csi bus width for clock calculation
  * @overhead: hw/ sw overhead considered while calculations
  * @ppc: HW capability, pixels per clock
- * @clk_rate: calculated clk rate for this node
- * @actual_clk_rate: clk rate set by nvhost
  * @bw: calculated bw for this node
  * @use_max: populated by hw engine to decide it's clocking policy
  * @memory_latency: latency allowed for memory freq scaling
@@ -57,6 +65,7 @@ enum tegra_camera_sensor_type {
  * @bpp: bytes per pixel
  * @stream_on: stream enabled on the channel
  * @device_node: list node
+ * @ops: operation callbacks of the camera device
  */
 struct tegra_camera_dev_info {
 	void *priv;
@@ -66,9 +75,7 @@ struct tegra_camera_dev_info {
 	u64 lane_speed;
 	u32 lane_num;
 	u32 ppc;
-	u64 clk_rate;
 	u64 pg_clk_rate;
-	unsigned long actual_clk_rate;
 	u64 bw;
 	bool use_max;
 	u32 memory_latency;
@@ -79,6 +86,7 @@ struct tegra_camera_dev_info {
 	u32 bpp;
 	bool stream_on;
 	struct list_head device_node;
+	const struct tegra_camera_dev_ops *ops;
 };
 
 int tegra_camera_update_isobw(void);