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nvethernet: set affinity for common irq

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Issue: when Softirq, vm and common interrupt
are scheduled on CPU0, due to priority inversion
of software IRQ, scheduling ISR corresponding to
HW interrupt got delayed.

Fix: set common IRQ affinity to other CPU core.

Bug 200780703

Change-Id: I56903de12fc753ac0075ace75ed72d34eac95c5d
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2610987
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rakesh Goyal
2021-10-12 14:47:52 +05:30
committed by Revanth Kumar Uppala
parent 5f3e27f093
commit 594032b82a
2 changed files with 31 additions and 0 deletions
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9
drivers/net/ethernet/nvidia/nvethernet/ether_linux.h
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@@ -36,6 +36,7 @@
#include <linux/module.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/smp.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/tcp.h>
@@ -84,6 +85,10 @@
* @brief Size of Ethernet IRQ name.
*/
#define ETHER_IRQ_NAME_SZ 32
/**
* @brief CPU to handle ethernet common interrupt
*/
#define ETHER_COMMON_IRQ_DEFAULT_CPU 4U
/**
* @addtogroup MAC address DT string
@@ -466,6 +471,10 @@ struct ether_priv_data {
unsigned int common_irq_alloc_mask;
/** Common IRQ number for MAC */
int common_irq;
/** CPU affinity mask for Common IRQ */
cpumask_t common_isr_cpu_mask;
/** CPU ID for handling Common IRQ */
unsigned int common_isr_cpu_id;
/** Array of DMA Transmit channel IRQ numbers */
int tx_irqs[ETHER_MAX_IRQS];
/** Array of DMA Receive channel IRQ numbers */