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ASoC: tegra-alt: create the new drivers for T186
1. Create T186 machine driver 2. Create ASRC/ARAD codec driver 3. Create header files of ahub_unit_fpga_clock, machine utility, afc, xbar, admaif for T186 4. Create files for additional T186 features of machine utility, afc, xbar Bug 1582514 Bug 1582510 Change-Id: I505e0af612c4399c675e39185879612ac1992768 Signed-off-by: Junghyun Kim <juskim@nvidia.com> Reviewed-on: http://git-master/r/751592 Reviewed-by: Dipesh Gandhi <dipeshg@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
This commit is contained in:
Junghyun Kim
committed by
Sameer Pujar
Sameer Pujar
parent
e69072642b
commit
606239daf9
43
sound/soc/tegra-alt/Kconfig
Normal file
43
sound/soc/tegra-alt/Kconfig
Normal file
@@ -0,0 +1,43 @@
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config SND_SOC_TEGRA_ALT_186
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def_bool y
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depends on SND_SOC_TEGRA_ALT
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depends on ARCH_TEGRA_APE
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depends on ARCH_TEGRA_18x_SOC
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config SND_SOC_TEGRA186_ASRC_ALT
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tristate "Tegra186 ASRC driver"
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depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_186
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help
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Say Y or M if you want to add support for Tegra186 ASRC module.
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config SND_SOC_TEGRA186_ARAD_ALT
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tristate "Tegra186 ARAD driver"
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depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_186
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help
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Say Y or M if you want to add support for Tegra186 ARAD module.
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config SND_SOC_TEGRA_T186REF_ALT
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tristate "SoC Audio support for T186Ref"
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depends on SND_SOC_TEGRA_ALT
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depends on ARCH_TEGRA_18x_SOC
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select SND_SOC_TEGRA210_XBAR_ALT
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select SND_SOC_TEGRA210_PCM_ALT
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select SND_SOC_TEGRA210_ADMA_ALT
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select SND_SOC_TEGRA210_ADMAIF_ALT
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select SND_SOC_TEGRA210_I2S_ALT
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select SND_SOC_TEGRA210_DMIC_ALT
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select SND_SOC_TEGRA210_AMX_ALT
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select SND_SOC_TEGRA210_ADX_ALT
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select SND_SOC_TEGRA210_MIXER_ALT
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select SND_SOC_TEGRA210_SFC_ALT
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select SND_SOC_TEGRA210_AFC_ALT
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select SND_SOC_TEGRA210_MVC_ALT
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select SND_SOC_TEGRA210_OPE_ALT
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select SND_SOC_TEGRA210_SPDIF_ALT
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select SND_SOC_TEGRA186_ASRC_ALT
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select SND_SOC_TEGRA186_ARAD_ALT
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select SND_SOC_TEGRA_ASOC_HWDEP_ALT
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select SND_SOC_SPDIF
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select SND_SOC_AD193X
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help
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Say Y or M here.
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16
sound/soc/tegra-alt/Makefile
Normal file
16
sound/soc/tegra-alt/Makefile
Normal file
@@ -0,0 +1,16 @@
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KBUILD_CFLAGS += -I$(srctree)/../kernel-3.18/sound/soc/tegra-alt
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snd-soc-tegra186-alt-asrc-objs := tegra186_asrc_alt.o
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snd-soc-tegra186-alt-arad-objs := tegra186_arad_alt.o
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snd-soc-tegra186-alt-afc-objs := tegra186_afc_alt.o
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snd-soc-tegra186-alt-xbar-objs := tegra186_xbar_alt.o
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obj-$(CONFIG_SND_SOC_TEGRA186_ASRC_ALT) += snd-soc-tegra186-alt-asrc.o
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obj-$(CONFIG_SND_SOC_TEGRA186_ARAD_ALT) += snd-soc-tegra186-alt-arad.o
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obj-$(CONFIG_SND_SOC_TEGRA210_AFC_ALT) += snd-soc-tegra186-alt-afc.o
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obj-$(CONFIG_SND_SOC_TEGRA210_XBAR_ALT) += snd-soc-tegra186-alt-xbar.o
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snd-soc-tegra-alt-t186ref-objs := tegra_t186ref_alt.o tegra_asoc_machine_alt_t18x.o \
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../../../../kernel-3.18/sound/soc/tegra-alt/tegra_asoc_machine_alt.o
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obj-$(CONFIG_SND_SOC_TEGRA_T186REF_ALT) += snd-soc-tegra-alt-t186ref.o
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778
sound/soc/tegra-alt/tegra186_arad_alt.c
Normal file
778
sound/soc/tegra-alt/tegra186_arad_alt.c
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@@ -0,0 +1,778 @@
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/*
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* tegra186_arad_alt.c - Tegra186 ARAD driver
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*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/of_device.h>
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#include "tegra210_xbar_alt.h"
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#include "tegra186_arad_alt.h"
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#define DRV_NAME "tegra186-arad"
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#define ARAD_LANE_NUMERATOR_MUX(id) \
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(TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL + id*TEGRA186_ARAD_LANE_STRIDE)
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#define ARAD_LANE_DENOMINATOR_MUX(id) \
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(TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL + id*TEGRA186_ARAD_LANE_STRIDE)
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#define ARAD_LANE_REG(reg, id) (reg + (id * TEGRA186_ARAD_LANE_STRIDE))
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#define ASRC_STREAM_REG_DEFAULTS(id) \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_RATIO_INTEGER_PART, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_RATIO_FRACTIONAL_PART, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_NUMERATOR_PRESCALAR, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_DENOMINATOR_PRESCALAR, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_SERVO_LOOP_CONFIG, id), 0xd5e7}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_LOCK_UNLOCK_DETECTOR_CONFIG, id), 0x840500}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_ERROR_LOCK_THRESHOLD, id), 0x400000}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_ERROR_UNLOCK_THRESHOLD, id), 0xa00000}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_RATIO_CALCULATOR_CONFIG, id), 0xf000006}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_CYA, id), 0x0}
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static const struct reg_default tegra186_arad_reg_defaults[] = {
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{ TEGRA186_ARAD_LANE_ENABLE, 0x0},
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{ TEGRA186_ARAD_LANE_SOFT_RESET, 0x0},
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{ TEGRA186_ARAD_LANE_INT_MASK, 0x0},
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{ TEGRA186_ARAD_LANE_INT_SET, 0x0},
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{ TEGRA186_ARAD_LANE_INT_CLEAR, 0x0},
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{ TEGRA186_ARAD_LANE_INT_CLEAR, 0x0},
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{ TEGRA186_ARAD_CG, 0x0},
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{ TEGRA186_ARAD_CYA_GLOBAL, 0x0},
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ASRC_STREAM_REG_DEFAULTS(0),
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ASRC_STREAM_REG_DEFAULTS(1),
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ASRC_STREAM_REG_DEFAULTS(2),
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ASRC_STREAM_REG_DEFAULTS(3),
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ASRC_STREAM_REG_DEFAULTS(4),
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ASRC_STREAM_REG_DEFAULTS(5),
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{ TEGRA186_ARAD_TX_CIF_CTRL, 0x115500},
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};
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static int tegra186_arad_runtime_suspend(struct device *dev)
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{
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struct tegra186_arad *arad = dev_get_drvdata(dev);
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regcache_cache_only(arad->regmap, true);
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pm_runtime_put_sync(dev->parent);
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return 0;
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}
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static int tegra186_arad_runtime_resume(struct device *dev)
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{
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struct tegra186_arad *arad = dev_get_drvdata(dev);
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int ret;
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ret = pm_runtime_get_sync(dev->parent);
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if (ret < 0) {
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dev_err(dev, "parent get_sync failed: %d\n", ret);
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return ret;
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}
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regcache_cache_only(arad->regmap, false);
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regcache_sync(arad->regmap);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra186_arad_suspend(struct device *dev)
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{
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struct tegra186_arad *arad = dev_get_drvdata(dev);
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regcache_mark_dirty(arad->regmap);
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return 0;
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}
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#endif
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static int tegra186_arad_codec_probe(struct snd_soc_codec *codec)
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{
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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codec->control_data = arad->regmap;
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return 0;
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}
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static int tegra186_arad_get_lane_lock_status(
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struct tegra186_arad *arad, unsigned int lane_id)
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{
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unsigned int val;
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regmap_read(arad->regmap,
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TEGRA186_ARAD_LANE_STATUS, &val);
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val = (val >> (16 + lane_id)) & 0x1;
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return val;
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}
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static struct snd_soc_dai_ops tegra186_arad_out_dai_ops = {
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};
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static struct snd_soc_dai_driver tegra186_arad_dais[] = {
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{
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.name = "ARAD OUT",
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.capture = {
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.stream_name = "ARAD Transmit",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S24_LE,
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},
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.ops = &tegra186_arad_out_dai_ops,
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},
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};
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static const int tegra186_arad_mux_value[] = {
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-1, /* None */
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0, 1, 2, 3, 4, 5, /* I2S1~6 */
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12, 13, 14, 15, /* DMIC1~4 */
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24, 25, /* DSPK1~2 */
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26, 27, /* IQC1~2 */
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28, 29, 30, 31, /* SPDIF_RX1,2 & SPDIF_TX1,2 */
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};
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static const char * const tegra186_arad_mux_text[] = {
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"None",
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"I2S1",
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"I2S2",
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"I2S3",
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"I2S4",
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"I2S5",
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"I2S6",
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"DMIC1",
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"DMIC2",
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"DMIC3",
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"DMIC4",
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"DSPK1",
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"DSPK2",
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"IQC1",
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"IQC2",
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"SPDIF1_RX1",
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"SPDIF1_RX2",
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"SPDIF1_TX1",
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"SPDIF1_TX2",
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};
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static int tegra186_arad_mux_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_enum *arad_private =
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(struct soc_enum *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int val, loop = 0;
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regmap_read(arad->regmap, arad_private->reg, &val);
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if (val) {
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for (loop = 1; loop < 19; loop++)
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if (val & (1<<arad_private->values[loop])) {
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val = loop;
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break;
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}
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}
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ucontrol->value.integer.value[0] = val;
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return 0;
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}
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static int tegra186_arad_mux_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_enum *arad_private =
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(struct soc_enum *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int val = ucontrol->value.integer.value[0];
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if (!val)
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regmap_write(arad->regmap, arad_private->reg, 0);
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else
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regmap_write(arad->regmap, arad_private->reg,
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1 << arad_private->values[val]);
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return 0;
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}
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static int tegra186_arad_get_ratio_int(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *arad_private =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int val;
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regmap_read(arad->regmap, arad_private->reg, &val);
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ucontrol->value.integer.value[0] = val;
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return 0;
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}
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static int tegra186_arad_get_ratio_frac(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *arad_private =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int val;
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regmap_read(arad->regmap, arad_private->reg, &val);
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ucontrol->value.integer.value[0] = val;
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return 0;
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}
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static int tegra186_arad_get_enable_lane(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *arad_private =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int enable;
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regmap_read(arad->regmap, arad_private->reg, &enable);
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enable = (enable >> arad_private->shift) & arad_private->max;
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ucontrol->value.integer.value[0] = enable;
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return 0;
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}
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static int tegra186_arad_put_enable_lane(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *arad_private =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int enable = 0, lane_id = arad_private->shift;
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int dcnt = 10;
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enable = ucontrol->value.integer.value[0];
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regmap_update_bits(arad->regmap,
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arad_private->reg, 1<<arad_private->shift,
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enable<<arad_private->shift);
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if (enable)
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while (!tegra186_arad_get_lane_lock_status(arad, lane_id) &&
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dcnt--)
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udelay(100);
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else {
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regmap_update_bits(arad->regmap,
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TEGRA186_ARAD_LANE_SOFT_RESET, 1<<arad_private->shift,
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1<<arad_private->shift);
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while (tegra186_arad_get_lane_lock_status(arad, lane_id) &&
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dcnt--)
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udelay(100);
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}
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if (dcnt < 0) {
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if (enable)
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pr_err("ARAD Lane %d can't be locked\n", lane_id+1);
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else
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pr_err("ARAD Lane %d can't be unlocked\n", lane_id+1);
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return -ETIMEDOUT;
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} else
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return 0;
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}
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#define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues) \
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{ .reg = xreg, .shift_l = shift, .shift_r = shift, \
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.items = xmax, .texts = xtexts, .values = xvalues, \
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.mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0}
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#define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, \
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xtexts, xvalues) \
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struct soc_enum name = SOC_VALUE_ENUM_WIDE(xreg, shift, \
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ARRAY_SIZE(xtexts), xtexts, xvalues)
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||||
|
||||
#define ARAD_MUX_ENUM_CTRL_DECL(ename, reg) \
|
||||
SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, reg, 0, \
|
||||
tegra186_arad_mux_text, tegra186_arad_mux_value); \
|
||||
static const struct snd_kcontrol_new ename##_ctrl = \
|
||||
SOC_DAPM_ENUM_EXT("Mux", ename##_enum, \
|
||||
tegra186_arad_mux_get, \
|
||||
tegra186_arad_mux_put)
|
||||
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(numerator1,
|
||||
TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(numerator2,
|
||||
TEGRA186_ARAD_LANE2_NUMERATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(numerator3,
|
||||
TEGRA186_ARAD_LANE3_NUMERATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(numerator4,
|
||||
TEGRA186_ARAD_LANE4_NUMERATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(numerator5,
|
||||
TEGRA186_ARAD_LANE5_NUMERATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(numerator6,
|
||||
TEGRA186_ARAD_LANE6_NUMERATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(denominator1,
|
||||
TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(denominator2,
|
||||
TEGRA186_ARAD_LANE2_DENOMINATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(denominator3,
|
||||
TEGRA186_ARAD_LANE3_DENOMINATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(denominator4,
|
||||
TEGRA186_ARAD_LANE4_DENOMINATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(denominator5,
|
||||
TEGRA186_ARAD_LANE5_DENOMINATOR_MUX_SEL);
|
||||
static ARAD_MUX_ENUM_CTRL_DECL(denominator6,
|
||||
TEGRA186_ARAD_LANE6_DENOMINATOR_MUX_SEL);
|
||||
|
||||
#define ARAD_RATIO_GEN_WIDGETS(sname, ename) \
|
||||
SND_SOC_DAPM_AIF_OUT(sname " TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
|
||||
SND_SOC_DAPM_MUX(sname " MUX", SND_SOC_NOPM, 0, 0, &ename##_ctrl)
|
||||
|
||||
static const struct snd_soc_dapm_widget tegra186_arad_widgets[] = {
|
||||
SND_SOC_DAPM_SIGGEN("I2S1 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("I2S2 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("I2S3 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("I2S4 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("I2S5 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("I2S6 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("DMIC1 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("DMIC2 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("DMIC3 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("DMIC4 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("DSPK1 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("DSPK2 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("IQC1 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("IQC2 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("SPDIF1_RX1 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("SPDIF1_RX2 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("SPDIF1_TX1 SIG"),
|
||||
SND_SOC_DAPM_SIGGEN("SPDIF1_TX2 SIG"),
|
||||
|
||||
ARAD_RATIO_GEN_WIDGETS("Numerator1", numerator1),
|
||||
ARAD_RATIO_GEN_WIDGETS("Numerator2", numerator2),
|
||||
ARAD_RATIO_GEN_WIDGETS("Numerator3", numerator3),
|
||||
ARAD_RATIO_GEN_WIDGETS("Numerator4", numerator4),
|
||||
ARAD_RATIO_GEN_WIDGETS("Numerator5", numerator5),
|
||||
ARAD_RATIO_GEN_WIDGETS("Numerator6", numerator6),
|
||||
ARAD_RATIO_GEN_WIDGETS("Denominator1", denominator1),
|
||||
ARAD_RATIO_GEN_WIDGETS("Denominator2", denominator2),
|
||||
ARAD_RATIO_GEN_WIDGETS("Denominator3", denominator3),
|
||||
ARAD_RATIO_GEN_WIDGETS("Denominator4", denominator4),
|
||||
ARAD_RATIO_GEN_WIDGETS("Denominator5", denominator5),
|
||||
ARAD_RATIO_GEN_WIDGETS("Denominator6", denominator6),
|
||||
|
||||
SND_SOC_DAPM_AIF_OUT("Packetizer", NULL, 0, 0, 0, 0),
|
||||
};
|
||||
|
||||
#define RATIO_GEN_ROUTE(sname) \
|
||||
{ sname " MUX", NULL, "I2S1 SIG" }, \
|
||||
{ sname " MUX", NULL, "I2S2 SIG" }, \
|
||||
{ sname " MUX", NULL, "I2S3 SIG" }, \
|
||||
{ sname " MUX", NULL, "I2S4 SIG" }, \
|
||||
{ sname " MUX", NULL, "I2S5 SIG" }, \
|
||||
{ sname " MUX", NULL, "I2S6 SIG" }, \
|
||||
{ sname " MUX", NULL, "DMIC1 SIG" }, \
|
||||
{ sname " MUX", NULL, "DMIC2 SIG" }, \
|
||||
{ sname " MUX", NULL, "DMIC3 SIG" }, \
|
||||
{ sname " MUX", NULL, "DMIC4 SIG" }, \
|
||||
{ sname " MUX", NULL, "IQC1 SIG" }, \
|
||||
{ sname " MUX", NULL, "IQC2 SIG" }, \
|
||||
{ sname " MUX", NULL, "SPDIF1_RX1 SIG" }, \
|
||||
{ sname " MUX", NULL, "SPDIF1_RX2 SIG" }, \
|
||||
{ sname " MUX", NULL, "SPDIF1_TX1 SIG" }, \
|
||||
{ sname " MUX", NULL, "SPDIF1_TX2 SIG" }
|
||||
|
||||
#define RATIO_GEN(sname) \
|
||||
RATIO_GEN_ROUTE(sname), \
|
||||
{ sname " TX", NULL, sname " MUX" }
|
||||
|
||||
#define PACKETIZER_ROUTE(sname) \
|
||||
{ sname, "Numerator1 TX", "Numerator1 TX" }, \
|
||||
{ sname, "Numerator2 TX", "Numerator2 TX" }, \
|
||||
{ sname, "Numerator3 TX", "Numerator3 TX" }, \
|
||||
{ sname, "Numerator4 TX", "Numerator4 TX" }, \
|
||||
{ sname, "Numerator5 TX", "Numerator5 TX" }, \
|
||||
{ sname, "Numerator6 TX", "Numerator6 TX" }, \
|
||||
{ sname, "Denominator1 TX", "Denominator1 TX" }, \
|
||||
{ sname, "Denominator2 TX", "Denominator2 TX" }, \
|
||||
{ sname, "Denominator3 TX", "Denominator3 TX" }, \
|
||||
{ sname, "Denominator4 TX", "Denominator4 TX" }, \
|
||||
{ sname, "Denominator5 TX", "Denominator5 TX" }, \
|
||||
{ sname, "Denominator6 TX", "Denominator6 TX" }
|
||||
|
||||
static const struct snd_soc_dapm_route tegra186_arad_routes[] = {
|
||||
RATIO_GEN("Numerator1"),
|
||||
RATIO_GEN("Numerator2"),
|
||||
RATIO_GEN("Numerator3"),
|
||||
RATIO_GEN("Numerator4"),
|
||||
RATIO_GEN("Numerator5"),
|
||||
RATIO_GEN("Numerator6"),
|
||||
RATIO_GEN("Denominator1"),
|
||||
RATIO_GEN("Denominator2"),
|
||||
RATIO_GEN("Denominator3"),
|
||||
RATIO_GEN("Denominator4"),
|
||||
RATIO_GEN("Denominator5"),
|
||||
RATIO_GEN("Denominator6"),
|
||||
|
||||
PACKETIZER_ROUTE("Packetizer"),
|
||||
|
||||
{ "ARAD Transmit", NULL, "Packetizer" },
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new tegra186_arad_controls[] = {
|
||||
SOC_SINGLE_EXT("Lane1 enable", TEGRA186_ARAD_LANE_ENABLE, 0, 1, 0,
|
||||
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
||||
SOC_SINGLE_EXT("Lane2 enable", TEGRA186_ARAD_LANE_ENABLE, 1, 1, 0,
|
||||
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
||||
SOC_SINGLE_EXT("Lane3 enable", TEGRA186_ARAD_LANE_ENABLE, 2, 1, 0,
|
||||
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
||||
SOC_SINGLE_EXT("Lane4 enable", TEGRA186_ARAD_LANE_ENABLE, 3, 1, 0,
|
||||
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
||||
SOC_SINGLE_EXT("Lane5 enable", TEGRA186_ARAD_LANE_ENABLE, 4, 1, 0,
|
||||
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
||||
SOC_SINGLE_EXT("Lane6 enable", TEGRA186_ARAD_LANE_ENABLE, 5, 1, 0,
|
||||
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
||||
|
||||
SOC_SINGLE_EXT("Lane1 Ratio Int",
|
||||
TEGRA186_ARAD_LANE1_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_int, NULL),
|
||||
SOC_SINGLE_EXT("Lane1 Ratio Frac",
|
||||
TEGRA186_ARAD_LANE1_RATIO_FRACTIONAL_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_frac, NULL),
|
||||
SOC_SINGLE_EXT("Lane2 Ratio Int",
|
||||
TEGRA186_ARAD_LANE2_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_int, NULL),
|
||||
SOC_SINGLE_EXT("Lane2 Ratio Frac",
|
||||
TEGRA186_ARAD_LANE2_RATIO_FRACTIONAL_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_frac, NULL),
|
||||
SOC_SINGLE_EXT("Lane3 Ratio Int",
|
||||
TEGRA186_ARAD_LANE3_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_int, NULL),
|
||||
SOC_SINGLE_EXT("Lane3 Ratio Frac",
|
||||
TEGRA186_ARAD_LANE3_RATIO_FRACTIONAL_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_frac, NULL),
|
||||
SOC_SINGLE_EXT("Lane4 Ratio Int",
|
||||
TEGRA186_ARAD_LANE4_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_int, NULL),
|
||||
SOC_SINGLE_EXT("Lane4 Ratio Frac",
|
||||
TEGRA186_ARAD_LANE4_RATIO_FRACTIONAL_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_frac, NULL),
|
||||
SOC_SINGLE_EXT("Lane5 Ratio Int",
|
||||
TEGRA186_ARAD_LANE5_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_int, NULL),
|
||||
SOC_SINGLE_EXT("Lane5 Ratio Frac",
|
||||
TEGRA186_ARAD_LANE5_RATIO_FRACTIONAL_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_frac, NULL),
|
||||
SOC_SINGLE_EXT("Lane6 Ratio Int",
|
||||
TEGRA186_ARAD_LANE6_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_int, NULL),
|
||||
SOC_SINGLE_EXT("Lane6 Ratio Frac",
|
||||
TEGRA186_ARAD_LANE6_RATIO_FRACTIONAL_PART,
|
||||
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_arad_get_ratio_frac, NULL),
|
||||
};
|
||||
|
||||
static struct snd_soc_codec_driver tegra186_arad_codec = {
|
||||
.probe = tegra186_arad_codec_probe,
|
||||
.dapm_widgets = tegra186_arad_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(tegra186_arad_widgets),
|
||||
.dapm_routes = tegra186_arad_routes,
|
||||
.num_dapm_routes = ARRAY_SIZE(tegra186_arad_routes),
|
||||
.controls = tegra186_arad_controls,
|
||||
.num_controls = ARRAY_SIZE(tegra186_arad_controls),
|
||||
.idle_bias_off = 1,
|
||||
};
|
||||
|
||||
static bool tegra186_arad_wr_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if ((reg >= TEGRA186_ARAD_LANE_START) &&
|
||||
(reg <= TEGRA186_ARAD_LANE_LIMIT)) {
|
||||
reg -= TEGRA186_ARAD_LANE_START;
|
||||
reg %= TEGRA186_ARAD_LANE_STRIDE;
|
||||
reg += TEGRA186_ARAD_LANE_START;
|
||||
}
|
||||
|
||||
switch (reg) {
|
||||
case TEGRA186_ARAD_LANE_ENABLE:
|
||||
case TEGRA186_ARAD_LANE_SOFT_RESET:
|
||||
case TEGRA186_ARAD_LANE_INT_MASK:
|
||||
case TEGRA186_ARAD_LANE_INT_SET:
|
||||
case TEGRA186_ARAD_LANE_INT_CLEAR:
|
||||
case TEGRA186_ARAD_GLOBAL_SOFT_RESET:
|
||||
case TEGRA186_ARAD_SEND_RATIO:
|
||||
case TEGRA186_ARAD_CG:
|
||||
case TEGRA186_ARAD_CYA_GLOBAL:
|
||||
|
||||
case TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL:
|
||||
case TEGRA186_ARAD_LANE1_NUMERATOR_PRESCALAR:
|
||||
case TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL:
|
||||
case TEGRA186_ARAD_LANE1_DENOMINATOR_PRESCALAR:
|
||||
case TEGRA186_ARAD_LANE1_SERVO_LOOP_CONFIG:
|
||||
case TEGRA186_ARAD_LANE1_LOCK_UNLOCK_DETECTOR_CONFIG:
|
||||
case TEGRA186_ARAD_LANE1_ERROR_LOCK_THRESHOLD:
|
||||
case TEGRA186_ARAD_LANE1_ERROR_UNLOCK_THRESHOLD:
|
||||
case TEGRA186_ARAD_LANE1_RATIO_CALCULATOR_CONFIG:
|
||||
case TEGRA186_ARAD_LANE1_CYA:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
};
|
||||
}
|
||||
|
||||
static bool tegra186_arad_rd_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if ((reg >= TEGRA186_ARAD_LANE_START) &&
|
||||
(reg <= TEGRA186_ARAD_LANE_LIMIT)) {
|
||||
reg -= TEGRA186_ARAD_LANE_START;
|
||||
reg %= TEGRA186_ARAD_LANE_STRIDE;
|
||||
reg += TEGRA186_ARAD_LANE_START;
|
||||
}
|
||||
|
||||
switch (reg) {
|
||||
case TEGRA186_ARAD_LANE_ENABLE:
|
||||
case TEGRA186_ARAD_LANE_STATUS:
|
||||
case TEGRA186_ARAD_LANE_SOFT_RESET:
|
||||
case TEGRA186_ARAD_LANE_INT_STATUS:
|
||||
case TEGRA186_ARAD_LANE_INT_MASK:
|
||||
case TEGRA186_ARAD_LANE_INT_SET:
|
||||
case TEGRA186_ARAD_LANE_INT_CLEAR:
|
||||
case TEGRA186_ARAD_GLOBAL_SOFT_RESET:
|
||||
case TEGRA186_ARAD_CG:
|
||||
case TEGRA186_ARAD_STATUS:
|
||||
case TEGRA186_ARAD_CYA_GLOBAL:
|
||||
|
||||
case TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL:
|
||||
case TEGRA186_ARAD_LANE1_NUMERATOR_PRESCALAR:
|
||||
case TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL:
|
||||
case TEGRA186_ARAD_LANE1_DENOMINATOR_PRESCALAR:
|
||||
case TEGRA186_ARAD_LANE1_RATIO_INTEGER_PART:
|
||||
case TEGRA186_ARAD_LANE1_RATIO_FRACTIONAL_PART:
|
||||
case TEGRA186_ARAD_LANE1_PERIOD_COUNT:
|
||||
case TEGRA186_ARAD_LANE1_SERVO_LOOP_CONFIG:
|
||||
case TEGRA186_ARAD_LANE1_LOCK_UNLOCK_DETECTOR_CONFIG:
|
||||
case TEGRA186_ARAD_LANE1_ERROR_LOCK_THRESHOLD:
|
||||
case TEGRA186_ARAD_LANE1_ERROR_UNLOCK_THRESHOLD:
|
||||
case TEGRA186_ARAD_LANE1_RATIO_CALCULATOR_CONFIG:
|
||||
case TEGRA186_ARAD_LANE1_CYA:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
};
|
||||
}
|
||||
|
||||
static bool tegra186_arad_volatile_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if ((reg >= TEGRA186_ARAD_LANE_START) &&
|
||||
(reg <= TEGRA186_ARAD_LANE_LIMIT)) {
|
||||
reg -= TEGRA186_ARAD_LANE_START;
|
||||
reg %= TEGRA186_ARAD_LANE_STRIDE;
|
||||
reg += TEGRA186_ARAD_LANE_START;
|
||||
}
|
||||
|
||||
switch (reg) {
|
||||
case TEGRA186_ARAD_LANE_STATUS:
|
||||
case TEGRA186_ARAD_LANE_INT_STATUS:
|
||||
case TEGRA186_ARAD_STATUS:
|
||||
|
||||
case TEGRA186_ARAD_LANE1_RATIO_INTEGER_PART:
|
||||
case TEGRA186_ARAD_LANE1_RATIO_FRACTIONAL_PART:
|
||||
case TEGRA186_ARAD_LANE1_PERIOD_COUNT:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
};
|
||||
}
|
||||
|
||||
static const struct regmap_config tegra186_arad_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = TEGRA186_ARAD_TX_CIF_CTRL,
|
||||
.writeable_reg = tegra186_arad_wr_reg,
|
||||
.readable_reg = tegra186_arad_rd_reg,
|
||||
.volatile_reg = tegra186_arad_volatile_reg,
|
||||
.reg_defaults = tegra186_arad_reg_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(tegra186_arad_reg_defaults),
|
||||
.cache_type = REGCACHE_FLAT,
|
||||
};
|
||||
|
||||
static const struct tegra186_arad_soc_data soc_data_tegra186 = {
|
||||
.set_audio_cif = tegra210_xbar_set_cif,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra186_arad_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra186-arad", .data = &soc_data_tegra186 },
|
||||
{},
|
||||
};
|
||||
|
||||
static int tegra186_arad_platform_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra186_arad *arad;
|
||||
struct resource *mem, *memregion;
|
||||
void __iomem *regs;
|
||||
int ret = 0;
|
||||
const struct of_device_id *match;
|
||||
struct tegra186_arad_soc_data *soc_data;
|
||||
|
||||
match = of_match_device(tegra186_arad_of_match, &pdev->dev);
|
||||
if (!match) {
|
||||
dev_err(&pdev->dev, "Error: No device match found\n");
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
soc_data = (struct tegra186_arad_soc_data *)match->data;
|
||||
|
||||
arad = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct tegra186_arad), GFP_KERNEL);
|
||||
if (!arad) {
|
||||
dev_err(&pdev->dev, "Can't allocate tegra210_arad\n");
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
dev_set_drvdata(&pdev->dev, arad);
|
||||
|
||||
arad->soc_data = soc_data;
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem) {
|
||||
dev_err(&pdev->dev, "No memory resource\n");
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
|
||||
memregion = devm_request_mem_region(&pdev->dev, mem->start,
|
||||
resource_size(mem), DRV_NAME);
|
||||
if (!memregion) {
|
||||
dev_err(&pdev->dev, "Memory region already claimed\n");
|
||||
ret = -EBUSY;
|
||||
goto err;
|
||||
}
|
||||
|
||||
regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
|
||||
if (!regs) {
|
||||
dev_err(&pdev->dev, "ioremap failed\n");
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
arad->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
||||
&tegra186_arad_regmap_config);
|
||||
if (IS_ERR(arad->regmap)) {
|
||||
dev_err(&pdev->dev, "regmap init failed\n");
|
||||
ret = PTR_ERR(arad->regmap);
|
||||
goto err;
|
||||
}
|
||||
regcache_cache_only(arad->regmap, true);
|
||||
|
||||
if (of_property_read_u32(pdev->dev.of_node,
|
||||
"nvidia,ahub-arad-id",
|
||||
&pdev->dev.id) < 0) {
|
||||
dev_err(&pdev->dev,
|
||||
"Missing property nvidia,ahub-arad-id\n");
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
if (!pm_runtime_enabled(&pdev->dev)) {
|
||||
ret = tegra186_arad_runtime_resume(&pdev->dev);
|
||||
if (ret)
|
||||
goto err_pm_disable;
|
||||
}
|
||||
|
||||
ret = snd_soc_register_codec(&pdev->dev, &tegra186_arad_codec,
|
||||
tegra186_arad_dais,
|
||||
ARRAY_SIZE(tegra186_arad_dais));
|
||||
if (ret != 0) {
|
||||
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
|
||||
goto err_suspend;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_suspend:
|
||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||
tegra186_arad_runtime_suspend(&pdev->dev);
|
||||
err_pm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra186_arad_platform_remove(struct platform_device *pdev)
|
||||
{
|
||||
snd_soc_unregister_codec(&pdev->dev);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||
tegra186_arad_runtime_suspend(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops tegra186_arad_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(tegra186_arad_runtime_suspend,
|
||||
tegra186_arad_runtime_resume, NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(tegra186_arad_suspend, NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver tegra186_arad_driver = {
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra186_arad_of_match,
|
||||
.pm = &tegra186_arad_pm_ops,
|
||||
},
|
||||
.probe = tegra186_arad_platform_probe,
|
||||
.remove = tegra186_arad_platform_remove,
|
||||
};
|
||||
module_platform_driver(tegra186_arad_driver)
|
||||
|
||||
MODULE_AUTHOR("Junghyun Kim <juskim@nvidia.com>");
|
||||
MODULE_DESCRIPTION("Tegra186 ARAD ASoC driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
MODULE_DEVICE_TABLE(of, tegra186_arad_of_match);
|
||||
937
sound/soc/tegra-alt/tegra186_asrc_alt.c
Normal file
937
sound/soc/tegra-alt/tegra186_asrc_alt.c
Normal file
@@ -0,0 +1,937 @@
|
||||
/*
|
||||
* tegra186_asrc_alt.c - Tegra186 ASRC driver
|
||||
*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
#include <sound/core.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <sound/soc.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/of_device.h>
|
||||
|
||||
#include "tegra210_xbar_alt.h"
|
||||
#include "tegra186_asrc_alt.h"
|
||||
|
||||
#define DRV_NAME "tegra186-asrc"
|
||||
|
||||
#define RATIO_ARAD 0
|
||||
#define RATIO_SW 1
|
||||
|
||||
#define ASRC_STREAM_SOURCE_SELECT(id) \
|
||||
(TEGRA186_ASRC_STREAM1_CONFIG + id*TEGRA186_ASRC_STREAM_STRIDE)
|
||||
|
||||
#define ASRC_STREAM_REG(reg, id) (reg + (id * TEGRA186_ASRC_STREAM_STRIDE))
|
||||
|
||||
#define ASRC_STREAM_REG_DEFAULTS(id) \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_CONFIG, id), ((id+1)<<4)}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART, id), 0x1}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART, id), 0x0}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_MUTE_UNMUTE_DURATION, id), 0x400}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_RX_CIF_CTRL, id), 0x7700}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_TX_CIF_CTRL, id), 0x7700}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_ENABLE, id), 0x0}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_SOFT_RESET, id), 0x0}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_STATEBUF_ADDR, id), 0x0}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_STATEBUF_CONFIG, id), 0x445}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_INSAMPLEBUF_ADDR, id), 0x0}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_INSAMPLEBUF_CONFIG, id), 0x64}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_OUTSAMPLEBUF_ADDR, id), 0x4b0}, \
|
||||
{ ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_OUTSAMPLEBUF_CONFIG, id), 0x64}
|
||||
|
||||
static const struct reg_default tegra186_asrc_reg_defaults[] = {
|
||||
ASRC_STREAM_REG_DEFAULTS(0),
|
||||
ASRC_STREAM_REG_DEFAULTS(1),
|
||||
ASRC_STREAM_REG_DEFAULTS(2),
|
||||
ASRC_STREAM_REG_DEFAULTS(3),
|
||||
ASRC_STREAM_REG_DEFAULTS(4),
|
||||
ASRC_STREAM_REG_DEFAULTS(5),
|
||||
|
||||
{ TEGRA186_ASRC_GLOBAL_ENB, 0},
|
||||
{ TEGRA186_ASRC_GLOBAL_SOFT_RESET, 0},
|
||||
{ TEGRA186_ASRC_GLOBAL_CG, 0},
|
||||
{ TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, 0},
|
||||
{ TEGRA186_ASRC_GLOBAL_SCRATCH_CONFIG, 0x0c207980},
|
||||
{ TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL, 0x00115500},
|
||||
{ TEGRA186_ASRC_RATIO_UPD_RX_STATUS, 0},
|
||||
{ TEGRA186_ASRC_GLOBAL_STATUS, 0},
|
||||
{ TEGRA186_ASRC_GLOBAL_STREAM_ENABLE_STATUS, 0},
|
||||
{ TEGRA186_ASRC_GLOBAL_INT_MASK, 0x0},
|
||||
{ TEGRA186_ASRC_GLOBAL_INT_SET, 0x0},
|
||||
{ TEGRA186_ASRC_GLOBAL_INT_CLEAR, 0x0},
|
||||
{ TEGRA186_ASRC_GLOBAL_APR_CTRL, 0x0},
|
||||
{ TEGRA186_ASRC_GLOBAL_APR_CTRL_ACCESS_CTRL, 0x0},
|
||||
{ TEGRA186_ASRC_GLOBAL_DISARM_APR, 0x0},
|
||||
{ TEGRA186_ASRC_GLOBAL_DISARM_APR_ACCESS_CTRL, 0x0},
|
||||
{ TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS, 0x0},
|
||||
{ TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS_CTRL, 0x0},
|
||||
{ TEGRA186_ASRC_CYA, 0x0},
|
||||
};
|
||||
|
||||
static int tegra186_asrc_get_ratio_lock_status(struct tegra186_asrc *asrc,
|
||||
unsigned int lane_id)
|
||||
{
|
||||
int val;
|
||||
|
||||
regmap_read(asrc->regmap,
|
||||
ASRC_STREAM_REG(
|
||||
TEGRA186_ASRC_STREAM1_RATIO_LOCK_STATUS, lane_id),
|
||||
&val);
|
||||
|
||||
return val & 0x1;
|
||||
}
|
||||
|
||||
static void tegra186_asrc_set_ratio_lock_status(struct tegra186_asrc *asrc,
|
||||
unsigned int lane_id)
|
||||
{
|
||||
int dcnt = 10;
|
||||
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(
|
||||
TEGRA186_ASRC_STREAM1_RATIO_LOCK_STATUS, lane_id), 0);
|
||||
|
||||
while (tegra186_asrc_get_ratio_lock_status(asrc, lane_id) && dcnt--)
|
||||
udelay(100);
|
||||
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(
|
||||
TEGRA186_ASRC_STREAM1_RATIO_LOCK_STATUS, lane_id), 1);
|
||||
}
|
||||
|
||||
static int tegra186_asrc_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct tegra186_asrc *asrc = dev_get_drvdata(dev);
|
||||
|
||||
regcache_cache_only(asrc->regmap, true);
|
||||
|
||||
pm_runtime_put_sync(dev->parent);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct tegra186_asrc *asrc = dev_get_drvdata(dev);
|
||||
int ret, lane_id;
|
||||
|
||||
ret = pm_runtime_get_sync(dev->parent);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "parent get_sync failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
regcache_cache_only(asrc->regmap, false);
|
||||
regcache_sync(asrc->regmap);
|
||||
|
||||
for (lane_id = 0; lane_id < 6; lane_id++) {
|
||||
if (asrc->lane[lane_id].ratio_source == RATIO_SW) {
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(
|
||||
TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART,
|
||||
lane_id),
|
||||
asrc->lane[lane_id].int_part);
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(
|
||||
TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART,
|
||||
lane_id),
|
||||
asrc->lane[lane_id].frac_part);
|
||||
tegra186_asrc_set_ratio_lock_status(asrc, lane_id);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int tegra186_asrc_suspend(struct device *dev)
|
||||
{
|
||||
struct tegra186_asrc *asrc = dev_get_drvdata(dev);
|
||||
|
||||
regcache_mark_dirty(asrc->regmap);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int tegra186_asrc_set_audio_cif(struct tegra186_asrc *asrc,
|
||||
struct snd_pcm_hw_params *params,
|
||||
unsigned int reg)
|
||||
{
|
||||
int channels, audio_bits;
|
||||
struct tegra210_xbar_cif_conf cif_conf;
|
||||
|
||||
memset(&cif_conf, 0, sizeof(struct tegra210_xbar_cif_conf));
|
||||
|
||||
channels = params_channels(params);
|
||||
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
audio_bits = TEGRA210_AUDIOCIF_BITS_16;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
audio_bits = TEGRA210_AUDIOCIF_BITS_24;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S32_LE:
|
||||
audio_bits = TEGRA210_AUDIOCIF_BITS_32;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
cif_conf.audio_channels = channels;
|
||||
cif_conf.client_channels = channels;
|
||||
cif_conf.audio_bits = audio_bits;
|
||||
cif_conf.client_bits = audio_bits;
|
||||
|
||||
asrc->soc_data->set_audio_cif(asrc->regmap, reg, &cif_conf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_in_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct device *dev = dai->dev;
|
||||
struct tegra186_asrc *asrc = snd_soc_dai_get_drvdata(dai);
|
||||
int ret;
|
||||
|
||||
/* set threshold */
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_RX_THRESHOLD, dai->id),
|
||||
0x00201002);
|
||||
|
||||
ret = tegra186_asrc_set_audio_cif(asrc, params,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_RX_CIF_CTRL, dai->id));
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't set ASRC RX%d CIF: %d\n", dai->id, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_out_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct device *dev = dai->dev;
|
||||
struct tegra186_asrc *asrc = snd_soc_dai_get_drvdata(dai);
|
||||
int ret, lane_id = dai->id - 7, dcnt = 10;
|
||||
|
||||
regmap_update_bits(asrc->regmap,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_CONFIG, lane_id),
|
||||
1, asrc->lane[lane_id].ratio_source);
|
||||
|
||||
ret = tegra186_asrc_set_audio_cif(asrc, params,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_TX_CIF_CTRL, lane_id));
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't set ASRC TX%d CIF: %d\n", lane_id, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* set ENABLE_HW_RATIO_COMP */
|
||||
regmap_update_bits(asrc->regmap,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_CONFIG, lane_id),
|
||||
TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_MASK,
|
||||
TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_ENABLE);
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(
|
||||
TEGRA186_ASRC_STREAM1_RATIO_COMP, lane_id),
|
||||
0xaaaa);
|
||||
|
||||
/* set lock */
|
||||
if (asrc->lane[lane_id].ratio_source == RATIO_SW) {
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(
|
||||
TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART,
|
||||
lane_id),
|
||||
asrc->lane[lane_id].int_part);
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(
|
||||
TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART, lane_id),
|
||||
asrc->lane[lane_id].frac_part);
|
||||
tegra186_asrc_set_ratio_lock_status(asrc, lane_id);
|
||||
} else
|
||||
while (!tegra186_asrc_get_ratio_lock_status(asrc, lane_id) &&
|
||||
dcnt--)
|
||||
udelay(100);
|
||||
|
||||
/* set threshold */
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_TX_THRESHOLD, lane_id),
|
||||
0x00201002);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_get_ratio_source(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct soc_enum *asrc_private =
|
||||
(struct soc_enum *)kcontrol->private_value;
|
||||
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
||||
struct tegra186_asrc *asrc = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
|
||||
|
||||
/* get the source of a lane in asrc */
|
||||
ucontrol->value.integer.value[0] = asrc->lane[id].ratio_source;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_put_ratio_source(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct soc_enum *asrc_private =
|
||||
(struct soc_enum *)kcontrol->private_value;
|
||||
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
||||
struct tegra186_asrc *asrc = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
|
||||
|
||||
/* update the source of the lane */
|
||||
asrc->lane[id].ratio_source = ucontrol->value.integer.value[0];
|
||||
regmap_update_bits(asrc->regmap, asrc_private->reg,
|
||||
TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK,
|
||||
asrc->lane[id].ratio_source);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_get_enable_stream(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct soc_mixer_control *asrc_private =
|
||||
(struct soc_mixer_control *)kcontrol->private_value;
|
||||
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
||||
struct tegra186_asrc *asrc = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int enable;
|
||||
|
||||
regmap_read(asrc->regmap, asrc_private->reg, &enable);
|
||||
ucontrol->value.integer.value[0] = enable;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_put_enable_stream(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct soc_mixer_control *asrc_private =
|
||||
(struct soc_mixer_control *)kcontrol->private_value;
|
||||
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
||||
struct tegra186_asrc *asrc = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int enable = 0;
|
||||
|
||||
enable = ucontrol->value.integer.value[0];
|
||||
regmap_write(asrc->regmap, asrc_private->reg, enable);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_get_ratio_int(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct soc_mixer_control *asrc_private =
|
||||
(struct soc_mixer_control *)kcontrol->private_value;
|
||||
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
||||
struct tegra186_asrc *asrc = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
|
||||
|
||||
regmap_read(asrc->regmap,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART, id),
|
||||
&asrc->lane[id].int_part);
|
||||
ucontrol->value.integer.value[0] = asrc->lane[id].int_part;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_put_ratio_int(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct soc_mixer_control *asrc_private =
|
||||
(struct soc_mixer_control *)kcontrol->private_value;
|
||||
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
||||
struct tegra186_asrc *asrc = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
|
||||
|
||||
asrc->lane[id].int_part = ucontrol->value.integer.value[0];
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART, id),
|
||||
asrc->lane[id].int_part);
|
||||
tegra186_asrc_set_ratio_lock_status(asrc, id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_get_ratio_frac(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct soc_mixer_control *asrc_private =
|
||||
(struct soc_mixer_control *)kcontrol->private_value;
|
||||
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
||||
struct tegra186_asrc *asrc = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
|
||||
|
||||
regmap_read(asrc->regmap,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART, id),
|
||||
&asrc->lane[id].frac_part);
|
||||
ucontrol->value.integer.value[0] = asrc->lane[id].frac_part;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_put_ratio_frac(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct soc_mixer_control *asrc_private =
|
||||
(struct soc_mixer_control *)kcontrol->private_value;
|
||||
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
||||
struct tegra186_asrc *asrc = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
|
||||
|
||||
asrc->lane[id].frac_part = ucontrol->value.integer.value[0];
|
||||
regmap_write(asrc->regmap,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART, id),
|
||||
asrc->lane[id].frac_part);
|
||||
tegra186_asrc_set_ratio_lock_status(asrc, id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_codec_probe(struct snd_soc_codec *codec)
|
||||
{
|
||||
struct tegra186_asrc *asrc = snd_soc_codec_get_drvdata(codec);
|
||||
|
||||
codec->control_data = asrc->regmap;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct snd_soc_dai_ops tegra186_asrc_in_dai_ops = {
|
||||
.hw_params = tegra186_asrc_in_hw_params,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_ops tegra186_asrc_out_dai_ops = {
|
||||
.hw_params = tegra186_asrc_out_hw_params,
|
||||
};
|
||||
|
||||
#define IN_DAI(sname, id, dai_ops) \
|
||||
{ \
|
||||
.name = #sname #id, \
|
||||
.playback = { \
|
||||
.stream_name = #sname #id " Receive", \
|
||||
.channels_min = 1, \
|
||||
.channels_max = 12, \
|
||||
.rates = SNDRV_PCM_RATE_8000_192000, \
|
||||
.formats = SNDRV_PCM_FMTBIT_S8 | \
|
||||
SNDRV_PCM_FMTBIT_S16_LE | \
|
||||
SNDRV_PCM_FMTBIT_S24_LE | \
|
||||
SNDRV_PCM_FMTBIT_S32_LE, \
|
||||
}, \
|
||||
.ops = dai_ops, \
|
||||
}
|
||||
|
||||
#define OUT_DAI(sname, id, dai_ops) \
|
||||
{ \
|
||||
.name = #sname #id, \
|
||||
.capture = { \
|
||||
.stream_name = #sname #id " Transmit", \
|
||||
.channels_min = 1, \
|
||||
.channels_max = 12, \
|
||||
.rates = SNDRV_PCM_RATE_8000_192000, \
|
||||
.formats = SNDRV_PCM_FMTBIT_S8 | \
|
||||
SNDRV_PCM_FMTBIT_S16_LE | \
|
||||
SNDRV_PCM_FMTBIT_S24_LE | \
|
||||
SNDRV_PCM_FMTBIT_S32_LE, \
|
||||
}, \
|
||||
.ops = dai_ops, \
|
||||
}
|
||||
|
||||
static struct snd_soc_dai_driver tegra186_asrc_dais[] = {
|
||||
IN_DAI(RX, 1, &tegra186_asrc_in_dai_ops),
|
||||
IN_DAI(RX, 2, &tegra186_asrc_in_dai_ops),
|
||||
IN_DAI(RX, 3, &tegra186_asrc_in_dai_ops),
|
||||
IN_DAI(RX, 4, &tegra186_asrc_in_dai_ops),
|
||||
IN_DAI(RX, 5, &tegra186_asrc_in_dai_ops),
|
||||
IN_DAI(RX, 6, &tegra186_asrc_in_dai_ops),
|
||||
IN_DAI(RX, 7, &tegra186_asrc_in_dai_ops),
|
||||
OUT_DAI(TX, 1, &tegra186_asrc_out_dai_ops),
|
||||
OUT_DAI(TX, 2, &tegra186_asrc_out_dai_ops),
|
||||
OUT_DAI(TX, 3, &tegra186_asrc_out_dai_ops),
|
||||
OUT_DAI(TX, 4, &tegra186_asrc_out_dai_ops),
|
||||
OUT_DAI(TX, 5, &tegra186_asrc_out_dai_ops),
|
||||
OUT_DAI(TX, 6, &tegra186_asrc_out_dai_ops),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_widget tegra186_asrc_widgets[] = {
|
||||
SND_SOC_DAPM_AIF_IN("RX1", NULL, 0, SND_SOC_NOPM,
|
||||
0, 0),
|
||||
SND_SOC_DAPM_AIF_IN("RX2", NULL, 0, SND_SOC_NOPM,
|
||||
0, 0),
|
||||
SND_SOC_DAPM_AIF_IN("RX3", NULL, 0, SND_SOC_NOPM,
|
||||
0, 0),
|
||||
SND_SOC_DAPM_AIF_IN("RX4", NULL, 0, SND_SOC_NOPM,
|
||||
0, 0),
|
||||
SND_SOC_DAPM_AIF_IN("RX5", NULL, 0, SND_SOC_NOPM,
|
||||
0, 0),
|
||||
SND_SOC_DAPM_AIF_IN("RX6", NULL, 0, SND_SOC_NOPM,
|
||||
0, 0),
|
||||
SND_SOC_DAPM_AIF_IN("RX7", NULL, 0, SND_SOC_NOPM,
|
||||
0, 0),
|
||||
SND_SOC_DAPM_AIF_OUT("TX1", NULL, 0, TEGRA186_ASRC_STREAM1_ENABLE,
|
||||
TEGRA186_ASRC_STREAM_EN_SHIFT, 0),
|
||||
SND_SOC_DAPM_AIF_OUT("TX2", NULL, 0, TEGRA186_ASRC_STREAM2_ENABLE,
|
||||
TEGRA186_ASRC_STREAM_EN_SHIFT, 0),
|
||||
SND_SOC_DAPM_AIF_OUT("TX3", NULL, 0, TEGRA186_ASRC_STREAM3_ENABLE,
|
||||
TEGRA186_ASRC_STREAM_EN_SHIFT, 0),
|
||||
SND_SOC_DAPM_AIF_OUT("TX4", NULL, 0, TEGRA186_ASRC_STREAM4_ENABLE,
|
||||
TEGRA186_ASRC_STREAM_EN_SHIFT, 0),
|
||||
SND_SOC_DAPM_AIF_OUT("TX5", NULL, 0, TEGRA186_ASRC_STREAM5_ENABLE,
|
||||
TEGRA186_ASRC_STREAM_EN_SHIFT, 0),
|
||||
SND_SOC_DAPM_AIF_OUT("TX6", NULL, 0, TEGRA186_ASRC_STREAM6_ENABLE,
|
||||
TEGRA186_ASRC_STREAM_EN_SHIFT, 0),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route tegra186_asrc_routes[] = {
|
||||
{ "RX1", NULL, "RX1 Receive" },
|
||||
{ "TX1", NULL, "RX1" },
|
||||
{ "TX1 Transmit", NULL, "TX1" },
|
||||
{ "RX2", NULL, "RX2 Receive" },
|
||||
{ "TX2", NULL, "RX2" },
|
||||
{ "TX2 Transmit", NULL, "TX2" },
|
||||
{ "RX3", NULL, "RX3 Receive" },
|
||||
{ "TX3", NULL, "RX3" },
|
||||
{ "TX3 Transmit", NULL, "TX3" },
|
||||
{ "RX4", NULL, "RX4 Receive" },
|
||||
{ "TX4", NULL, "RX4" },
|
||||
{ "TX4 Transmit", NULL, "TX4" },
|
||||
{ "RX5", NULL, "RX5 Receive" },
|
||||
{ "TX5", NULL, "RX5" },
|
||||
{ "TX5 Transmit", NULL, "TX5" },
|
||||
{ "RX6", NULL, "RX6 Receive" },
|
||||
{ "TX6", NULL, "RX6" },
|
||||
{ "TX6 Transmit", NULL, "TX6" },
|
||||
{ "RX7", NULL, "RX7 Receive" },
|
||||
};
|
||||
|
||||
static const char * const tegra186_asrc_ratio_source_text[] = {
|
||||
"ARAD",
|
||||
"SW",
|
||||
};
|
||||
|
||||
#define ASRC_SOURCE_DECL(name, id) \
|
||||
static const struct soc_enum name = \
|
||||
SOC_ENUM_SINGLE(ASRC_STREAM_SOURCE_SELECT(id), \
|
||||
0, 2, tegra186_asrc_ratio_source_text)
|
||||
|
||||
ASRC_SOURCE_DECL(src_select1, 0);
|
||||
ASRC_SOURCE_DECL(src_select2, 1);
|
||||
ASRC_SOURCE_DECL(src_select3, 2);
|
||||
ASRC_SOURCE_DECL(src_select4, 3);
|
||||
ASRC_SOURCE_DECL(src_select5, 4);
|
||||
ASRC_SOURCE_DECL(src_select6, 5);
|
||||
|
||||
static const struct snd_kcontrol_new tegra186_asrc_controls[] = {
|
||||
SOC_SINGLE_EXT("Ratio1 Int", TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
|
||||
SOC_SINGLE_EXT("Ratio1 Frac", TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
|
||||
SOC_SINGLE_EXT("Ratio2 Int", TEGRA186_ASRC_STREAM2_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
|
||||
SOC_SINGLE_EXT("Ratio2 Frac", TEGRA186_ASRC_STREAM2_RATIO_FRAC_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
|
||||
SOC_SINGLE_EXT("Ratio3 Int", TEGRA186_ASRC_STREAM3_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
|
||||
SOC_SINGLE_EXT("Ratio3 Frac", TEGRA186_ASRC_STREAM3_RATIO_FRAC_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
|
||||
SOC_SINGLE_EXT("Ratio4 Int", TEGRA186_ASRC_STREAM4_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
|
||||
SOC_SINGLE_EXT("Ratio4 Frac", TEGRA186_ASRC_STREAM4_RATIO_FRAC_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
|
||||
SOC_SINGLE_EXT("Ratio5 Int", TEGRA186_ASRC_STREAM5_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
|
||||
SOC_SINGLE_EXT("Ratio5 Frac", TEGRA186_ASRC_STREAM5_RATIO_FRAC_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
|
||||
SOC_SINGLE_EXT("Ratio6 Int", TEGRA186_ASRC_STREAM6_RATIO_INTEGER_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
|
||||
SOC_SINGLE_EXT("Ratio6 Frac", TEGRA186_ASRC_STREAM6_RATIO_FRAC_PART,
|
||||
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
|
||||
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
|
||||
|
||||
SOC_ENUM_EXT("Ratio1 SRC", src_select1,
|
||||
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
|
||||
SOC_ENUM_EXT("Ratio2 SRC", src_select2,
|
||||
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
|
||||
SOC_ENUM_EXT("Ratio3 SRC", src_select3,
|
||||
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
|
||||
SOC_ENUM_EXT("Ratio4 SRC", src_select4,
|
||||
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
|
||||
SOC_ENUM_EXT("Ratio5 SRC", src_select5,
|
||||
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
|
||||
SOC_ENUM_EXT("Ratio6 SRC", src_select6,
|
||||
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
|
||||
|
||||
SOC_SINGLE_EXT("Stream1 Enable",
|
||||
TEGRA186_ASRC_STREAM1_ENABLE, 0, 1, 0,
|
||||
tegra186_asrc_get_enable_stream, tegra186_asrc_put_enable_stream),
|
||||
SOC_SINGLE_EXT("Stream2 Enable",
|
||||
TEGRA186_ASRC_STREAM2_ENABLE, 0, 1, 0,
|
||||
tegra186_asrc_get_enable_stream, tegra186_asrc_put_enable_stream),
|
||||
SOC_SINGLE_EXT("Stream3 Enable",
|
||||
TEGRA186_ASRC_STREAM3_ENABLE, 0, 1, 0,
|
||||
tegra186_asrc_get_enable_stream, tegra186_asrc_put_enable_stream),
|
||||
SOC_SINGLE_EXT("Stream4 Enable",
|
||||
TEGRA186_ASRC_STREAM4_ENABLE, 0, 1, 0,
|
||||
tegra186_asrc_get_enable_stream, tegra186_asrc_put_enable_stream),
|
||||
SOC_SINGLE_EXT("Stream5 Enable",
|
||||
TEGRA186_ASRC_STREAM5_ENABLE, 0, 1, 0,
|
||||
tegra186_asrc_get_enable_stream, tegra186_asrc_put_enable_stream),
|
||||
SOC_SINGLE_EXT("Stream6 Enable",
|
||||
TEGRA186_ASRC_STREAM6_ENABLE, 0, 1, 0,
|
||||
tegra186_asrc_get_enable_stream, tegra186_asrc_put_enable_stream),
|
||||
};
|
||||
|
||||
static struct snd_soc_codec_driver tegra186_asrc_codec = {
|
||||
.probe = tegra186_asrc_codec_probe,
|
||||
.dapm_widgets = tegra186_asrc_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(tegra186_asrc_widgets),
|
||||
.dapm_routes = tegra186_asrc_routes,
|
||||
.num_dapm_routes = ARRAY_SIZE(tegra186_asrc_routes),
|
||||
.controls = tegra186_asrc_controls,
|
||||
.num_controls = ARRAY_SIZE(tegra186_asrc_controls),
|
||||
.idle_bias_off = 1,
|
||||
};
|
||||
|
||||
static bool tegra186_asrc_wr_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if (reg < TEGRA186_ASRC_STREAM_LIMIT)
|
||||
reg %= TEGRA186_ASRC_STREAM_STRIDE;
|
||||
|
||||
switch (reg) {
|
||||
case TEGRA186_ASRC_STREAM1_CONFIG:
|
||||
case TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART:
|
||||
case TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART:
|
||||
case TEGRA186_ASRC_STREAM1_RATIO_LOCK_STATUS:
|
||||
case TEGRA186_ASRC_STREAM1_MUTE_UNMUTE_DURATION:
|
||||
case TEGRA186_ASRC_STREAM1_RATIO_COMP:
|
||||
case TEGRA186_ASRC_STREAM1_RX_CIF_CTRL:
|
||||
case TEGRA186_ASRC_STREAM1_TX_CIF_CTRL:
|
||||
case TEGRA186_ASRC_STREAM1_ENABLE:
|
||||
case TEGRA186_ASRC_STREAM1_SOFT_RESET:
|
||||
case TEGRA186_ASRC_STREAM1_STATEBUF_ADDR:
|
||||
case TEGRA186_ASRC_STREAM1_STATEBUF_CONFIG:
|
||||
case TEGRA186_ASRC_STREAM1_INSAMPLEBUF_ADDR:
|
||||
case TEGRA186_ASRC_STREAM1_INSAMPLEBUF_CONFIG:
|
||||
case TEGRA186_ASRC_STREAM1_OUTSAMPLEBUF_ADDR:
|
||||
case TEGRA186_ASRC_STREAM1_OUTSAMPLEBUF_CONFIG:
|
||||
|
||||
case TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL:
|
||||
|
||||
case TEGRA186_ASRC_GLOBAL_ENB:
|
||||
case TEGRA186_ASRC_GLOBAL_SOFT_RESET:
|
||||
case TEGRA186_ASRC_GLOBAL_CG:
|
||||
case TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR:
|
||||
case TEGRA186_ASRC_GLOBAL_SCRATCH_CONFIG:
|
||||
|
||||
case TEGRA186_ASRC_GLOBAL_INT_MASK:
|
||||
case TEGRA186_ASRC_GLOBAL_INT_SET:
|
||||
case TEGRA186_ASRC_GLOBAL_INT_CLEAR:
|
||||
case TEGRA186_ASRC_GLOBAL_APR_CTRL:
|
||||
case TEGRA186_ASRC_GLOBAL_APR_CTRL_ACCESS_CTRL:
|
||||
case TEGRA186_ASRC_GLOBAL_DISARM_APR:
|
||||
case TEGRA186_ASRC_GLOBAL_DISARM_APR_ACCESS_CTRL:
|
||||
case TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS:
|
||||
case TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS_CTRL:
|
||||
case TEGRA186_ASRC_CYA:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
};
|
||||
}
|
||||
|
||||
static bool tegra186_asrc_rd_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if (reg < TEGRA186_ASRC_STREAM_LIMIT)
|
||||
reg %= TEGRA186_ASRC_STREAM_STRIDE;
|
||||
|
||||
switch (reg) {
|
||||
case TEGRA186_ASRC_STREAM1_CONFIG:
|
||||
case TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART:
|
||||
case TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART:
|
||||
case TEGRA186_ASRC_STREAM1_RATIO_LOCK_STATUS:
|
||||
case TEGRA186_ASRC_STREAM1_MUTE_UNMUTE_DURATION:
|
||||
case TEGRA186_ASRC_STREAM1_RATIO_COMP:
|
||||
case TEGRA186_ASRC_STREAM1_RX_STATUS:
|
||||
case TEGRA186_ASRC_STREAM1_RX_CIF_CTRL:
|
||||
case TEGRA186_ASRC_STREAM1_TX_STATUS:
|
||||
case TEGRA186_ASRC_STREAM1_TX_CIF_CTRL:
|
||||
case TEGRA186_ASRC_STREAM1_ENABLE:
|
||||
case TEGRA186_ASRC_STREAM1_SOFT_RESET:
|
||||
case TEGRA186_ASRC_STREAM1_STATUS:
|
||||
case TEGRA186_ASRC_STREAM1_BUFFER_STATUS:
|
||||
case TEGRA186_ASRC_STREAM1_CONFIG_ERR_TYPE:
|
||||
case TEGRA186_ASRC_STREAM1_STATEBUF_ADDR:
|
||||
case TEGRA186_ASRC_STREAM1_STATEBUF_CONFIG:
|
||||
case TEGRA186_ASRC_STREAM1_INSAMPLEBUF_ADDR:
|
||||
case TEGRA186_ASRC_STREAM1_INSAMPLEBUF_CONFIG:
|
||||
case TEGRA186_ASRC_STREAM1_OUTSAMPLEBUF_ADDR:
|
||||
case TEGRA186_ASRC_STREAM1_OUTSAMPLEBUF_CONFIG:
|
||||
|
||||
case TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL:
|
||||
case TEGRA186_ASRC_RATIO_UPD_RX_STATUS:
|
||||
|
||||
case TEGRA186_ASRC_GLOBAL_ENB:
|
||||
case TEGRA186_ASRC_GLOBAL_SOFT_RESET:
|
||||
case TEGRA186_ASRC_GLOBAL_CG:
|
||||
case TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR:
|
||||
case TEGRA186_ASRC_GLOBAL_SCRATCH_CONFIG:
|
||||
|
||||
case TEGRA186_ASRC_GLOBAL_STATUS:
|
||||
case TEGRA186_ASRC_GLOBAL_STREAM_ENABLE_STATUS:
|
||||
case TEGRA186_ASRC_GLOBAL_INT_STATUS:
|
||||
case TEGRA186_ASRC_GLOBAL_INT_MASK:
|
||||
case TEGRA186_ASRC_GLOBAL_INT_SET:
|
||||
case TEGRA186_ASRC_GLOBAL_INT_CLEAR:
|
||||
case TEGRA186_ASRC_GLOBAL_TRANSFER_ERROR_LOG:
|
||||
case TEGRA186_ASRC_GLOBAL_APR_CTRL:
|
||||
case TEGRA186_ASRC_GLOBAL_APR_CTRL_ACCESS_CTRL:
|
||||
case TEGRA186_ASRC_GLOBAL_DISARM_APR:
|
||||
case TEGRA186_ASRC_GLOBAL_DISARM_APR_ACCESS_CTRL:
|
||||
case TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS:
|
||||
case TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS_CTRL:
|
||||
case TEGRA186_ASRC_CYA:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
};
|
||||
}
|
||||
|
||||
static bool tegra186_asrc_volatile_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if (reg < TEGRA186_ASRC_STREAM_LIMIT)
|
||||
reg %= TEGRA186_ASRC_STREAM_STRIDE;
|
||||
|
||||
switch (reg) {
|
||||
case TEGRA186_ASRC_STREAM1_RX_STATUS:
|
||||
case TEGRA186_ASRC_STREAM1_TX_STATUS:
|
||||
case TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART:
|
||||
case TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART:
|
||||
case TEGRA186_ASRC_STREAM1_STATUS:
|
||||
case TEGRA186_ASRC_STREAM1_BUFFER_STATUS:
|
||||
case TEGRA186_ASRC_STREAM1_CONFIG_ERR_TYPE:
|
||||
|
||||
case TEGRA186_ASRC_RATIO_UPD_RX_STATUS:
|
||||
|
||||
case TEGRA186_ASRC_GLOBAL_STATUS:
|
||||
case TEGRA186_ASRC_GLOBAL_STREAM_ENABLE_STATUS:
|
||||
case TEGRA186_ASRC_GLOBAL_INT_STATUS:
|
||||
case TEGRA186_ASRC_GLOBAL_TRANSFER_ERROR_LOG:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
};
|
||||
}
|
||||
|
||||
static const struct regmap_config tegra186_asrc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = TEGRA186_ASRC_CYA,
|
||||
.writeable_reg = tegra186_asrc_wr_reg,
|
||||
.readable_reg = tegra186_asrc_rd_reg,
|
||||
.volatile_reg = tegra186_asrc_volatile_reg,
|
||||
.reg_defaults = tegra186_asrc_reg_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(tegra186_asrc_reg_defaults),
|
||||
.cache_type = REGCACHE_FLAT,
|
||||
};
|
||||
|
||||
static const struct tegra186_asrc_soc_data soc_data_tegra186 = {
|
||||
.set_audio_cif = tegra210_xbar_set_cif,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra186_asrc_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra186-asrc", .data = &soc_data_tegra186 },
|
||||
{},
|
||||
};
|
||||
|
||||
static int tegra186_asrc_platform_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra186_asrc *asrc;
|
||||
struct resource *mem, *memregion;
|
||||
void __iomem *regs;
|
||||
int ret = 0;
|
||||
const struct of_device_id *match;
|
||||
struct tegra186_asrc_soc_data *soc_data;
|
||||
unsigned int i = 0;
|
||||
|
||||
match = of_match_device(tegra186_asrc_of_match, &pdev->dev);
|
||||
if (!match) {
|
||||
dev_err(&pdev->dev, "Error: No device match found\n");
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
soc_data = (struct tegra186_asrc_soc_data *)match->data;
|
||||
|
||||
asrc = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct tegra186_asrc), GFP_KERNEL);
|
||||
if (!asrc) {
|
||||
dev_err(&pdev->dev, "Can't allocate asrc\n");
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
dev_set_drvdata(&pdev->dev, asrc);
|
||||
|
||||
asrc->soc_data = soc_data;
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem) {
|
||||
dev_err(&pdev->dev, "No memory resource\n");
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
|
||||
memregion = devm_request_mem_region(&pdev->dev, mem->start,
|
||||
resource_size(mem), pdev->name);
|
||||
if (!memregion) {
|
||||
dev_err(&pdev->dev, "Memory region already claimed\n");
|
||||
ret = -EBUSY;
|
||||
goto err;
|
||||
}
|
||||
|
||||
regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
|
||||
if (!regs) {
|
||||
dev_err(&pdev->dev, "ioremap failed\n");
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
asrc->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
||||
&tegra186_asrc_regmap_config);
|
||||
if (IS_ERR(asrc->regmap)) {
|
||||
dev_err(&pdev->dev, "regmap init failed\n");
|
||||
ret = PTR_ERR(asrc->regmap);
|
||||
goto err;
|
||||
}
|
||||
regcache_cache_only(asrc->regmap, true);
|
||||
|
||||
if (of_property_read_u32(pdev->dev.of_node,
|
||||
"nvidia,ahub-asrc-id",
|
||||
&pdev->dev.id) < 0) {
|
||||
dev_err(&pdev->dev,
|
||||
"Missing property nvidia,ahub-asrc-id\n");
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
if (!pm_runtime_enabled(&pdev->dev)) {
|
||||
ret = tegra186_asrc_runtime_resume(&pdev->dev);
|
||||
if (ret)
|
||||
goto err_pm_disable;
|
||||
}
|
||||
|
||||
regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_CONFIG,
|
||||
TEGRA186_ASRC_GLOBAL_CONFIG_FRAC_32BIT_PRECISION);
|
||||
|
||||
/* Set global starting address of the buffer in ARAM */
|
||||
regmap_write(asrc->regmap,
|
||||
TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, 0x3F808000);
|
||||
|
||||
/* set global enable */
|
||||
regmap_write(asrc->regmap,
|
||||
TEGRA186_ASRC_GLOBAL_ENB, TEGRA186_ASRC_GLOBAL_EN);
|
||||
|
||||
/* initialize default output srate */
|
||||
for (i = 0; i < 6; i++) {
|
||||
asrc->lane[i].int_part = 1;
|
||||
asrc->lane[i].frac_part = 0;
|
||||
asrc->lane[i].ratio_source = RATIO_SW;
|
||||
regmap_update_bits(asrc->regmap,
|
||||
ASRC_STREAM_REG(TEGRA186_ASRC_STREAM1_CONFIG, i), 1, 1);
|
||||
}
|
||||
|
||||
ret = snd_soc_register_codec(&pdev->dev, &tegra186_asrc_codec,
|
||||
tegra186_asrc_dais,
|
||||
ARRAY_SIZE(tegra186_asrc_dais));
|
||||
if (ret != 0) {
|
||||
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
|
||||
goto err_suspend;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_suspend:
|
||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||
tegra186_asrc_runtime_suspend(&pdev->dev);
|
||||
err_pm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra186_asrc_platform_remove(struct platform_device *pdev)
|
||||
{
|
||||
snd_soc_unregister_codec(&pdev->dev);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||
tegra186_asrc_runtime_suspend(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops tegra186_asrc_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(tegra186_asrc_runtime_suspend,
|
||||
tegra186_asrc_runtime_resume, NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(tegra186_asrc_suspend, NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver tegra186_asrc_driver = {
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra186_asrc_of_match,
|
||||
.pm = &tegra186_asrc_pm_ops,
|
||||
},
|
||||
.probe = tegra186_asrc_platform_probe,
|
||||
.remove = tegra186_asrc_platform_remove,
|
||||
};
|
||||
module_platform_driver(tegra186_asrc_driver)
|
||||
|
||||
MODULE_AUTHOR("Junghyun Kim <juskim@nvidia.com>");
|
||||
MODULE_DESCRIPTION("Tegra186 ASRC ASoC driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
MODULE_DEVICE_TABLE(of, tegra186_asrc_of_match);
|
||||
Reference in New Issue
Block a user