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ASoC: tegra: Update ASRC and OPE control name

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Updated ASRC and OPE control names as per upstream kernel.
To simplify the unification of audio scripts

Bug 3592105
Bug 3896761

Change-Id: If9449baed51d59a33efdadff6c7ba3d2858299ca
Signed-off-by: Sheetal <sheetal@nvidia.com>
(cherry picked from commit 524e22f44cdf68ca4eb05a690b89d8ca6e4886d1)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.10/+/2844839
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2856572
Tested-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Sheetal
2023-01-17 16:02:42 +05:30
committed by mobile promotions
parent a51a3b4d6f
commit 69a7eaf40a
3 changed files with 49 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
sound/soc/tegra/tegra186_asrc.c
View File

@@ -2,7 +2,7 @@
// //
// tegra186_asrc.c - Tegra186 ASRC driver // tegra186_asrc.c - Tegra186 ASRC driver
// //
// Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. // Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/delay.h> #include <linux/delay.h>
@@ -720,60 +720,60 @@ ASRC_SOURCE_DECL(src_select6, 5);
.invert = 0, .min = 0, .max = xmax} } .invert = 0, .min = 0, .max = xmax} }
static const struct snd_kcontrol_new tegra186_asrc_controls[] = { static const struct snd_kcontrol_new tegra186_asrc_controls[] = {
SOC_SINGLE_EXT("Ratio1 Int", TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART, SOC_SINGLE_EXT("Ratio1 Integer Part", TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0, 0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int), tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT_FRAC("Ratio1 Frac", SOC_SINGLE_EXT_FRAC("Ratio1 Fractional Part",
TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART, TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART,
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac), tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT("Ratio2 Int", TEGRA186_ASRC_STREAM2_RATIO_INTEGER_PART, SOC_SINGLE_EXT("Ratio2 Integer Part", TEGRA186_ASRC_STREAM2_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0, 0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int), tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT_FRAC("Ratio2 Frac", SOC_SINGLE_EXT_FRAC("Ratio2 Fractional Part",
TEGRA186_ASRC_STREAM2_RATIO_FRAC_PART, TEGRA186_ASRC_STREAM2_RATIO_FRAC_PART,
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac), tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT("Ratio3 Int", TEGRA186_ASRC_STREAM3_RATIO_INTEGER_PART, SOC_SINGLE_EXT("Ratio3 Integer Part", TEGRA186_ASRC_STREAM3_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0, 0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int), tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT_FRAC("Ratio3 Frac", SOC_SINGLE_EXT_FRAC("Ratio3 Fractional Part",
TEGRA186_ASRC_STREAM3_RATIO_FRAC_PART, TEGRA186_ASRC_STREAM3_RATIO_FRAC_PART,
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac), tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT("Ratio4 Int", TEGRA186_ASRC_STREAM4_RATIO_INTEGER_PART, SOC_SINGLE_EXT("Ratio4 Integer Part", TEGRA186_ASRC_STREAM4_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0, 0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int), tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT_FRAC("Ratio4 Frac", SOC_SINGLE_EXT_FRAC("Ratio4 Fractional Part",
TEGRA186_ASRC_STREAM4_RATIO_FRAC_PART, TEGRA186_ASRC_STREAM4_RATIO_FRAC_PART,
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac), tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT("Ratio5 Int", TEGRA186_ASRC_STREAM5_RATIO_INTEGER_PART, SOC_SINGLE_EXT("Ratio5 Integer Part", TEGRA186_ASRC_STREAM5_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0, 0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int), tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT_FRAC("Ratio5 Frac", SOC_SINGLE_EXT_FRAC("Ratio5 Fractional Part",
TEGRA186_ASRC_STREAM5_RATIO_FRAC_PART, TEGRA186_ASRC_STREAM5_RATIO_FRAC_PART,
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac), tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT("Ratio6 Int", TEGRA186_ASRC_STREAM6_RATIO_INTEGER_PART, SOC_SINGLE_EXT("Ratio6 Integer Part", TEGRA186_ASRC_STREAM6_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0, 0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int), tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT_FRAC("Ratio6 Frac", SOC_SINGLE_EXT_FRAC("Ratio6 Fractional Part",
TEGRA186_ASRC_STREAM6_RATIO_FRAC_PART, TEGRA186_ASRC_STREAM6_RATIO_FRAC_PART,
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac), tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_ENUM_EXT("Ratio1 SRC", src_select1, SOC_ENUM_EXT("Ratio1 Source", src_select1,
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source), tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
SOC_ENUM_EXT("Ratio2 SRC", src_select2, SOC_ENUM_EXT("Ratio2 Source", src_select2,
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source), tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
SOC_ENUM_EXT("Ratio3 SRC", src_select3, SOC_ENUM_EXT("Ratio3 Source", src_select3,
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source), tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
SOC_ENUM_EXT("Ratio4 SRC", src_select4, SOC_ENUM_EXT("Ratio4 Source", src_select4,
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source), tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
SOC_ENUM_EXT("Ratio5 SRC", src_select5, SOC_ENUM_EXT("Ratio5 Source", src_select5,
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source), tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
SOC_ENUM_EXT("Ratio6 SRC", src_select6, SOC_ENUM_EXT("Ratio6 Source", src_select6,
tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source), tegra186_asrc_get_ratio_source, tegra186_asrc_put_ratio_source),
SOC_SINGLE_EXT("Stream1 Enable", SOC_SINGLE_EXT("Stream1 Enable",

50
sound/soc/tegra/tegra210_mbdrc.c
View File

@@ -2,7 +2,7 @@
// //
// tegra210_mbdrc.c - Tegra210 MBDRC driver // tegra210_mbdrc.c - Tegra210 MBDRC driver
// //
// Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved. // Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
#include <linux/device.h> #include <linux/device.h>
#include <linux/io.h> #include <linux/io.h>
@@ -431,56 +431,56 @@ static const struct soc_enum tegra210_mbdrc_frame_size_enum =
static const DECLARE_TLV_DB_MINMAX(mdbrc_vol_tlv, -25600, 25500); static const DECLARE_TLV_DB_MINMAX(mdbrc_vol_tlv, -25600, 25500);
static const struct snd_kcontrol_new tegra210_mbdrc_controls[] = { static const struct snd_kcontrol_new tegra210_mbdrc_controls[] = {
SOC_ENUM_EXT("mbdrc peak-rms mode", tegra210_mbdrc_peak_rms_enum, SOC_ENUM_EXT("MBDRC Peak RMS Mode", tegra210_mbdrc_peak_rms_enum,
tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum), tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum),
SOC_ENUM_EXT("mbdrc filter structure", SOC_ENUM_EXT("MBDRC Filter Structure",
tegra210_mbdrc_filter_structure_enum, tegra210_mbdrc_filter_structure_enum,
tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum), tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum),
SOC_ENUM_EXT("mbdrc frame size", tegra210_mbdrc_frame_size_enum, SOC_ENUM_EXT("MBDRC Frame Size", tegra210_mbdrc_frame_size_enum,
tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum), tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum),
SOC_ENUM_EXT("mbdrc mode", tegra210_mbdrc_mode_enum, SOC_ENUM_EXT("MBDRC Mode", tegra210_mbdrc_mode_enum,
tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum), tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum),
SOC_SINGLE_EXT("mbdrc rms offset", TEGRA210_MBDRC_CONFIG, SOC_SINGLE_EXT("MBDRC RMS Offset", TEGRA210_MBDRC_CONFIG,
TEGRA210_MBDRC_CONFIG_RMS_OFFSET_SHIFT, 0x1ff, 0, TEGRA210_MBDRC_CONFIG_RMS_OFFSET_SHIFT, 0x1ff, 0,
tegra210_mbdrc_get, tegra210_mbdrc_put), tegra210_mbdrc_get, tegra210_mbdrc_put),
SOC_SINGLE_EXT("mbdrc shift control", TEGRA210_MBDRC_CONFIG, SOC_SINGLE_EXT("MBDRC Shift Control", TEGRA210_MBDRC_CONFIG,
TEGRA210_MBDRC_CONFIG_SHIFT_CTRL_SHIFT, 0x1f, 0, TEGRA210_MBDRC_CONFIG_SHIFT_CTRL_SHIFT, 0x1f, 0,
tegra210_mbdrc_get, tegra210_mbdrc_put), tegra210_mbdrc_get, tegra210_mbdrc_put),
SOC_SINGLE_EXT("mbdrc fast attack factor", TEGRA210_MBDRC_FAST_FACTOR, SOC_SINGLE_EXT("MBDRC Fast Attack Factor", TEGRA210_MBDRC_FAST_FACTOR,
TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT, 0xffff, 0, TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT, 0xffff, 0,
tegra210_mbdrc_get, tegra210_mbdrc_put), tegra210_mbdrc_get, tegra210_mbdrc_put),
SOC_SINGLE_EXT("mbdrc fast release factor", TEGRA210_MBDRC_FAST_FACTOR, SOC_SINGLE_EXT("MBDRC Fast Release Factor", TEGRA210_MBDRC_FAST_FACTOR,
TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIFT, 0xffff, 0, TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIFT, 0xffff, 0,
tegra210_mbdrc_get, tegra210_mbdrc_put), tegra210_mbdrc_get, tegra210_mbdrc_put),
SOC_SINGLE_RANGE_EXT_TLV("mbdrc master volume", TEGRA210_MBDRC_MASTER_VOLUME, SOC_SINGLE_RANGE_EXT_TLV("MBDRC Master Volume", TEGRA210_MBDRC_MASTER_VOLUME,
TEGRA210_MBDRC_MASTER_VOLUME_SHIFT, TEGRA210_MBDRC_MASTER_VOL_MIN, TEGRA210_MBDRC_MASTER_VOLUME_SHIFT, TEGRA210_MBDRC_MASTER_VOL_MIN,
TEGRA210_MBDRC_MASTER_VOL_MAX, 0, TEGRA210_MBDRC_MASTER_VOL_MAX, 0,
tegra210_mbdrc_vol_get, tegra210_mbdrc_vol_put, mdbrc_vol_tlv), tegra210_mbdrc_vol_get, tegra210_mbdrc_vol_put, mdbrc_vol_tlv),
TEGRA_SOC_BYTES_EXT("mbdrc iir stages", TEGRA210_MBDRC_IIR_CONFIG, TEGRA_SOC_BYTES_EXT("MBDRC IIR Stages", TEGRA210_MBDRC_IIR_CONFIG,
TEGRA210_MBDRC_FILTER_COUNT, TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_IIR_CONFIG_NUM_STAGES_SHIFT, TEGRA210_MBDRC_IIR_CONFIG_NUM_STAGES_SHIFT,
TEGRA210_MBDRC_IIR_CONFIG_NUM_STAGES_MASK, TEGRA210_MBDRC_IIR_CONFIG_NUM_STAGES_MASK,
tegra210_mbdrc_band_params_get, tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put, tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc in attack tc", TEGRA210_MBDRC_IN_ATTACK, TEGRA_SOC_BYTES_EXT("MBDRC In Attack Time Const", TEGRA210_MBDRC_IN_ATTACK,
TEGRA210_MBDRC_FILTER_COUNT, TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT, TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT,
TEGRA210_MBDRC_IN_ATTACK_TC_MASK, TEGRA210_MBDRC_IN_ATTACK_TC_MASK,
tegra210_mbdrc_band_params_get, tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put, tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc in release tc", TEGRA210_MBDRC_IN_RELEASE, TEGRA_SOC_BYTES_EXT("MBDRC In Release Time Const", TEGRA210_MBDRC_IN_RELEASE,
TEGRA210_MBDRC_FILTER_COUNT, TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT, TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT,
TEGRA210_MBDRC_IN_RELEASE_TC_MASK, TEGRA210_MBDRC_IN_RELEASE_TC_MASK,
tegra210_mbdrc_band_params_get, tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put, tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc fast attack tc", TEGRA210_MBDRC_FAST_ATTACK, TEGRA_SOC_BYTES_EXT("MBDRC Fast Attack Time Const", TEGRA210_MBDRC_FAST_ATTACK,
TEGRA210_MBDRC_FILTER_COUNT, TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT, TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT,
TEGRA210_MBDRC_FAST_ATTACK_TC_MASK, TEGRA210_MBDRC_FAST_ATTACK_TC_MASK,
@@ -488,48 +488,48 @@ static const struct snd_kcontrol_new tegra210_mbdrc_controls[] = {
tegra210_mbdrc_band_params_put, tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc in threshold", TEGRA210_MBDRC_IN_THRESHOLD, TEGRA_SOC_BYTES_EXT("MBDRC In Threshold", TEGRA210_MBDRC_IN_THRESHOLD,
TEGRA210_MBDRC_FILTER_COUNT * 4, 0, 0xffffffff, TEGRA210_MBDRC_FILTER_COUNT * 4, 0, 0xffffffff,
tegra210_mbdrc_threshold_get, tegra210_mbdrc_threshold_put, tegra210_mbdrc_param_info), tegra210_mbdrc_threshold_get, tegra210_mbdrc_threshold_put, tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc out threshold", TEGRA210_MBDRC_OUT_THRESHOLD, TEGRA_SOC_BYTES_EXT("MBDRC Out Threshold", TEGRA210_MBDRC_OUT_THRESHOLD,
TEGRA210_MBDRC_FILTER_COUNT * 4, 0, 0xffffffff, TEGRA210_MBDRC_FILTER_COUNT * 4, 0, 0xffffffff,
tegra210_mbdrc_threshold_get, tegra210_mbdrc_threshold_put, tegra210_mbdrc_param_info), tegra210_mbdrc_threshold_get, tegra210_mbdrc_threshold_put, tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc ratio", TEGRA210_MBDRC_RATIO_1ST, TEGRA_SOC_BYTES_EXT("MBDRC Ratio", TEGRA210_MBDRC_RATIO_1ST,
TEGRA210_MBDRC_FILTER_COUNT * 5, TEGRA210_MBDRC_FILTER_COUNT * 5,
TEGRA210_MBDRC_RATIO_1ST_SHIFT, TEGRA210_MBDRC_RATIO_1ST_MASK, TEGRA210_MBDRC_RATIO_1ST_SHIFT, TEGRA210_MBDRC_RATIO_1ST_MASK,
tegra210_mbdrc_band_params_get, tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put, tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc makeup gain", TEGRA210_MBDRC_MAKEUP_GAIN, TEGRA_SOC_BYTES_EXT("MBDRC Makeup Gain", TEGRA210_MBDRC_MAKEUP_GAIN,
TEGRA210_MBDRC_FILTER_COUNT, TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT, TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT,
TEGRA210_MBDRC_MAKEUP_GAIN_MASK, TEGRA210_MBDRC_MAKEUP_GAIN_MASK,
tegra210_mbdrc_band_params_get, tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put, tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc init gain", TEGRA210_MBDRC_INIT_GAIN, TEGRA_SOC_BYTES_EXT("MBDRC Init Gain", TEGRA210_MBDRC_INIT_GAIN,
TEGRA210_MBDRC_FILTER_COUNT, TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_INIT_GAIN_SHIFT, TEGRA210_MBDRC_INIT_GAIN_SHIFT,
TEGRA210_MBDRC_INIT_GAIN_MASK, TEGRA210_MBDRC_INIT_GAIN_MASK,
tegra210_mbdrc_band_params_get, tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put, tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc attack gain", TEGRA210_MBDRC_GAIN_ATTACK, TEGRA_SOC_BYTES_EXT("MBDRC Attack Gain", TEGRA210_MBDRC_GAIN_ATTACK,
TEGRA210_MBDRC_FILTER_COUNT, TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_GAIN_ATTACK_SHIFT, TEGRA210_MBDRC_GAIN_ATTACK_SHIFT,
TEGRA210_MBDRC_GAIN_ATTACK_MASK, TEGRA210_MBDRC_GAIN_ATTACK_MASK,
tegra210_mbdrc_band_params_get, tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put, tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc release gain", TEGRA210_MBDRC_GAIN_RELEASE, TEGRA_SOC_BYTES_EXT("MBDRC Release Gain", TEGRA210_MBDRC_GAIN_RELEASE,
TEGRA210_MBDRC_FILTER_COUNT, TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_GAIN_RELEASE_SHIFT, TEGRA210_MBDRC_GAIN_RELEASE_SHIFT,
TEGRA210_MBDRC_GAIN_RELEASE_MASK, TEGRA210_MBDRC_GAIN_RELEASE_MASK,
tegra210_mbdrc_band_params_get, tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put, tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc fast release gain", TEGRA_SOC_BYTES_EXT("MBDRC Fast Release Gain",
TEGRA210_MBDRC_FAST_RELEASE, TEGRA210_MBDRC_FAST_RELEASE,
TEGRA210_MBDRC_FILTER_COUNT, TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_FAST_RELEASE_SHIFT, TEGRA210_MBDRC_FAST_RELEASE_SHIFT,
@@ -538,20 +538,20 @@ static const struct snd_kcontrol_new tegra210_mbdrc_controls[] = {
tegra210_mbdrc_band_params_put, tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc low band biquad coeffs", TEGRA_SOC_BYTES_EXT("MBDRC Low Band Biquad Coeffs",
TEGRA210_MBDRC_AHUBRAMCTL_CONFIG_RAM_CTRL, TEGRA210_MBDRC_AHUBRAMCTL_CONFIG_RAM_CTRL,
TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5, 0, 0xffffffff, TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5, 0, 0xffffffff,
tegra210_mbdrc_biquad_coeffs_get, tegra210_mbdrc_biquad_coeffs_get,
tegra210_mbdrc_biquad_coeffs_put, tegra210_mbdrc_biquad_coeffs_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc mid band biquad coeffs", TEGRA_SOC_BYTES_EXT("MBDRC Mid Band Biquad Coeffs",
TEGRA210_MBDRC_AHUBRAMCTL_CONFIG_RAM_CTRL + TEGRA210_MBDRC_AHUBRAMCTL_CONFIG_RAM_CTRL +
TEGRA210_MBDRC_FILTER_PARAM_STRIDE, TEGRA210_MBDRC_FILTER_PARAM_STRIDE,
TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5, 0, 0xffffffff, TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5, 0, 0xffffffff,
tegra210_mbdrc_biquad_coeffs_get, tegra210_mbdrc_biquad_coeffs_get,
tegra210_mbdrc_biquad_coeffs_put, tegra210_mbdrc_biquad_coeffs_put,
tegra210_mbdrc_param_info), tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("mbdrc high band biquad coeffs", TEGRA_SOC_BYTES_EXT("MBDRC High Band Biquad Coeffs",
TEGRA210_MBDRC_AHUBRAMCTL_CONFIG_RAM_CTRL + TEGRA210_MBDRC_AHUBRAMCTL_CONFIG_RAM_CTRL +
(TEGRA210_MBDRC_FILTER_PARAM_STRIDE * 2), (TEGRA210_MBDRC_FILTER_PARAM_STRIDE * 2),
TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5, 0, 0xffffffff, TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5, 0, 0xffffffff,

10
sound/soc/tegra/tegra210_peq.c
View File

@@ -2,7 +2,7 @@
// //
// tegra210_peq.c - Tegra210 PEQ driver // tegra210_peq.c - Tegra210 PEQ driver
// //
// Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved. // Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/device.h> #include <linux/device.h>
@@ -151,7 +151,7 @@ static int tegra210_peq_param_info(struct snd_kcontrol *kcontrol,
} }
#define TEGRA210_PEQ_GAIN_PARAMS_CTRL(chan) \ #define TEGRA210_PEQ_GAIN_PARAMS_CTRL(chan) \
TEGRA_SOC_BYTES_EXT("peq channel" #chan " biquad gain params", \ TEGRA_SOC_BYTES_EXT("PEQ Channel-" #chan " biquad gain params", \
TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL, \ TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL, \
TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH, \ TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH, \
(TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH * chan), 0xffffffff, \ (TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH * chan), 0xffffffff, \
@@ -159,7 +159,7 @@ static int tegra210_peq_param_info(struct snd_kcontrol *kcontrol,
tegra210_peq_param_info) tegra210_peq_param_info)
#define TEGRA210_PEQ_SHIFT_PARAMS_CTRL(chan) \ #define TEGRA210_PEQ_SHIFT_PARAMS_CTRL(chan) \
TEGRA_SOC_BYTES_EXT("peq channel" #chan " biquad shift params", \ TEGRA_SOC_BYTES_EXT("PEQ Channel-" #chan " biquad shift params", \
TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL, \ TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL, \
TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH, \ TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH, \
(TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH * chan), 0x1f, \ (TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH * chan), 0x1f, \
@@ -167,10 +167,10 @@ static int tegra210_peq_param_info(struct snd_kcontrol *kcontrol,
tegra210_peq_param_info) tegra210_peq_param_info)
static const struct snd_kcontrol_new tegra210_peq_controls[] = { static const struct snd_kcontrol_new tegra210_peq_controls[] = {
SOC_SINGLE_EXT("peq active", TEGRA210_PEQ_CONFIG, SOC_SINGLE_EXT("PEQ Active", TEGRA210_PEQ_CONFIG,
TEGRA210_PEQ_CONFIG_MODE_SHIFT, 1, 0, TEGRA210_PEQ_CONFIG_MODE_SHIFT, 1, 0,
tegra210_peq_get, tegra210_peq_put), tegra210_peq_get, tegra210_peq_put),
SOC_SINGLE_EXT("peq biquad stages", TEGRA210_PEQ_CONFIG, SOC_SINGLE_EXT("PEQ Biquad Stages", TEGRA210_PEQ_CONFIG,
TEGRA210_PEQ_CONFIG_BIQUAD_STAGES_SHIFT, TEGRA210_PEQ_CONFIG_BIQUAD_STAGES_SHIFT,
TEGRA210_PEQ_MAX_BIQUAD_STAGES - 1, 0, TEGRA210_PEQ_MAX_BIQUAD_STAGES - 1, 0,
tegra210_peq_get, tegra210_peq_put), tegra210_peq_get, tegra210_peq_put),