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ASoC: tegra: update AHUB drivers as per upstream

Browse Source 
AHUB and few components have been pushed for upstream review. Though the
changes are still under review, we can leverage the work done on upstream
5.x and use the same here on 5.4 kernel. This helps to align the downstream
code. Any changes that happen because of upstream review can be cherry
picked here. If we plan for any downstream changes, upstream patch needs to
be pushed to keep the code in sync.

As of today current snapshot is pulled from v3 of AHUB series,
http://patchwork.ozlabs.org/project/linux-tegra/list/?series=159664

Above series was worked on later versions of linux-next and hence following
are the changes required for porting back on 5.4
 * tegra_pcm_new() and tegra_pcm_free() are exposed from tegra_pcm.c and
   component driver callbacks use these.
 * Callback functions required for snd_pcm_ops in component driver are
   implemented by tegra_pcm.c
 * With this ADMAIF driver need not register platform device with ASoC
   core.

For components (AHUB, ADMAIF, I2S, DMIC and DSPK) the downsream code
differs in few aspects from the code that was pushed for v3. Some of them
are listed below.
 * I2S driver in downstream implements startup()/shutdown() calls for DAI,
   which does some setup related to pinconfig and regulators. The same is
   true for DMIC and DSPK drivers as well.
 * Downstream ADMAIF drivers makes bandwidth requests in startup/shutdown()
   calls and has helper function for dumping registers. It also has
   additional DAI interfaces which are used for ADSP audio.
 * Downstream AHUB driver has DAI interfaces for connecting to all other
   modules.
These differences will be cherry-picked as and when it is necessary.

Bug 2845498

Change-Id: Id374967ecae26f6b7334a959fb23308d383c15f2
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
This commit is contained in:
Sameer Pujar
2020-02-24 11:48:08 +05:30
parent 39e4507117
commit 6b98f0a740
10 changed files with 2198 additions and 2421 deletions
Download Patch File Download Diff File Expand all files Collapse all files

590
sound/soc/tegra/tegra186_dspk.c
View File

@@ -1,88 +1,86 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra186_dspk_alt.c - Tegra186 DSPK driver
* tegra186_dspk.c - Tegra186 DSPK driver
*
* Copyright (c) 2015-2019 NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/of_device.h>
#include <soc/tegra/chip-id.h>
#include <linux/pinctrl/pinconf-tegra.h>
#include "tegra210_xbar_alt.h"
#include "tegra186_dspk_alt.h"
#include "ahub_unit_fpga_clock.h"
#define DRV_NAME "tegra186-dspk"
#include "tegra186_dspk.h"
#include "tegra_cif.h"
static const struct reg_default tegra186_dspk_reg_defaults[] = {
{ TEGRA186_DSPK_AXBAR_RX_INT_MASK, 0x00000007},
{ TEGRA186_DSPK_AXBAR_RX_CIF_CTRL, 0x00007700},
{ TEGRA186_DSPK_CG, 0x00000001},
{ TEGRA186_DSPK_CORE_CTRL, 0x00000310},
{ TEGRA186_DSPK_CODEC_CTRL, 0x03000000},
{ TEGRA186_DSPK_SDM_COEF_A_2, 0x000013bb},
{ TEGRA186_DSPK_SDM_COEF_A_3, 0x00001cbf},
{ TEGRA186_DSPK_SDM_COEF_A_4, 0x000029d7},
{ TEGRA186_DSPK_SDM_COEF_A_5, 0x00003782},
{ TEGRA186_DSPK_SDM_COEF_C_1, 0x000000a6},
{ TEGRA186_DSPK_SDM_COEF_C_2, 0x00001959},
{ TEGRA186_DSPK_SDM_COEF_C_3, 0x00002b9f},
{ TEGRA186_DSPK_SDM_COEF_C_4, 0x00004218},
{ TEGRA186_DSPK_SDM_COEF_G_1, 0x00000074},
{ TEGRA186_DSPK_SDM_COEF_G_2, 0x0000007d},
{ TEGRA186_DSPK_RX_INT_MASK, 0x00000007 },
{ TEGRA186_DSPK_RX_CIF_CTRL, 0x00007700 },
{ TEGRA186_DSPK_CG, 0x00000001 },
{ TEGRA186_DSPK_CORE_CTRL, 0x00000310 },
{ TEGRA186_DSPK_CODEC_CTRL, 0x03000000 },
};
static int tegra186_dspk_get_control(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct tegra186_dspk *dspk = snd_soc_codec_get_drvdata(codec);
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
if (strstr(kcontrol->id.name, "Rx fifo threshold"))
if (strstr(kcontrol->id.name, "FIFO Threshold"))
ucontrol->value.integer.value[0] = dspk->rx_fifo_th;
else if (strstr(kcontrol->id.name, "OSR Value"))
ucontrol->value.integer.value[0] = dspk->osr_val;
else if (strstr(kcontrol->id.name, "LR Polarity Select"))
ucontrol->value.integer.value[0] = dspk->lrsel;
else if (strstr(kcontrol->id.name, "Sample Rate"))
ucontrol->value.integer.value[0] = dspk->srate_override;
else if (strstr(kcontrol->id.name, "Audio Channels"))
ucontrol->value.integer.value[0] = dspk->audio_ch_override;
else if (strstr(kcontrol->id.name, "Channel Select"))
ucontrol->value.integer.value[0] = dspk->ch_sel;
else if (strstr(kcontrol->id.name, "Audio Bit Format"))
ucontrol->value.integer.value[0] = dspk->audio_fmt_override;
else if (strstr(kcontrol->id.name, "Mono To Stereo"))
ucontrol->value.integer.value[0] = dspk->mono_to_stereo;
else if (strstr(kcontrol->id.name, "Stereo To Mono"))
ucontrol->value.integer.value[0] = dspk->stereo_to_mono;
return 0;
}
static int tegra186_dspk_put_control(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct tegra186_dspk *dspk = snd_soc_codec_get_drvdata(codec);
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
int val = ucontrol->value.integer.value[0];
if (strstr(kcontrol->id.name, "Rx fifo threshold")) {
if (val >= 0 && val < TEGRA186_DSPK_RX_FIFO_DEPTH)
dspk->rx_fifo_th = val;
else
return -EINVAL;
} else if (strstr(kcontrol->id.name, "OSR Value"))
if (strstr(kcontrol->id.name, "FIFO Threshold"))
dspk->rx_fifo_th = val;
else if (strstr(kcontrol->id.name, "OSR Value"))
dspk->osr_val = val;
else if (strstr(kcontrol->id.name, "LR Polarity Select"))
dspk->lrsel = val;
else if (strstr(kcontrol->id.name, "Sample Rate"))
dspk->srate_override = val;
else if (strstr(kcontrol->id.name, "Audio Channels"))
dspk->audio_ch_override = val;
else if (strstr(kcontrol->id.name, "Channel Select"))
dspk->ch_sel = val;
else if (strstr(kcontrol->id.name, "Audio Bit Format"))
dspk->audio_fmt_override = val;
else if (strstr(kcontrol->id.name, "Mono To Stereo"))
dspk->mono_to_stereo = val;
else if (strstr(kcontrol->id.name, "Stereo To Mono"))
dspk->stereo_to_mono = val;
return 0;
}
@@ -94,8 +92,7 @@ static int tegra186_dspk_runtime_suspend(struct device *dev)
regcache_cache_only(dspk->regmap, true);
regcache_mark_dirty(dspk->regmap);
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()))
clk_disable_unprepare(dspk->clk_dspk);
clk_disable_unprepare(dspk->clk_dspk);
return 0;
}
@@ -103,14 +100,12 @@ static int tegra186_dspk_runtime_suspend(struct device *dev)
static int tegra186_dspk_runtime_resume(struct device *dev)
{
struct tegra186_dspk *dspk = dev_get_drvdata(dev);
int ret;
int err;
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
ret = clk_prepare_enable(dspk->clk_dspk);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
return ret;
}
err = clk_prepare_enable(dspk->clk_dspk);
if (err) {
dev_err(dev, "failed to enable DSPK clock, err: %d\n", err);
return err;
}
regcache_cache_only(dspk->regmap, false);
@@ -119,114 +114,129 @@ static int tegra186_dspk_runtime_resume(struct device *dev)
return 0;
}
static int tegra186_dspk_set_audio_cif(struct tegra186_dspk *dspk,
struct snd_pcm_hw_params *params,
unsigned int reg, struct snd_soc_dai *dai)
static const unsigned int tegra186_dspk_fmts[] = {
0,
TEGRA_ACIF_BITS_16,
TEGRA_ACIF_BITS_32,
};
static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int channels, max_th;
struct tegra210_xbar_cif_conf cif_conf;
struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
unsigned int channels, srate, dspk_clk;
struct device *dev = dai->dev;
struct tegra_cif_conf cif_conf;
unsigned int max_th;
int err;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params);
memset(&cif_conf, 0, sizeof(struct tegra210_xbar_cif_conf));
cif_conf.audio_channels = channels;
cif_conf.client_channels = channels;
cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_24;
cif_conf.audio_ch = channels;
/* RX FIFO threshold interms of frames */
max_th = (TEGRA186_DSPK_RX_FIFO_DEPTH / channels) - 1;
max_th = (max_th < 0) ? 0 : max_th;
if (dspk->rx_fifo_th > max_th) { /* error handling */
cif_conf.threshold = max_th;
dspk->rx_fifo_th = max_th;
} else
cif_conf.threshold = dspk->rx_fifo_th;
/* Override audio channel */
if (dspk->audio_ch_override)
cif_conf.audio_ch = dspk->audio_ch_override;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_16;
cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_16;
/* Client channel */
switch (dspk->ch_sel) {
case DSPK_CH_SELECT_LEFT:
case DSPK_CH_SELECT_RIGHT:
cif_conf.client_ch = 1;
break;
case SNDRV_PCM_FORMAT_S32_LE:
cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_32;
case DSPK_CH_SELECT_STEREO:
cif_conf.client_ch = 2;
break;
default:
dev_err(dev, "Wrong format!\n");
dev_err(dev, "Invalid DSPK client channels\n");
return -EINVAL;
}
tegra210_xbar_set_cif(dspk->regmap, TEGRA186_DSPK_AXBAR_RX_CIF_CTRL,
&cif_conf);
return 0;
}
cif_conf.client_bits = TEGRA_ACIF_BITS_24;
static int tegra186_dspk_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
int ret;
if (dspk->prod_name != NULL) {
ret = tegra_pinctrl_config_prod(dev, dspk->prod_name);
if (ret < 0)
dev_warn(dev, "Failed to set %s setting\n",
dspk->prod_name);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
cif_conf.client_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
break;
default:
dev_err(dev, "unsupported format!\n");
return -ENOTSUPP;
}
return 0;
}
/* Audio bit format override */
if (dspk->audio_fmt_override)
cif_conf.audio_bits =
tegra186_dspk_fmts[dspk->audio_fmt_override];
static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
int channels, srate, ret, dspk_clk;
int osr = dspk->osr_val;
int interface_clk_ratio = 4; /* dspk interface clock should be fsout*4 */
channels = params_channels(params);
srate = params_rate(params);
dspk_clk = (1 << (5+osr)) * srate * interface_clk_ratio;
/* Sample rate override */
if (dspk->srate_override)
srate = dspk->srate_override;
if ((tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
program_dspk_clk(dspk_clk);
} else {
ret = clk_set_rate(dspk->clk_dspk, dspk_clk);
if (ret) {
dev_err(dev, "Can't set dspk clock rate: %d\n", ret);
return ret;
}
/* RX FIFO threshold in terms of frames */
max_th = (TEGRA186_DSPK_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1;
if (dspk->rx_fifo_th > max_th)
dspk->rx_fifo_th = max_th;
cif_conf.threshold = dspk->rx_fifo_th;
cif_conf.mono_conv = dspk->mono_to_stereo;
cif_conf.stereo_conv = dspk->stereo_to_mono;
tegra_set_cif(dspk->regmap, TEGRA186_DSPK_RX_CIF_CTRL,
&cif_conf);
/*
* DSPK clock and PDM codec clock should be synchronous with 4:1 ratio,
* this is because it takes 4 clock cycles to send out one sample to
* codec by sigma delta modulator. Finally the clock rate is a multiple
* of 'Over Sampling Ratio', 'Sample Rate' and 'Interface Clock Ratio'.
*/
dspk_clk = (DSPK_OSR_FACTOR << dspk->osr_val) * srate * DSPK_CLK_RATIO;
err = clk_set_rate(dspk->clk_dspk, dspk_clk);
if (err) {
dev_err(dev, "can't set DSPK clock rate %u, err: %d\n",
dspk_clk, err);
return err;
}
regmap_update_bits(dspk->regmap,
TEGRA186_DSPK_CORE_CTRL,
TEGRA186_DSPK_OSR_MASK,
osr << TEGRA186_DSPK_OSR_SHIFT);
/* Reg */
TEGRA186_DSPK_CORE_CTRL,
/* Mask */
TEGRA186_DSPK_OSR_MASK |
TEGRA186_DSPK_CHANNEL_SELECT_MASK |
TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK,
/* Value */
(dspk->osr_val << DSPK_OSR_SHIFT) |
((dspk->ch_sel + 1) << CH_SEL_SHIFT) |
(dspk->lrsel << LRSEL_POL_SHIFT));
regmap_update_bits(dspk->regmap,
TEGRA186_DSPK_CORE_CTRL,
TEGRA186_DSPK_CHANNEL_SELECT_MASK,
((1 << channels) - 1) <<
TEGRA186_DSPK_CHANNEL_SELECT_SHIFT);
/* program cif control register */
ret = tegra186_dspk_set_audio_cif(dspk, params,
TEGRA186_DSPK_AXBAR_RX_CIF_CTRL,
dai);
if (ret)
dev_err(dev, "Can't set dspk RX CIF: %d\n", ret);
return ret;
return 0;
}
static struct snd_soc_dai_ops tegra186_dspk_dai_ops = {
static const struct snd_soc_dai_ops tegra186_dspk_dai_ops = {
.hw_params = tegra186_dspk_hw_params,
.startup = tegra186_dspk_startup,
};
/*
* Three DAIs are exposed
* 1. "CIF" DAI for connecting with XBAR
* 2. "DAP" DAI for connecting with CODEC
* 3. "DUMMY_SINK" can be used when no external
* codec connection is available. In such case
* "DAP" is connected with "DUMMY_SINK"
* Order of these DAIs should not be changed, since DAI links in DT refer
* to these DAIs depending on the index.
*/
static struct snd_soc_dai_driver tegra186_dspk_dais[] = {
{
.name = "CIF",
@@ -252,33 +262,6 @@ static struct snd_soc_dai_driver tegra186_dspk_dais[] = {
.ops = &tegra186_dspk_dai_ops,
.symmetric_rates = 1,
},
/* The second DAI is used when the output of the DSPK is connected
* to two mono codecs. When the output of the DSPK is connected to
* a single stereo codec, then only the first DAI should be used.
*/
{
.name = "CIF2",
.playback = {
.stream_name = "CIF2 Receive",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
},
{
.name = "DAP2",
.capture = {
.stream_name = "DAP2 Transmit",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.symmetric_rates = 1,
},
{
.name = "DUMMY_SINK",
.playback = {
@@ -294,74 +277,107 @@ static struct snd_soc_dai_driver tegra186_dspk_dais[] = {
static const struct snd_soc_dapm_widget tegra186_dspk_widgets[] = {
SND_SOC_DAPM_AIF_OUT("DAP TX", NULL, 0, TEGRA186_DSPK_ENABLE, 0, 0),
SND_SOC_DAPM_AIF_OUT("DAP2 TX", NULL, 0, 0, 0, 0),
SND_SOC_DAPM_SPK("Dummy Output", NULL),
};
static const struct snd_soc_dapm_route tegra186_dspk_routes[] = {
{ "DAP TX", NULL, "CIF Receive" },
{ "DAP TX", NULL, "CIF Receive" },
{ "DAP Transmit", NULL, "DAP TX" },
{ "DAP2 TX", NULL, "CIF2 Receive" },
{ "DAP2 Transmit", NULL, "DAP2 TX" },
{ "Dummy Output", NULL, "Dummy Playback" },
{ "Dummy Output", NULL, "Dummy Playback" },
};
static const char * const tegra186_dspk_format_text[] = {
"None",
"16",
"32",
};
static const struct soc_enum tegra186_dspk_format_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_format_text),
tegra186_dspk_format_text);
static const char * const tegra186_dspk_ch_sel_text[] = {
"Left", "Right", "Stereo",
};
static const struct soc_enum tegra186_dspk_ch_sel_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_ch_sel_text),
tegra186_dspk_ch_sel_text);
static const char * const tegra186_dspk_osr_text[] = {
"OSR_32", "OSR_64", "OSR_128", "OSR_256",
};
static const struct soc_enum tegra186_dspk_osr_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(tegra186_dspk_osr_text),
tegra186_dspk_osr_text);
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_osr_text),
tegra186_dspk_osr_text);
#define NV_SOC_SINGLE_RANGE_EXT(xname, xmin, xmax, xget, xput) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.info = snd_soc_info_xr_sx, .get = xget, .put = xput, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.invert = 0, .min = xmin, .max = xmax, \
.platform_max = xmax} \
}
static const char * const tegra186_dspk_lrsel_text[] = {
"Left", "Right",
};
static const char * const tegra186_dspk_mono_conv_text[] = {
"ZERO", "COPY",
};
static const struct soc_enum tegra186_dspk_mono_conv_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(tegra186_dspk_mono_conv_text),
tegra186_dspk_mono_conv_text);
static const char * const tegra186_dspk_stereo_conv_text[] = {
"CH0", "CH1", "AVG",
};
static const struct soc_enum tegra186_dspk_stereo_conv_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(tegra186_dspk_stereo_conv_text),
tegra186_dspk_stereo_conv_text);
static const struct soc_enum tegra186_dspk_lrsel_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_lrsel_text),
tegra186_dspk_lrsel_text);
static const struct snd_kcontrol_new tegrat186_dspk_controls[] = {
NV_SOC_SINGLE_RANGE_EXT("Rx fifo threshold", 0,
TEGRA186_DSPK_RX_FIFO_DEPTH - 1, tegra186_dspk_get_control,
tegra186_dspk_put_control),
SOC_SINGLE_EXT("FIFO Threshold", SND_SOC_NOPM, 0,
TEGRA186_DSPK_RX_FIFO_DEPTH - 1, 0,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("OSR Value", tegra186_dspk_osr_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("LR Polarity Select", tegra186_dspk_lrsel_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_SINGLE_EXT("Sample Rate", SND_SOC_NOPM, 0, 48000, 0,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_SINGLE_EXT("Audio Channels", SND_SOC_NOPM, 0, 2, 0,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("Channel Select", tegra186_dspk_ch_sel_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("Audio Bit Format", tegra186_dspk_format_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("Mono To Stereo", tegra186_dspk_mono_conv_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("Stereo To Mono", tegra186_dspk_stereo_conv_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
};
static struct snd_soc_codec_driver tegra186_dspk_codec = {
.idle_bias_off = 1,
.component_driver = {
.dapm_widgets = tegra186_dspk_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra186_dspk_widgets),
.dapm_routes = tegra186_dspk_routes,
.num_dapm_routes = ARRAY_SIZE(tegra186_dspk_routes),
.controls = tegrat186_dspk_controls,
.num_controls = ARRAY_SIZE(tegrat186_dspk_controls),
},
static const struct snd_soc_component_driver tegra186_dspk_cmpnt = {
.dapm_widgets = tegra186_dspk_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra186_dspk_widgets),
.dapm_routes = tegra186_dspk_routes,
.num_dapm_routes = ARRAY_SIZE(tegra186_dspk_routes),
.controls = tegrat186_dspk_controls,
.num_controls = ARRAY_SIZE(tegrat186_dspk_controls),
};
/* Regmap callback functions */
static bool tegra186_dspk_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA186_DSPK_AXBAR_RX_INT_MASK:
case TEGRA186_DSPK_AXBAR_RX_INT_SET:
case TEGRA186_DSPK_AXBAR_RX_INT_CLEAR:
case TEGRA186_DSPK_AXBAR_RX_CIF_CTRL:
case TEGRA186_DSPK_AXBAR_RX_CYA:
case TEGRA186_DSPK_ENABLE:
case TEGRA186_DSPK_SOFT_RESET:
case TEGRA186_DSPK_CG:
case TEGRA186_DSPK_RX_INT_MASK ... TEGRA186_DSPK_RX_CIF_CTRL:
case TEGRA186_DSPK_ENABLE ... TEGRA186_DSPK_CG:
case TEGRA186_DSPK_CORE_CTRL ... TEGRA186_DSPK_CODEC_CTRL:
return true;
default:
if (((reg % 4) == 0) && (reg >= TEGRA186_DSPK_CORE_CTRL) &&
(reg <= TEGRA186_DSPK_SDM_COEF_G_2))
return true;
else
return false;
return false;
};
}
@@ -371,27 +387,8 @@ static bool tegra186_dspk_rd_reg(struct device *dev, unsigned int reg)
return true;
switch (reg) {
case TEGRA186_DSPK_AXBAR_RX_STATUS:
case TEGRA186_DSPK_AXBAR_RX_INT_STATUS:
case TEGRA186_DSPK_AXBAR_RX_CIF_FIFO_STATUS:
case TEGRA186_DSPK_STATUS:
case TEGRA186_DSPK_INT_STATUS:
return true;
default:
if (((reg % 4) == 0) && (reg >= TEGRA186_DSPK_DEBUG_STATUS) &&
(reg <= TEGRA186_DSPK_DEBUG_STAGE4_CNTR))
return true;
else
return false;
};
}
static bool tegra186_dspk_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA186_DSPK_AXBAR_RX_STATUS:
case TEGRA186_DSPK_AXBAR_RX_INT_STATUS:
case TEGRA186_DSPK_AXBAR_RX_CIF_FIFO_STATUS:
case TEGRA186_DSPK_RX_STATUS:
case TEGRA186_DSPK_RX_INT_STATUS:
case TEGRA186_DSPK_STATUS:
case TEGRA186_DSPK_INT_STATUS:
return true;
@@ -400,114 +397,105 @@ static bool tegra186_dspk_volatile_reg(struct device *dev, unsigned int reg)
};
}
static const struct regmap_config tegra186_dspk_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA186_DSPK_DEBUG_STAGE4_CNTR,
.writeable_reg = tegra186_dspk_wr_reg,
.readable_reg = tegra186_dspk_rd_reg,
.volatile_reg = tegra186_dspk_volatile_reg,
.precious_reg = NULL,
.reg_defaults = tegra186_dspk_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra186_dspk_reg_defaults),
.cache_type = REGCACHE_FLAT,
static bool tegra186_dspk_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA186_DSPK_RX_STATUS:
case TEGRA186_DSPK_RX_INT_STATUS:
case TEGRA186_DSPK_STATUS:
case TEGRA186_DSPK_INT_STATUS:
return true;
default:
return false;
};
}
static const struct regmap_config tegra186_dspk_regmap = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA186_DSPK_CODEC_CTRL,
.writeable_reg = tegra186_dspk_wr_reg,
.readable_reg = tegra186_dspk_rd_reg,
.volatile_reg = tegra186_dspk_volatile_reg,
.reg_defaults = tegra186_dspk_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra186_dspk_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static const struct of_device_id tegra186_dspk_of_match[] = {
{ .compatible = "nvidia,tegra186-dspk" },
{},
};
MODULE_DEVICE_TABLE(of, tegra186_dspk_of_match);
static int tegra186_dspk_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra186_dspk *dspk;
struct device_node *np = pdev->dev.of_node;
struct resource *mem;
void __iomem *regs;
int ret = 0;
const struct of_device_id *match;
int err;
match = of_match_device(tegra186_dspk_of_match, &pdev->dev);
if (!match) {
dev_err(&pdev->dev, "Error: No device match found\n");
return -ENODEV;
}
dspk = devm_kzalloc(&pdev->dev, sizeof(*dspk), GFP_KERNEL);
dspk = devm_kzalloc(dev, sizeof(*dspk), GFP_KERNEL);
if (!dspk)
return -ENOMEM;
dspk->prod_name = NULL;
dspk->rx_fifo_th = 0;
dspk->osr_val = TEGRA186_DSPK_OSR_64;
dev_set_drvdata(&pdev->dev, dspk);
dspk->osr_val = DSPK_OSR_64;
dspk->lrsel = DSPK_LRSEL_LEFT;
dspk->ch_sel = DSPK_CH_SELECT_STEREO;
dspk->mono_to_stereo = 0; /* "ZERO" */
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
dspk->clk_dspk = devm_clk_get(&pdev->dev, "dspk");
if (IS_ERR(dspk->clk_dspk)) {
dev_err(&pdev->dev, "Can't retrieve dspk clock\n");
return PTR_ERR(dspk->clk_dspk);
}
dev_set_drvdata(dev, dspk);
dspk->clk_dspk = devm_clk_get(dev, "dspk");
if (IS_ERR(dspk->clk_dspk)) {
dev_err(dev, "can't retrieve DSPK clock\n");
return PTR_ERR(dspk->clk_dspk);
}
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(&pdev->dev, mem);
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
dspk->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&tegra186_dspk_regmap_config);
dspk->regmap = devm_regmap_init_mmio(dev, regs, &tegra186_dspk_regmap);
if (IS_ERR(dspk->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
dev_err(dev, "regmap init failed\n");
return PTR_ERR(dspk->regmap);
}
regcache_cache_only(dspk->regmap, true);
pm_runtime_enable(&pdev->dev);
ret = snd_soc_register_codec(&pdev->dev, &tegra186_dspk_codec,
tegra186_dspk_dais,
ARRAY_SIZE(tegra186_dspk_dais));
if (ret != 0) {
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
pm_runtime_disable(&pdev->dev);
return ret;
err = devm_snd_soc_register_component(dev, &tegra186_dspk_cmpnt,
tegra186_dspk_dais,
ARRAY_SIZE(tegra186_dspk_dais));
if (err) {
dev_err(dev, "can't register DSPK component, err: %d\n",
err);
return err;
}
if (of_property_read_string(np, "prod-name", &dspk->prod_name) == 0) {
ret = tegra_pinctrl_config_prod(&pdev->dev, dspk->prod_name);
if (ret < 0)
dev_warn(&pdev->dev, "Failed to set %s setting\n",
dspk->prod_name);
}
pm_runtime_enable(dev);
return 0;
}
static int tegra186_dspk_platform_remove(struct platform_device *pdev)
{
struct tegra186_dspk *dspk;
dspk = dev_get_drvdata(&pdev->dev);
snd_soc_unregister_codec(&pdev->dev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
tegra186_dspk_runtime_suspend(&pdev->dev);
return 0;
}
static const struct dev_pm_ops tegra186_dspk_pm_ops = {
SET_RUNTIME_PM_OPS(tegra186_dspk_runtime_suspend,
tegra186_dspk_runtime_resume, NULL)
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
tegra186_dspk_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra186_dspk_driver = {
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE,
.name = "tegra186-dspk",
.of_match_table = tegra186_dspk_of_match,
.pm = &tegra186_dspk_pm_ops,
},
@@ -516,9 +504,7 @@ static struct platform_driver tegra186_dspk_driver = {
};
module_platform_driver(tegra186_dspk_driver);
MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>");
MODULE_DESCRIPTION("Tegra186 DSPK ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra186_dspk_of_match);
MODULE_AUTHOR("Sameer Pujar <spujar@nvidia.com>");
MODULE_DESCRIPTION("Tegra186 ASoC DSPK driver");
MODULE_LICENSE("GPL v2");