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nvethernet: T26x CAR changes

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Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3126090

Bug 4228185

Change-Id: I74b0607de28b9a635afeae80dbc31cb79bd45f30
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>

fix compilation error

Change-Id: I088609c66a180aeacf8baeb9dad0d29a38550726
This commit is contained in:
Mahesh Patil
2024-04-25 11:12:32 -07:00
committed by Bhadram Varka
parent 54ca566b6a
commit 6bc9570126
5 changed files with 578 additions and 219 deletions
Download Patch File Download Diff File Expand all files Collapse all files

635
drivers/net/ethernet/nvidia/nvethernet/ether_linux.c
View File

File diff suppressed because it is too large Load Diff

10
drivers/net/ethernet/nvidia/nvethernet/ether_linux.h
View File

@@ -128,22 +128,28 @@
* @brief Ethernet clk rates
*/
#define ETHER_RX_INPUT_CLK_RATE 125000000UL
#define ETHER_MGBE_MAC_DIV_RATE_25G 781250000UL
#define ETHER_MGBE_MAC_DIV_RATE_10G 312500000UL
#define ETHER_MGBE_MAC_DIV_RATE_5G 156250000UL
#define ETHER_MGBE_MAC_DIV_RATE_2_5G 78125000UL
// gbe_pll2_txclkref (644 MHz) --> programmable link TX_CLK divider
// --> link_Tx_clk --> fixed 1/2 gear box divider --> lane TX clk.
#define ETHER_MGBE_TXRX_CLK_XAUI_25G 805664000UL
#define ETHER_MGBE_TX_CLK_USXGMII_10G 644531250UL
#define ETHER_MGBE_TX_CLK_USXGMII_5G 322265625UL
#define ETHER_MGBE_RX_CLK_USXGMII_10G 644531250UL
#define ETHER_MGBE_RX_CLK_USXGMII_5G 322265625UL
#define ETHER_MGBE_TXRX_PCS_CLK_XAUI_25G 390625000UL
#define ETHER_MGBE_TX_PCS_CLK_USXGMII_10G 156250000UL
#define ETHER_MGBE_TX_PCS_CLK_USXGMII_5G 78125000UL
#define ETHER_MGBE_RX_PCS_CLK_USXGMII_10G 156250000UL
#define ETHER_MGBE_RX_PCS_CLK_USXGMII_5G 78125000UL
#define ETHER_EQOS_TX_CLK_2_5G 312500000UL
#define ETHER_EQOS_TX_CLK_1000M 125000000UL
#define ETHER_EQOS_TX_CLK_100M 25000000UL
#define ETHER_EQOS_TX_CLK_10M 2500000UL
#define ETHER_EQOS_UPHY_LX_TX_2_5G_CLK 195312500UL
#define ETHER_EQOS_UPHY_LX_TX_1G_CLK 78125000UL
/**
* @brief 1 Second in Neno Second
@@ -472,6 +478,8 @@ struct ether_priv_data {
struct clk *tx_div_clk;
/** Receive Monitoring clock */
struct clk *rx_m_clk;
/** Transmit Monitoring clock */
struct clk *tx_m_clk;
/** RX PCS monitoring clock */
struct clk *rx_pcs_m_clk;
/** RX PCS input clock */
@@ -651,6 +659,8 @@ struct ether_priv_data {
unsigned int fixed_link;
/** Flag to represent rx_m clk enabled or not */
bool rx_m_enabled;
/** Flag to represent tx_m clk enabled or not */
bool tx_m_enabled;
/** Flag to represent rx_pcs_m clk enabled or not */
bool rx_pcs_m_enabled;
/* Timer value in msec for ether_stats_work thread */

26
drivers/net/ethernet/nvidia/nvethernet/macsec.c
View File

@@ -101,8 +101,8 @@ static int macsec_disable_car(struct macsec_priv_data *macsec_pdata)
PRINT_ENTRY();
if (pdata->osi_core->mac != OSI_MAC_HW_EQOS) {
if (!IS_ERR_OR_NULL(macsec_pdata->mgbe_clk)) {
clk_disable_unprepare(macsec_pdata->mgbe_clk);
if (!IS_ERR_OR_NULL(macsec_pdata->macsec_clk)) {
clk_disable_unprepare(macsec_pdata->macsec_clk);
}
} else {
if (!IS_ERR_OR_NULL(macsec_pdata->eqos_tx_clk)) {
@@ -130,8 +130,8 @@ static int macsec_enable_car(struct macsec_priv_data *macsec_pdata)
PRINT_ENTRY();
if (pdata->osi_core->mac != OSI_MAC_HW_EQOS) {
if (!IS_ERR_OR_NULL(macsec_pdata->mgbe_clk)) {
ret = clk_prepare_enable(macsec_pdata->mgbe_clk);
if (!IS_ERR_OR_NULL(macsec_pdata->macsec_clk)) {
ret = clk_prepare_enable(macsec_pdata->macsec_clk);
if (ret < 0) {
dev_err(dev, "failed to enable macsec clk\n");
goto exit;
@@ -167,8 +167,8 @@ static int macsec_enable_car(struct macsec_priv_data *macsec_pdata)
err_ns_rst:
if (pdata->osi_core->mac != OSI_MAC_HW_EQOS) {
if (!IS_ERR_OR_NULL(macsec_pdata->mgbe_clk)) {
clk_disable_unprepare(macsec_pdata->mgbe_clk);
if (!IS_ERR_OR_NULL(macsec_pdata->macsec_clk)) {
clk_disable_unprepare(macsec_pdata->macsec_clk);
}
} else {
if (!IS_ERR_OR_NULL(macsec_pdata->eqos_rx_clk)) {
@@ -326,10 +326,14 @@ static int macsec_get_platform_res(struct macsec_priv_data *macsec_pdata)
/* Get clks */
if (pdata->osi_core->mac != OSI_MAC_HW_EQOS) {
macsec_pdata->mgbe_clk = devm_clk_get(dev, "mgbe_macsec");
if (IS_ERR(macsec_pdata->mgbe_clk)) {
if (pdata->osi_core->mac_ver == OSI_MGBE_MAC_3_10) {
macsec_pdata->macsec_clk = devm_clk_get(dev, "mgbe_macsec");
} else {
macsec_pdata->macsec_clk = devm_clk_get(dev, "macsec");
}
if (IS_ERR(macsec_pdata->macsec_clk)) {
dev_err(dev, "failed to get macsec clk\n");
ret = PTR_ERR(macsec_pdata->mgbe_clk);
ret = PTR_ERR(macsec_pdata->macsec_clk);
goto exit;
}
} else {
@@ -360,8 +364,8 @@ static void macsec_release_platform_res(struct macsec_priv_data *macsec_pdata)
PRINT_ENTRY();
if (pdata->osi_core->mac != OSI_MAC_HW_EQOS) {
if (!IS_ERR_OR_NULL(macsec_pdata->mgbe_clk)) {
devm_clk_put(dev, macsec_pdata->mgbe_clk);
if (!IS_ERR_OR_NULL(macsec_pdata->macsec_clk)) {
devm_clk_put(dev, macsec_pdata->macsec_clk);
}
} else {
if (!IS_ERR_OR_NULL(macsec_pdata->eqos_tx_clk)) {

8
drivers/net/ethernet/nvidia/nvethernet/macsec.h
View File

@@ -218,11 +218,11 @@ struct nvpkcs_data {
struct macsec_priv_data {
/** Non secure reset */
struct reset_control *ns_rst;
/** MGBE Macsec clock */
struct clk *mgbe_clk;
/** EQOS Macsec TX clock */
/** MGBE/EQOS Macsec clock */
struct clk *macsec_clk;
/** T23x EQOS Macsec TX clock */
struct clk *eqos_tx_clk;
/** EQOS Macsec RX clock */
/** T23x EQOS Macsec RX clock */
struct clk *eqos_rx_clk;
/** Secure irq */
int s_irq;

34
drivers/net/ethernet/nvidia/nvethernet/sysfs.c
View File

@@ -2636,6 +2636,8 @@ static ssize_t ether_phy_iface_mode_show(struct device *dev,
struct osi_core_priv_data *osi_core = pdata->osi_core;
switch (osi_core->phy_iface_mode) {
case OSI_XAUI_MODE_25G:
return scnprintf(buf, PAGE_SIZE, "XAUI-25G\n");
case OSI_XFI_MODE_10G:
return scnprintf(buf, PAGE_SIZE, "XFI-10G\n");
case OSI_XFI_MODE_5G:
@@ -2675,7 +2677,9 @@ static ssize_t ether_phy_iface_mode_store(struct device *dev,
return size;
}
if (strncmp(buf, "XFI-10G", 7) == 0U) {
if (strncmp(buf, "XAUI-25G", 7) == 0U) {
osi_core->phy_iface_mode = OSI_XAUI_MODE_25G;
} else if (strncmp(buf, "XFI-10G", 7) == 0U) {
osi_core->phy_iface_mode = OSI_XFI_MODE_10G;
} else if (strncmp(buf, "XFI-5G", 6) == 0U) {
osi_core->phy_iface_mode = OSI_XFI_MODE_5G;
@@ -2718,9 +2722,19 @@ static ssize_t ether_uphy_gbe_mode_show(struct device *dev,
struct ether_priv_data *pdata = netdev_priv(ndev);
struct osi_core_priv_data *osi_core = pdata->osi_core;
return scnprintf(buf, PAGE_SIZE, "%s\n",
(osi_core->uphy_gbe_mode == OSI_ENABLE) ?
"10G" : "5G");
switch (osi_core->uphy_gbe_mode) {
case OSI_UPHY_GBE_MODE_25G:
return scnprintf(buf, PAGE_SIZE, "25G\n");
case OSI_GBE_MODE_10G:
return scnprintf(buf, PAGE_SIZE, "10G\n");
case OSI_GBE_MODE_5G:
return scnprintf(buf, PAGE_SIZE, "5G\n");
case OSI_GBE_MODE_2_5G:
return scnprintf(buf, PAGE_SIZE, "2_5G\n");
default:
return scnprintf(buf, PAGE_SIZE, "1G\n");
}
}
/**
@@ -2749,10 +2763,16 @@ static ssize_t ether_uphy_gbe_mode_store(struct device *dev,
return size;
}
if (strncmp(buf, "10G", 3) == 0U) {
osi_core->uphy_gbe_mode = OSI_ENABLE;
if (strncmp(buf, "25G", 3) == 0U) {
osi_core->uphy_gbe_mode = OSI_UPHY_GBE_MODE_25G;
} else if (strncmp(buf, "10G", 3) == 0U) {
osi_core->uphy_gbe_mode = OSI_GBE_MODE_10G;
} else if (strncmp(buf, "5G", 2) == 0U) {
osi_core->uphy_gbe_mode = OSI_DISABLE;
osi_core->uphy_gbe_mode = OSI_GBE_MODE_5G;
} else if (strncmp(buf, "2_5G", 4) == 0U) {
osi_core->uphy_gbe_mode = OSI_GBE_MODE_2_5G;
} else if (strncmp(buf, "1G", 2) == 0U) {
osi_core->uphy_gbe_mode = OSI_GBE_MODE_1G;
} else {
dev_err(pdata->dev,
"Invalid value passed. Valid values are 10G or 5G\n");