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nvidia-oot: add support for hypervisor driver
Using this patch we are adding support for hypervisor driver Bug 3595577 JIRA ESLC-6884 Signed-off-by: Manish Bhardwaj <mbhardwaj@nvidia.com> Change-Id: I0fc9b5eed45d584bc658c2613b33968bf8a91eaf Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2779389 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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489
include/soc/tegra/virt/syscalls.h
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489
include/soc/tegra/virt/syscalls.h
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@@ -0,0 +1,489 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#ifndef __TEGRA_SYSCALLS_H__
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#define __TEGRA_SYSCALLS_H__
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#include <soc/tegra/virt/tegra_hv_sysmgr.h>
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#define HVC_NR_READ_STAT 1
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#define HVC_NR_READ_IVC 2
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#define HVC_NR_READ_GID 3
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#define HVC_NR_RAISE_IRQ 4
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#define HVC_NR_READ_NGUESTS 5
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#define HVC_NR_READ_IPA_PA 6
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#define HVC_NR_READ_GUEST_STATE 7
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#define HVC_NR_READ_HYP_INFO 9
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#define HVC_NR_GUEST_RESET 10
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#define HVC_NR_SYSINFO_IPA 13
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#define HVC_NR_TRACE_GET_EVENT_MASK 0x8003U
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#define HVC_NR_TRACE_SET_EVENT_MASK 0x8004U
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#define GUEST_PRIMARY 0
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#define GUEST_IVC_SERVER 0
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#define HVC_NR_CPU_FREQ 0xC6000022
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#define NGUESTS_MAX 16
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#ifndef __ASSEMBLY__
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#if defined(__KERNEL__)
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#include <linux/types.h>
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#endif
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struct tegra_hv_queue_data {
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uint32_t id; /* IVC id */
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uint32_t peers[2];
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uint32_t size;
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uint32_t nframes;
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uint32_t frame_size;
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uint32_t offset;
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uint16_t irq, raise_irq;
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uint64_t trap_ipa; /** @brief IO address used to notify peer endpoint */
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uint64_t msi_ipa; /** @brief MSI address used to notify peer endpoint */
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};
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struct ivc_mempool {
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uint64_t pa;
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uint64_t size;
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uint32_t id;
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uint32_t peer_vmid;
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};
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struct ivc_shared_area {
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uint64_t pa;
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uint64_t size;
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uint32_t guest;
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uint16_t free_irq_start;
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uint16_t free_irq_count;
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};
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struct ivc_info_page {
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uint32_t nr_queues;
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uint32_t nr_areas;
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uint32_t nr_mempools;
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uint32_t padding; /**< @brief reserved for internal use */
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// IMPORTANT: Padding is needed to align
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// sizeof(struct ivc_info_page ) to 64 bits
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uint64_t trap_region_base_ipa; /**< @brief MMIO trap region start address */
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uint64_t trap_region_size; /**< @brief MMIO trap region size */
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uint64_t trap_ipa_stride; /**< @brief MMIO trap IPA stride size */
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uint64_t msi_region_base_ipa; /**< @brief MMIO msi region start address */
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uint64_t msi_region_size; /**< @brief MMIO msi region size */
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uint64_t msi_ipa_stride; /**< @brief MMIO msi IPA stride size */
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/* The actual length of this array is nr_areas. */
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struct ivc_shared_area areas[];
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/*
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* Following the shared array is an array of queue data structures with
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* an entry per queue that is assigned to the guest. This array is
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* terminated by an entry with no frames.
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*
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* struct tegra_hv_queue_data queue_data[nr_queues];
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*/
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/*
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* Following the queue data array is an array of mempool structures
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* with an entry per mempool assigned to the guest.
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*
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* struct ivc_mempool[nr_mempools];
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*/
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};
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static inline struct ivc_shared_area *ivc_shared_area_addr(
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const struct ivc_info_page *info, uint32_t area_num)
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{
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return ((struct ivc_shared_area *) (((uintptr_t) info) + sizeof(*info)))
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+ area_num;
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}
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static inline const struct tegra_hv_queue_data *ivc_info_queue_array(
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const struct ivc_info_page *info)
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{
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return (struct tegra_hv_queue_data *)&info->areas[info->nr_areas];
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}
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static inline const struct ivc_mempool *ivc_info_mempool_array(
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const struct ivc_info_page *info)
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{
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return (struct ivc_mempool *)
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&ivc_info_queue_array(info)[info->nr_queues];
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}
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struct hyp_ipa_pa_info {
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uint64_t base; /* base of contiguous pa region */
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uint64_t offset; /* offset for requested ipa address */
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uint64_t size; /* size of pa region */
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};
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#define HVC_MAX_VCPU 64
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struct trapped_access {
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uint64_t ipa;
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uint32_t size;
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int32_t write_not_read;
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uint64_t data;
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uint32_t guest_id;
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};
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struct hyp_server_page {
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/* guest reset protocol */
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uint32_t guest_reset_virq;
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/* boot delay offsets per VM needed by monitor partition */
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uint32_t boot_delay[NGUESTS_MAX];
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/* hypervisor trace log */
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uint64_t log_ipa;
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uint32_t log_size;
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/* secure-hypervisor trace log */
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uint64_t secure_log_ipa;
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uint32_t secure_log_size;
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/* PCT data */
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uint64_t pct_ipa;
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uint64_t pct_size;
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/* check if the VM is a server or a guest */
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uint32_t is_server_vm;
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/* golden register data */
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uint64_t gr_ipa;
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uint32_t gr_size;
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/* all vm mappings ipa */
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uint64_t mappings_ipa;
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};
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/* For backwards compatibility, alias the old name for hyp_server_name. */
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#define hyp_info_page hyp_server_page
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#ifdef CONFIG_ARM64
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#define _X3_X17 "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", \
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"x13", "x14", "x15", "x16", "x17"
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#define _X4_X17 "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", \
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"x13", "x14", "x15", "x16", "x17"
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static inline int hyp_read_gid(unsigned int *gid)
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{
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register uint64_t r0 asm("x0");
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register uint64_t r1 asm("x1");
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asm("hvc %2"
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: "=r"(r0), "=r"(r1)
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: "i"(HVC_NR_READ_GID)
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: "x2", "x3", _X4_X17);
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*gid = r1;
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return (int)r0;
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}
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static inline int hyp_read_nguests(unsigned int *nguests)
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{
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register uint64_t r0 asm("x0");
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register uint64_t r1 asm("x1");
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asm("hvc %2"
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: "=r"(r0), "=r"(r1)
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: "i"(HVC_NR_READ_NGUESTS)
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: "x2", "x3", _X4_X17);
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*nguests = r1;
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return (int)r0;
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}
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static inline int hyp_read_ivc_info(uint64_t *ivc_info_page_pa)
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{
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register uint64_t r0 asm("x0");
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register uint64_t r1 asm("x1");
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asm("hvc %2"
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: "=r"(r0), "=r"(r1)
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: "i"(HVC_NR_READ_IVC)
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: "x2", "x3", _X4_X17);
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*ivc_info_page_pa = r1;
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return (int)r0;
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}
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static inline int hyp_read_ipa_pa_info(struct hyp_ipa_pa_info *info,
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unsigned int guestid, uint64_t ipa)
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{
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register uint64_t r0 asm("x0") = guestid;
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register uint64_t r1 asm("x1") = ipa;
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register uint64_t r2 asm("x2");
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register uint64_t r3 asm("x3");
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asm("hvc %4"
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: "+r"(r0), "+r"(r1), "=r"(r2), "=r"(r3)
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: "i"(HVC_NR_READ_IPA_PA)
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: _X4_X17);
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info->base = r1;
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info->offset = r2;
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info->size = r3;
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return (int)r0;
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}
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static inline int hyp_raise_irq(unsigned int irq, unsigned int vmid)
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{
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register uint64_t r0 asm("x0") = irq;
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register uint64_t r1 asm("x1") = vmid;
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asm volatile("hvc %1"
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: "+r"(r0)
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: "i"(HVC_NR_RAISE_IRQ), "r"(r1)
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: "x2", "x3", _X4_X17);
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return (int)r0;
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}
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static inline int hyp_read_guest_state(unsigned int vmid, unsigned int *state)
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{
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register uint64_t r0 asm("x0") = vmid;
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register uint64_t r1 asm("x1");
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asm("hvc %2"
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: "+r"(r0), "=r"(r1)
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: "i"(HVC_NR_READ_GUEST_STATE)
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: "x2", _X3_X17);
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*state = (unsigned int)r1;
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return (int)r0;
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}
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static inline int hyp_read_hyp_info(uint64_t *hyp_info_page_pa)
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{
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register uint64_t r0 asm("x0");
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register uint64_t r1 asm("x1");
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asm("hvc %2"
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: "=r"(r0), "=r"(r1)
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: "i"(HVC_NR_READ_HYP_INFO)
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: "x2", "x3", _X4_X17);
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*hyp_info_page_pa = r1;
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return (int)r0;
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}
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static inline int hyp_guest_reset(unsigned int id,
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struct hyp_sys_state_info *out)
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{
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register uint64_t r0 asm("x0") = id;
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register uint64_t r1 asm("x1");
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register uint64_t r2 asm("x2");
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register uint64_t r3 asm("x3");
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asm volatile("hvc %4"
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: "+r"(r0), "=r"(r1),
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"=r"(r2), "=r"(r3)
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: "i"(HVC_NR_GUEST_RESET)
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: _X4_X17);
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if (out != NULL) {
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out->sys_transition_mask = (uint32_t)r1;
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out->vm_shutdown_mask = (uint32_t)r2;
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out->vm_reboot_mask = (uint32_t)r3;
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}
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return (int)r0;
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}
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static inline uint64_t hyp_sysinfo_ipa(void)
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{
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register uint64_t r0 asm("x0");
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asm("hvc %1"
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: "=r"(r0)
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: "i"(HVC_NR_SYSINFO_IPA)
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: "x1", "x2", "x3", _X4_X17);
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return r0;
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}
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static inline int hyp_read_freq_feedback(uint64_t *value)
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{
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register uint64_t r0 asm("x0") = HVC_NR_CPU_FREQ;
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register uint64_t r1 asm("x1") = 1U;
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asm volatile("hvc #0"
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: "+r"(r0), "+r"(r1)
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:
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: "x2", "x3", _X4_X17);
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if (r0 == 1 && value != NULL)
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*value = r1;
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return (int16_t)r0;
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}
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static inline int hyp_read_freq_request(uint64_t *value)
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{
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register uint64_t r0 asm("x0") = HVC_NR_CPU_FREQ;
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register uint64_t r1 asm("x1") = 0U;
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asm volatile("hvc #0"
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: "+r"(r0), "+r"(r1)
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:
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: "x2", "x3", _X4_X17);
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if (r0 == 1 && value != NULL)
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*value = r1;
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return (int16_t)r0;
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}
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static inline int hyp_write_freq_request(uint64_t value)
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{
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register uint64_t r0 asm("x0") = HVC_NR_CPU_FREQ;
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register uint64_t r1 asm("x1") = 2U;
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register uint64_t r2 asm("x2") = value;
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asm volatile("hvc #0"
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: "+r"(r0)
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: "r"(r1), "r"(r2)
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: "x3", _X4_X17);
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return (int16_t)r0;
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}
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static inline int hyp_pct_cpu_id_read_freq_feedback(uint8_t cpu_id,
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uint64_t *value)
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{
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register uint64_t r0 asm("x0") = HVC_NR_CPU_FREQ;
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register uint64_t r1 asm("x1") = 4U;
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register uint64_t r2 asm("x2") = cpu_id;
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asm volatile("hvc #0"
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: "+r"(r0), "+r"(r1)
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: "r"(r2)
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: "x3", _X4_X17);
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if (r0 == 1 && value != 0)
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*value = r1;
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return (int16_t)r0;
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}
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static inline int hyp_pct_cpu_id_read_freq_request(uint8_t cpu_id,
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uint64_t *value)
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{
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register uint64_t r0 asm("x0") = HVC_NR_CPU_FREQ;
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register uint64_t r1 asm("x1") = 3U;
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register uint64_t r2 asm("x2") = cpu_id;
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asm volatile("hvc #0"
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: "+r"(r0), "+r"(r1)
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: "r"(r2)
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: "x3", _X4_X17);
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if (r0 == 1 && value != 0)
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*value = r1;
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return (int16_t)r0;
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}
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static inline int hyp_pct_cpu_id_write_freq_request(uint8_t cpu_id,
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uint64_t value)
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{
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register uint64_t r0 asm("x0") = HVC_NR_CPU_FREQ;
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register uint64_t r1 asm("x1") = 5U;
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register uint64_t r2 asm("x2") = value;
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register uint64_t r3 asm("x3") = cpu_id;
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asm volatile("hvc #0"
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: "+r"(r0)
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: "r"(r1), "r"(r2), "r"(r3)
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: _X4_X17);
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return (int16_t)r0;
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}
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static inline uint8_t hyp_get_cpu_count(void)
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{
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register uint64_t r0 asm("x0") = HVC_NR_CPU_FREQ;
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register uint64_t r1 asm("x1") = 6U;
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asm volatile("hvc #0"
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: "+r"(r0), "+r"(r1)
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:
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: "x2", "x3", _X4_X17);
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if (r0 == 1)
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return r1;
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return 0;
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}
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static __attribute__((always_inline)) inline void hyp_call44(uint16_t id,
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uint64_t args[4])
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{
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register uint64_t x0 asm("x0") = args[0];
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register uint64_t x1 asm("x1") = args[1];
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register uint64_t x2 asm("x2") = args[2];
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register uint64_t x3 asm("x3") = args[3];
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asm volatile("HVC %[imm16]"
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: "+r"(x0), "+r"(x1), "+r"(x2), "+r"(x3)
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:
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[imm16] "i"(((uint32_t)id)));
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args[0] = x0;
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args[1] = x1;
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args[2] = x2;
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args[3] = x3;
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}
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static inline int hyp_trace_get_mask(uint64_t *value)
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{
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uint64_t args[4] = { 0U, 0U, 0U, 0U };
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hyp_call44(HVC_NR_TRACE_GET_EVENT_MASK, args);
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if (args[0] == 0U)
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*value = args[1];
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return (int) args[0];
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}
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|
||||
static inline int hyp_trace_set_mask(uint64_t mask)
|
||||
{
|
||||
uint64_t args[4] = { mask, 0U, 0U, 0U };
|
||||
|
||||
hyp_call44(HVC_NR_TRACE_SET_EVENT_MASK, args);
|
||||
return (int) args[0];
|
||||
}
|
||||
|
||||
#undef _X3_X17
|
||||
#undef _X4_X17
|
||||
|
||||
#else
|
||||
|
||||
int hyp_read_gid(unsigned int *gid);
|
||||
int hyp_read_nguests(unsigned int *nguests);
|
||||
int hyp_read_ivc_info(uint64_t *ivc_info_page_pa);
|
||||
int hyp_read_ipa_pa_info(struct hyp_ipa_pa_info *info, int guestid,
|
||||
uint64_t ipa);
|
||||
int hyp_raise_irq(unsigned int irq, unsigned int vmid);
|
||||
uint64_t hyp_sysinfo_ipa(void);
|
||||
|
||||
/* ASM prototypes */
|
||||
extern int hvc_read_gid(void *);
|
||||
extern int hvc_read_ivc_info(int *);
|
||||
extern int hvc_read_ipa_pa_info(void *, int guestid, uint64_t ipa);
|
||||
extern int hvc_read_nguests(void *);
|
||||
extern int hvc_raise_irq(unsigned int irq, unsigned int vmid);
|
||||
|
||||
#endif /* CONFIG_ARCH_ARM64 */
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* __TEGRA_SYSCALLS_H__ */
|
||||
Reference in New Issue
Block a user