From 6d78ed22c7a44f8911ce65903441992663ffc07c Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Thu, 22 Aug 2024 06:02:51 +0000 Subject: [PATCH] memory: tegra: Restrict access to non-PERMUX registers SOC-HWPM shouldn't request read/write to non-PERMUX registers of MC-Channels or MSS-HUB. If it does, restrict the access and return error. Bug 4704678 Change-Id: I03bae82dfcf4bb9b63e135132b03b5b1e67632f1 Signed-off-by: Ashish Mhetre Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3198241 GVS: buildbot_gerritrpt Reviewed-by: Pritesh Raithatha Reviewed-by: Ketan Patil --- drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c b/drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c index fb786154..7024f51f 100644 --- a/drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c +++ b/drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c @@ -15,6 +15,10 @@ #include +#define MC_MCC_CTL_PERFMUX_OFFSET 0x8914 +#define MC_MCC_DP_PERFMUX_OFFSET 0x8918 +#define MC_CBRIDGE_PERFMUX_OFFSET 0x891c + #define MAX_MC_CHANNELS 17 // Broadcast Channel + 16 MC Channels static struct tegra_soc_hwpm_ip_ops hwpm_ip_ops; @@ -57,10 +61,16 @@ static int tegra_mc_hwpm_reg_op(void *ip_dev, } if (inst_element_index >= mc->no_ch) { - pr_err("Incorrect channel number: %u\n", inst_element_index); + dev_err(dev, "Incorrect channel number: %u\n", inst_element_index); return -EINVAL; } + if (reg_offset != MC_MCC_CTL_PERFMUX_OFFSET && reg_offset != MC_MCC_DP_PERFMUX_OFFSET && + reg_offset != MC_CBRIDGE_PERFMUX_OFFSET) { + dev_err(dev, "SOC-HWPM requesting access to prohibited register"); + return -EPERM; + } + if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_READ) { *reg_data = mc_readl(mc, inst_element_index, (u32)reg_offset); } else if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_WRITE) {