From 6e66abaff3f7b77659484e32c0423d908a1fd453 Mon Sep 17 00:00:00 2001
From: Laxman Dewangan <ldewangan@nvidia.com>
Date: Thu, 5 May 2022 12:05:15 +0530
Subject: [PATCH] Documentation: Add DT binding doc for Tegra fuse-burn

Add DT binding document for NVIDIA Tegra fuse burn controller.

Bug 3631213

Change-Id: I02b40f4b23d84b81d1fd7e870596a82a4f3fd96f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2707661
Reviewed-by: Kartik . <kkartik@nvidia.com>
GVS: Gerrit_Virtual_Submit
---
 .../bindings/soc/nvidia/tegra/fuse-burn.yaml  | 86 +++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/nvidia/tegra/fuse-burn.yaml

diff --git a/Documentation/devicetree/bindings/soc/nvidia/tegra/fuse-burn.yaml b/Documentation/devicetree/bindings/soc/nvidia/tegra/fuse-burn.yaml
new file mode 100644
index 00000000..9e20de14
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/nvidia/tegra/fuse-burn.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/nvidia/tegra/fuse-burn.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra fuse burn DT binding
+
+maintainers:
+  - Laxman Dewangan <ldewangan@nvidia.com>
+
+description: |
+   This driver burn the fuse on NVIDIA Tegra SOCs.
+
+properties:
+  compatible:
+    enum:
+      - nvidia,tegra194-efuse-burn
+      - nvidia,tegra234-efuse-burn
+
+  reg:
+    items:
+      - description: Base register address and size of the MISC.
+      - description: Base register address and size of the Fuse.
+
+  clocks:
+    maxItems: 2
+    description: |
+       Two entries, first one is for fuse clock and secon one is for the PGM clock.
+
+  clock-names:
+     description: |
+        Name of the clock source. The valid names are "fuse-clk" and "pgm-clk".
+
+  nvidia,temp-range:
+     $ref: /schemas/types.yaml#/definitions/uint32-array
+     description: |
+        Temperature range in degC. It has two entries for lower and upper range.
+
+  nvidia,redundant-aid-war:
+     $ref: /schemas/types.yaml#/definitions/flag
+     description: |
+        If this property present then add WAR for the AID fuse to have redundancy.
+
+  thermal-zone:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+       Thermal zone ID for the fuse.
+
+  thermal-zone-type:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: |
+       Thermal zone type.
+
+  nvidia,bpmp:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: |
+      Handle of the BPMP node.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - nvidia,bpmp
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #define TEGRA234_CLK_FUSE         40U
+    #define TEGRA234_CLK_CLK_M        14U
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        efuse-burn@3810000 {
+           compatible = "nvidia,tegra234-efuse-burn";
+           reg = <0x0 0x0c3a0000 0x0 0x10000>,
+                 <0x0 0x03810000 0x0 0x19000>;
+           clocks = <&bpmp_clks TEGRA234_CLK_FUSE>,
+                 <&bpmp_clks TEGRA234_CLK_CLK_M>;
+           clock-names = "fuse-clk", "pgm-clk";
+           nvidia,bpmp = <&bpmp>;
+        };
+    };
+...