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platform: tegra: Remove EMC register access for HV

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EMC registers are currently accessed to get DRAM parameters.
As these are platform specific and static, DRAM parameters are added in
device-tree. In case of hypervisor environment, read DRAM properties
from device-tree instead of accessing EMC registers.
Also, MC and EMC register access by kernel is going to be blocked from
hypervisor. So, remove access to these registers.

Bug 3938091

Change-Id: I8a85bef7c34a919a48b3f0999f631f264540585a
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2848653
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Ashish Mhetre
2023-01-25 12:56:30 +05:30
committed by mobile promotions
parent 8efaee4e42
commit 7a504c1633
1 changed files with 53 additions and 28 deletions
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39
drivers/platform/tegra/mc-utils/mc-utils.c
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@@ -1,5 +1,5 @@
/** /**
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
@@ -21,6 +21,9 @@
#include <linux/version.h> #include <linux/version.h>
#include <soc/tegra/fuse.h> #include <soc/tegra/fuse.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h>
#include <soc/tegra/virt/hv-ivc.h>
#define BYTES_PER_CLK_PER_CH 4 #define BYTES_PER_CLK_PER_CH 4
#define CH_16 16 #define CH_16 16
@@ -80,7 +83,6 @@
struct emc_params { struct emc_params {
u32 rank; u32 rank;
u32 ecc; u32 ecc;
u32 ch;
u32 dram; u32 dram;
}; };
@@ -292,12 +294,27 @@ static void tegra_mc_utils_debugfs_init(void)
} }
#endif #endif
static u32 get_dram_dt_prop(struct device_node *np, const char *prop)
{
u32 val;
int ret;
ret = of_property_read_u32(np, prop, &val);
if (ret) {
pr_err("failed to read %s\n", prop);
return ~0U;
}
return val;
}
static int __init tegra_mc_utils_init(void) static int __init tegra_mc_utils_init(void)
{ {
u32 dram, ch, ecc, rank; u32 dram, ch, ecc, rank;
void __iomem *emc_base; void __iomem *emc_base;
void __iomem *mcb_base; void __iomem *mcb_base;
if (!is_tegra_hypervisor_mode()) {
emc_base = ioremap(EMC_BASE, 0x00010000); emc_base = ioremap(EMC_BASE, 0x00010000);
dram = readl(emc_base + EMC_FBIO_CFG5_0) & DRAM_MASK; dram = readl(emc_base + EMC_FBIO_CFG5_0) & DRAM_MASK;
mcb_base = ioremap(MCB_BASE, MCB_SIZE); mcb_base = ioremap(MCB_BASE, MCB_SIZE);
@@ -308,10 +325,6 @@ static int __init tegra_mc_utils_init(void)
ch = readl(mcb_base + MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0); ch = readl(mcb_base + MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0);
ch &= CH_MASK; ch &= CH_MASK;
/*
* TODO: For non orin chips MC_ECC_CONTROL_0 is not present, hence set
* ecc to 0 and cleanup this once we have chip specific mc_utils driver.
*/
ecc = readl(mcb_base + MC_ECC_CONTROL_0) & ECC_MASK; ecc = readl(mcb_base + MC_ECC_CONTROL_0) & ECC_MASK;
rank = readl(mcb_base + MC_EMEM_ADR_CFG_0) & RANK_MASK; rank = readl(mcb_base + MC_EMEM_ADR_CFG_0) & RANK_MASK;
@@ -324,8 +337,20 @@ static int __init tegra_mc_utils_init(void)
ch_num++; ch_num++;
ch >>= 1; ch >>= 1;
} }
} else {
struct device_node *np = of_find_compatible_node(NULL, NULL, "nvidia,tegra234-mc");
if (!np) {
pr_err("mc-utils: Not able to find MC DT node\n");
return -ENODEV;
}
ecc = get_dram_dt_prop(np, "dram_ecc");
rank = get_dram_dt_prop(np, "dram_rank");
dram = get_dram_dt_prop(np, "dram_lpddr");
ch_num = get_dram_dt_prop(np, "dram_channels");
}
emc_param.ch = ch;
emc_param.ecc = ecc; emc_param.ecc = ecc;
emc_param.rank = rank; emc_param.rank = rank;
emc_param.dram = dram; emc_param.dram = dram;